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Code No: 54206/MT M.Tech. II-Semester Examinations, August/September-2007. LOW POWER VLSI DESIGN (Embedded Systems, Digital Electronics & Communication Systems and VLSI System Design) Time: 3 hours Max. Marks: 60 Answer any FIVE questions All questions carry equal marks --1.a] b] 2.a] b] 3. 4.a] b] 5. 6. What are the various advantages and limitations of the Silicon–onInsulator Technology ? Explain about shallow Trench Isolation (SIT) technique. How threshold Voltage adjustments can be carried out for CMOS devices? Explain with the help of necessary equations. With the help of sketches explain about the Retrograde–Well CMOS process. Describe the Low – Voltage, Low- power CMOS SOI process. Describe the dynamic characteristics of MOS transistor, using necessary equations. Describe the characteristics of Secondary MOS FET behavior. Draw the circuit for common–Emitter configuration and explain its characteristics. Bi CMOS driver
Explain about the characteristics of Bi CMOS a] Circuits utilizing lateral p-n-p BJTs in PMOS structures. b] Give the performance evaluation of merged Bi CMOS logic gates. How the weak points of conventional Bi CMOS logic gates are overcome by these circuits ? Explain about the Functionality Theme and Synchronous themes of latches and Flip – Flops. What are the Performance measures of latches and Flip–Flops. Write notes on any TWO a] MOSFET in a Hybrid – mode environment. b] ESD–free Bi CMOS c] Bipolar SPICE Model ^*^*^
7.a] b] 8.