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Timing Closure Guide

Timing Closure Guide

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Sections

  • Introduction
  • Recommended Timing Closure Flow
  • Software
  • Foundation Flow
  • Data Preparation and Validation
  • Data Preparation
  • Data Validation
  • Determining and Setting the RC Scaling Factors
  • Data Preparation and Validation for Low Power Designs
  • Flow Preparation
  • Setting the Design Mode
  • Extraction
  • Timing Analysis
  • Pre-Placement Optimization
  • Floorplanning and Initial Placement
  • Ensuring Routability
  • Validating the Floorplan
  • Timing-Driven Placement
  • Pre-CTS Optimization
  • Guidelines for Pre-CTS Optimization
  • Pre-CTS optDesign Command Sequences
  • Path Group Optimization
  • Checking & Debugging Timing
  • Clock Tree Synthesis
  • Creating the Clock Specification File
  • Synthesizing the Clock Tree
  • Analyzing and Debugging the Clock Tree Results
  • Optimizing the Clock Tree
  • Clock Specification File Example
  • Post-CTS Optimization
  • Post-CTS Optimization Command Sequences
  • Hold Optimization
  • Checking Timing
  • Detailed Routing
  • Improving Timing during Routing
  • Routing Command Sequence
  • PostRoute Extraction
  • Post-Route Optimization
  • Post-Route Optimization Command Sequences
  • Optimizing With 3rd Party SPEF or SDF
  • Timing Sign Off
  • Additional Resources

EDI Timing Closure Guide

Cadence Design Systems, Inc.

Application Note

Timing Closure Guide

Encounter Digital Implementation (EDI) System, 10.1
Rev – 1.0 August - 2011

COPYRIGHT © 2011, CADENCE DESIGN SYSTEMS, INC.
ALL RIGHTS RESERVED. PAGE 1

EDI Timing Closure Guide

Table Of Content
Introduction .................................................................................................................. 4 Recommended Timing Closure Flow ........................................................................... 4 Software ................................................................................................................... 4 Foundation Flow....................................................................................................... 4 Data Preparation and Validation .................................................................................. 5 Data Preparation ...................................................................................................... 5 Data Validation ......................................................................................................... 8 Determining and Setting the RC Scaling Factors ................................................... 12 Data Preparation and Validation for Low Power Designs....................................... 12 Flow Preparation........................................................................................................ 13 Setting the Design Mode ........................................................................................ 13 Extraction ............................................................................................................... 14 Timing Analysis ...................................................................................................... 15 Pre-Placement Optimization ...................................................................................... 16 Floorplanning and Initial Placement ........................................................................... 17 Ensuring Routability ............................................................................................... 18 Validating the Floorplan ......................................................................................... 20 Timing-Driven Placement ....................................................................................... 20 Pre-CTS Optimization ................................................................................................ 23 Guidelines for Pre-CTS Optimization ..................................................................... 23 Pre-CTS optDesign Command Sequences............................................................ 24 Path Group Optimization ........................................................................................ 27 Checking & Debugging Timing ............................................................................... 28 Clock Tree Synthesis ................................................................................................. 30 Creating the Clock Specification File...................................................................... 31 Synthesizing the Clock Tree .................................................................................. 32 Analyzing and Debugging the Clock Tree Results ................................................. 36 Optimizing the Clock Tree ...................................................................................... 36 Clock Specification File Example ........................................................................... 37 Post-CTS Optimization .............................................................................................. 39 Post-CTS Optimization Command Sequences ...................................................... 40 Hold Optimization ................................................................................................... 41
COPYRIGHT © 2011, CADENCE DESIGN SYSTEMS, INC.
ALL RIGHTS RESERVED. PAGE 2

EDI Timing Closure Guide

Checking Timing .................................................................................................... 45 Detailed Routing ........................................................................................................ 45 Improving Timing during Routing ........................................................................... 45 Routing Command Sequence ................................................................................ 45 PostRoute Extraction ............................................................................................. 47 Checking Timing .................................................................................................... 48 Post-Route Optimization ............................................................................................ 48 Data Preparation .................................................................................................... 49 Post-Route Optimization Command Sequences .................................................... 50 Checking Timing .................................................................................................... 52 Optimizing With 3rd Party SPEF or SDF ................................................................ 52 Timing Sign Off .......................................................................................................... 53 Additional Resources ................................................................................................. 54

COPYRIGHT © 2011, CADENCE DESIGN SYSTEMS, INC.
ALL RIGHTS RESERVED. PAGE 3

EDI Timing Closure Guide

Introduction
Achieving timing closure on a design is the process of creating a design implementation that is free from logical, physical, and design rule violations and meets or exceeds the timing specifications for the design. For a production chip, all physical effects, such as metal fill and coupling, must be taken into account before you can confirm that timing closure has been achieved. Timing Closure is not just about timing optimization. It is a complete flow that has to converge, including placement, timing optimization, clock tree synthesis (CTS), routing and SI fixing. Each step has to reach the expected targets or else timing closure will likely not be achieved. This document discusses each step in the implementation flow as it relates to timing closure in EDI 10.1, and provides recommended settings specific to high performance, congested or high utilization designs.

Recommended Timing Closure Flow
Below is a high level diagram showing the steps in the timing closure flow:

Software The EDI System software is constantly being improved to provide better quality of results, reliability and ease of use. To ensure you're running with the latest improvement we recommend running with the latest software version available from http://downloads.cadence.com. Foundation Flow If you've developed your own flow scripts, you know maintaining and updating them can be time consuming and error prone. Also, ensuring you're running with the latest recommended commands and options can be challenging. Therefore, we recommend using the Foundation Flow scripts. The Foundation Flow provides Cadence-recommended procedures for implementing flat, hierarchical, and low-power/CPF designs using the EDI
COPYRIGHT © 2011, CADENCE DESIGN SYSTEMS, INC.
ALL RIGHTS RESERVED. PAGE 4

EDI Timing Closure Guide

System software. The Foundation Flow is a starting point for building an implementation environment, but you can augment them with designspecific content. Utilizing the Foundation Flow helps achieve timing closure because it provides the latest recommended flow which you can further customize based on your design requirements. If you are new to the Foundation Flow, we recommend you start with the Foundation Flow video demonstrations. These provide examples of setting up and using the flows. They are accessible from within the EDI System GUI by selecting Flows - Foundation Flow Demo.

Data Preparation and Validation
This section outlines the data (libraries, constraints, netlist, etc.) required for implementing the timing closure flow and how to validate that data. The goals of data preparation and validation include:
• • • • •

Confirming that the EDI System has a complete and consistent set of design data (all library views and versions must be consistent). Ensuring that all tools in the flow interpret the timing constraints consistently. Making sure logically equivalent cells are defined properly. Creating a capacitance table file that matches the process technology. Correlating parasitics among the prototyping and sign-off extraction tools.

Data Preparation This section lists the data required and data setup recommended for the timing closure flow. Timing Libraries

Every cell used in the design should be defined in the timing library. o If multiple delay corners are being analyzed then each cell needs to be characterized for each corner. o EDI System supports Non-linear Delay Models (NLDM), ECSM and CCS.  ECSM/CCS require the Signal Storm delay calculator (setDelayCalMode -engine signalStorm)  CCS/ECSM are less pessimistic than NLDM and therefore you can gain about 5% to 10% of the clock period on the slack using CCS/ECSM libraries.

COPYRIGHT © 2011, CADENCE DESIGN SYSTEMS, INC.
ALL RIGHTS RESERVED. PAGE 5

ALL RIGHTS RESERVED. CADENCE DESIGN SYSTEMS. materials. profiles.EDI Timing Closure Guide Physical Libraries • • • You need to have an abstract defined for every cell in either a LEF file or OpenAccess database. o Run uniquifyNetlist at the Linux command line to uniquify the netlist. If assign statements exist. and outputs a capacitance table file. Alternatively. and so forth). The Interconnect Technology (ICT) file describes the detailed process information for a given technology (layer thicknesses. These can be defined in the LEF or added within EDI System. the generateCapTbl command can be used to generate the cap table. Capacitance Table File A capacitance table is used by EDI System to accurately extract parasitics. COPYRIGHT © 2011. Confirm you have the latest technology LEF from your library vendor or foundry. Define Non-Default Rules (NDRs) for routing as needed. The technology LEF should have an optimized set of vias to be used for routing. You should have an SDC file for each operational mode required for analysis. Any non-default rules for the design should be defined in the LEF file you are using. • The netlist should also be unique. Verilog Netlist • Check the Verilog netlist for assign statements. Timing Constraints Timing constraints in the form of SDCs are required. PAGE 6 . generateCapTbl reads a detailed process description file in Interconnect Technology (ICT) format and a LEF technology file. o And set "setImportMode -bufferFeedThruAssign true". use the following procedure to enable optimization to work on those nets: o Run "setDoAssign on" before loading the design data OR use "set rda_Input(assign_buffer) {1}" in the configuration file (these commands do the same thing). A cap table is required for each RC corner to be analyzed. dielectric constants. INC. You may obtain the cap table(s) from your foundry.

use it and do not recreate it.EDI Timing Closure Guide The capacitance table file consists of two parts: • Basic Capacitance Table Provides a table of spacing versus capacitance information for each layer.ict -output process. A capacitance table file (basic or extended) is processspecific and not design dependent. Multi-Mode Multi-Corner (MMMC) Setup Multi-Mode Multi-Corner (MMMC) setup is required for optimizing designs over multiple operating conditions. COPYRIGHT © 2011. Extended Capacitance Table Provides encoded extraction patterns that are derived using a 3D field solver which provides much greater accuracy during detailed extraction.xCapTbl QRC Tech File A QRC technology file (ICT file) is required in order to run turbo-QRC (tQRC). so it only needs to be created once per technology. A QRC tech file is required for each RC corner to be analyzed. This will be required in EDI System 11.lef -ict process. • The following example shows how to generate an extended capacitance table using the default field solver (Coyote).1. MMMC setup is also required for accurate push-out/pull-in reporting during Signal Integrity (SI) analysis. Therefore. CADENCE DESIGN SYSTEMS. integrated QRC (iQRC) or standalone QRC. If a capacitance table already exists for your process. ALL RIGHTS RESERVED. See the chapter Performing Multi-Mode Multi-Corner Timing Analysis and Optimization in the EDI System User Guide for information on defining the MMMC environment. Signal Integrity (SI) Libraries SI libraries in the form of cdB's are required for SI analysis and optimization. INC. we highly recommend setting up your analysis views using the MMMC environment. These can be generated from SPICE using the make_cdb command. The flow described in this document assumes you are running in MMMC mode. generateCapTbl -lef tech. PAGE 7 .

Run loadConfig to import the libraries. PAGE 8 .conf loadConfig executes a number of checks to validate the data and highlight problems. • A blackbox is an instance declaration in the netlist for which no module or macro definition is found. The following is reported for blackbox (empty) modules: *** Found empty module (bbox). The Log Viewer expands/collapses the log output by command and color codes messages to make them easy to identify. We recommend using the Log Viewer (Tools .EDI Timing Closure Guide Data Validation This section explains how to identify problems when importing the data and checks you can run to catch data issues early in the flow. It is important you review the log file to understand and resolve warnings and error messages it reports. If there are blackboxes reported. Unless your design is being done using a blackbox style of floorplanning. there should be no blackboxes in the design. ALL RIGHTS RESERVED. • Verify the netlist is unqiue. The following is reported if it is not unique: *** Netlist is NOT unique. Following are things to look for when reviewing the loadConfig output: • loadConfig reports cells in the LEF which are not defined in the timing libraries.Log Viewer) to review the loadConfig results. Loading the Design Once you have prepared the necessary data you are ready to import it. COPYRIGHT © 2011. CADENCE DESIGN SYSTEMS. INC. loadConfig design. and make sure you include the LEF file that defines the macro being referenced in the netlist. be sure to load the Verilog file that defines the logic module. netlist and timing environment. Look for the following and confirm if these cells need to be analyzed for timing: **WARN: (ENCSYC-2): Timing is not defined for cell INVXL.

The cell will only be used for analysis. check for the following problems: • Unsupported constraints o The EDI System software may not support the SDC constraints being used with the design.EDI Timing Closure Guide • By default. it identifies buffers. inverters and delay cells. If the constraints are not supported. CADENCE DESIGN SYSTEMS. look for cells which do not have a function defined for them: No function defined for cell 'HOLDX1'. ALL RIGHTS RESERVED. or the constraints may not match the netlist. inverters and delay cells are properly identified. it uses the "function" statement to determine cells which are functionally equivalent and can be swapped during optimization. Additionally. they may need COPYRIGHT © 2011. Below is an example of what you'll see: List of usable buffers: BUFX2 BUFX1 BUFX12 BUFX16 BUFX20 BUFX3 BUFX4 BUFX8 BUFXL CLKBUFX2 CLKBUFX1 CLKBUFX12 CLKBUFX16 CLKBUFX20 CLKBUFX3 CLKBUFX4 CLKBUFX8 CLKBUFXL Total number of usable buffers: 18 List of unusable buffers: Total number of unusable buffers: 0 List of usable inverters: CLKINVX2 CLKINVX1 CLKINVX12 CLKINVX16 CLKINVX20 CLKINVX3 CLKINVX4 CLKINVX8 CLKINVXL INVX1 INVX2 INVX12 INVX16 INVX20 INVX3 INVXL INVX4 INVX8 Total number of usable inverters: 18 List of unusable inverters: Total number of unusable inverters: 0 List of identified usable delay cells: DLY2X1 DLY1X1 DLY4X1 DLY3X1 Total number of identified usable delay cells: 4 List of identified unusable delay cells: Total number of identified unusable delay cells: 0 Also. After running loadConfig. INC. Review the log file to confirm the buffers. the loadConfig command also checks the syntax of timing constraints. PAGE 9 . This means instead of relying on the "footprint" definitions inside the timing libraries. Inconsistencies in how the cell functions are defined can lead to suboptimal or erroneous optimization results. Checking Timing Constraint Syntax In addition to checking the libraries. EDI System utilizes a "footprintless" flow.

 An incorrect type of object is being passed to a constraint. INC. set_ideal_network -> will prevent optimization on these nets o set_propagated_clock -> will limit preCTS optimization by not allowing resize on sequential elements. CK or D register pin) to define starting and endpoints of set_false_path and set_multicycle_path. or nets that are not found in the netlist. and a new set of constraints and/or a new netlist needs to be obtained. A combinatorial pin or a Q register pin is not valid. Set this only after clock trees are inserted.  Illegal endpoints are used in assertions.  The netlist and constraints are out of sync. set_dont_touch -> confirm that the proper settings are used o Have a constraint file for every mode required for signoff timing analysis o Understand and adjust clock uncertainty depending on the stage of the design flow (preCTS / postCTS / postRoute / signoff). Use the primary IOs (top-level ports. o The following are possible causes for ignored constraints. cells. • Ignored timing constraints o Syntax errors can cause the tools to ignore certain constraints resulting in the misinterpretation of important timing considerations. o set_dont_use. Check for warnings or errors about unaccepted SDC constraints. CADENCE DESIGN SYSTEMS. then consider the following possible causes:  There could be a naming convention problem in the constraint file. ALL RIGHTS RESERVED.EDI Timing Closure Guide to be re-expressed (if possible) in constraints that the EDI System software does support. Other things to consider when defining constraints: o set_ideal_net. • COPYRIGHT © 2011.  A design object is not found.  An option is being used incorrectly or an unknown option is used. PAGE 10 . If the constraints refer to pins.

ICT. You can review this file to see which cells are identified as logically equivalent. To validate timing constraints. COPYRIGHT © 2011. Make sure the cap table. spacings and pitches should be consistent between the files. of how much effort will be required to close timing and whether the timing constraints are valid for the design. Additionally. and LEF files match. Use correct temperature for resistance extraction. This ensures the cap table information is used most effectively by extraction. use the command: timeDesign -prePlace -outDir preplaceTimingReports This command generates a quick timing report using zero wire load and provides a first indication. Checking Logically Equivalent Cells Available for Optimization • • Run "checkFootPrint" to report any problems with footprint functions. you can run the command "check_timing -verbose" to report timing problems the Common Timing Engine (CTE) sees. it is also important to ensure that the timing constraints are valid for the design. run checkFootPrint again to verify the file you loaded does not have problems. ALL RIGHTS RESERVED.EDI Timing Closure Guide Cap Table Checks • • • Make sure the cap table is current and generated with a recent version of generateCapTbl. If you made updates. CADENCE DESIGN SYSTEMS. widths. PAGE 11 . o You can edit the footprints file if needed and run "loadFootPrint infile file_name" to load it. the loadConfig command checks the syntax of specified timing constraints. However. During pre-placement timing analysis. before placement and routing. high fanout nets are temporarily set as ideal so that more immediate timing issues can be addressed first. A good first-pass method is to check the zero wire-load model timing. o If there are problems reported run "reportFootPrint -outfile file_name" command to create a footprints file. Validating Timing Constraints As described in the previous section. The layer names. INC.

CADENCE DESIGN SYSTEMS. Please see the solution How to Generate Scaling Factors for RC Correlation for the steps to generate the correlation factors with Ostrich. Use Ostrich to obtain the parasitic measurements to determine the appropriate scaling factors. o When using CPF most of the MMMC setup is defined within the CPF. the recommended flow is to enable leakage optimization at the beginning of the flow and allow the tool to manage the optimization.EDI Timing Closure Guide checkDesign command You can run "checkDesign -all" to check the design after loadConfig. Delay corner names are 'CPF-generated' so keep that in mind when attaching RC corners and derating timing. Review the file to understand any problems found. make sure an alwayson buffer is available and usable. Run runCLP to verify the CPF and make sure the results are well understood before proceeding. For low power designs utilizing power shutdown. PAGE 12 . INC. ALL RIGHTS RESERVED. Optimization of leakage and/or dynamic power is typically on top of the presented flows: • For designs where leakage is a high priority. Data Preparation and Validation for Low Power Designs If your design is utilizing a low power flow using a Common Power Format (CPF) file you should also check the following: • • • • Make sure the CPF points to the proper libraries and constraints. Determining and Setting the RC Scaling Factors RC Scaling factors are recommended to correlate EDI System's native parasitic extractor with your signoff extractor. This command calculates the capacitance factors by comparing EDI System extraction with the results of either QRC Extraction or a SPEF file. This will run a number of checks and output the results to a text file. This is done by setting: setOptMode -leakagePowerEffort high COPYRIGHT © 2011. Once the scaling factors are determined specify them in your MMMC setup using the create_rc_corner or update_rc_corner commands. This provides more accurate timing and predictability throughout the flow.

You can use this command to change the process technology dependant default settings globally for each application instead of setting several mode options. only does postRoute reclaim. Flow Preparation Setting the design mode and understanding how extraction and timing analysis are utilized during the flow are important to achieving timing closure.  This method typically works best with a VCD or TCF to properly apply the activity rates. PAGE 13 . Low effort only performs postRoute downsizing. the EDI System software assigns coupling capacitance threshold values to the RC extraction filters automatically. enabled via "setOptMode -leakagePower low". the grounding of coupling capacitances also depends on the capacitance filtering mode set by the -capFilterMode parameter of the setExtractRCMode command.  This flow has the least impact to run time but typically results in a 5-10% loss of potential leakage savings.EDI Timing Closure Guide o o High effort leakage does come with a run time and area penalty and is particularly time consuming as the ratio of higher VT cells drops. Setting the Design Mode setDesignMode specifies the process technology value and flow effort level. ALL RIGHTS RESERVED. dynamic power optimization can be enabled with the following and also set at the beginning of the flow: setOptMode -dyanmicPowerEffort [ low | high ] o High effort does reclaim throughout the flow. These values determine whether the coupling capacitances of the nets in a design will be lumped to the ground. INC. COPYRIGHT © 2011. • "setDesignMode -process" specifies the process technology you are designing at. Note: In detailed extraction mode. When you specify a process technology value using the setDesignMode command. • For designs where dynamic power is a high priority. CADENCE DESIGN SYSTEMS. Low leakage effort.

CADENCE DESIGN SYSTEMS. the target is to achieve good QoR with minimum runtime. The -engine option indicates whether to use the preRoute or postRoute extraction engine. In this mode. high : Forces every super-command to use their high-effort settings and the additional non-default options. COPYRIGHT © 2011. Fast extraction is used early in the flow to provide fast turnaround times so you can experiment with different floorplans and solutions. As you progress through the flow.EDI Timing Closure Guide • "setDesignMode -flowEffort" can be used to force every supercommand to use their high-effort settings and the additional nondefault options. The lower the effort level. the effort level is increased which improves the accuracy of the extraction at the expense of run time. The following example sets the process to 45nm and effort level to high: setDesignMode -process 45nm -effortLevel high • Extraction Resistance and Capacitance (RC) extraction using the extractRC command is run frequently in the flow each time timing analysis is performed. In this mode. the faster extraction runs at the expense of being less accurate. The effortLevel parameter further specifies which postroute engine is used for balancing performance versus accuracy needs. INC. • • Use "-engine preRoute" when the design has not been detail routed by NanoRoute yet. In this mode. coupling is not reported. ALL RIGHTS RESERVED. PAGE 14 . The setExtractRCMode options -engine and -effortLevel control which extractor is used by extractRC. the target is to achieve best possible timing/yield at the expense of some more CPU runtime. coupling is reported. the target is to achieve best possible timing/yield at the expense of some more CPU runtime. Use "-engine postRoute" after the design has been detail routed by NanoRoute. RC extraction is done by the detailed measurement of the distance to the surrounding wires. When "-engine preRoute" is set RC extraction is done by the fast density measurements of the surrounding wires. none : Leaves every super-command to use their default settings.

medium . Download instructions are available at http://support. TQRC (-effortLevel medium) is the default extraction engine in the postroute flow for 65nm and below design. The default for nodes above 65nm is low. IQRC supports distributed processing. providing maximum flexibility. The default value for -effortLevel depends on the value of setDesignMode.Invokes the native detailed extraction engine. This engine supports distributed processing. If timing violations exist.Invokes the Integrated QRC (IQRC) extraction engine. Note: IQRC requires a QRC license. Initial timing analysis should not be performed after placement.cadence. CADENCE DESIGN SYSTEMS.EDI Timing Closure Guide The -effortLevel value controls which extractor is used when the postRoute engine is used. TQRC performance and accuracy falls between native detailed extraction and IQRC engine.solutionNumber=11681606. thereby.1. we recommend using the Global Timing Debug (GTD) GUI to analyze and debug the results: • GTD is an invaluable tool which provides forms and graphs to help you visually see timing problems. Timing Analysis Timing analysis is typically run after each step in the timing closure flow using the timeDesign command. signoff . o TQRC engine is recommended for process nodes < 65nm. Native Detailed (effortLevel low) engine remains the default engine if no QRC Tech file has been defined or if the defineRCCorner command has been used. high . INC. This engine choice provides the highest accuracy. o IQRC provides superior accuracy compared to TQRC. Therefore. In addition.Invokes the Standalone QRC extraction engine. Note: This setting does not require a QRC license. • • • • low . The engine has several run modes.Invokes the Turbo QRC (TQRC) extraction mode.com/wps/mypoc/cos?uri=deeplinkmin:Vi ewSolution. ALL RIGHTS RESERVED. o To learn more about GTD we recommend completing the Workshop provided with EDI 10. PAGE 15 . However. TQRC and IQRC do not support the obsoleted 3 corner flow (defineRCCorner flow) and require a QRC Tech file. IQRC is recommended for extraction after ECO. Instead. This is the same as specifying the "-engine postRoute" setting. we recommend always waiting until after pre-CTS optimization to report your initial timing: COPYRIGHT © 2011.

Until the cells are in that region. Additionally. it can be advantageous to run pre-placement optimization or simple buffer and double-inverter removal (area reclamation) prior to initial placement. ALL RIGHTS RESERVED. we recommend starting with the default flow (or Foundation Flow) then apply additional options based on your design requirements. the input netlist (typically from a poor RTL synthesis) is not a good candidate for placement since it might contain buffer trees or logic that is poorly structured for timing closure. In most cases. but it is often the case. It is more reliable to allow buffer insertion algorithms to build and place buffer trees rather than to rely on the placer to put previously inserted trees in optimal locations. It is not uncommon to have the original "worse" placement come out better post-optimization than the "better" placement. It is important to note that using options from a previous design might not necessarily apply to your current design. The goals of pre-placement optimization are to optimize the netlist to: • • • • Improve the logic structure Reduce congestion Reduce area Improve timing In some situations. • A placement should always be followed by an optimization run to bring the cells into line prior to making a timing and routability judgment. INC. having buffer trees in the initial netlist can adversely affect the initial placement. Note deleteBufferTree is run by placeDesign by default. any timing analysis results are highly suspect. Additionally. This can be accomplished by using the deleteBufferTree and removeClockTree commands. CADENCE DESIGN SYSTEMS. Therefore. Pre-Placement Optimization Data preparation is complete and you are now ready to implement your design. COPYRIGHT © 2011.EDI Timing Closure Guide • After placement. PAGE 16 . high-fanout nets should be buffered after placement. as you proceed through the flow you should investigate each flow step and validate it before moving to the next one. This seems nonintuitive. there will be some basic buffering and resizing to get cells into their characterized region of timing as defined by their lookup tables. Because of these effects.

 Automatic Floorplan Synthesis is a set of nativelyintegrated automatic floorplan capabilities that can create a quick.  Prototype placement does not produce legal placement so make sure you run placement with "setPlaceMode -fp false" as you converge on a floorplan. Prototyping allows you to create a floorplan that can be implemented with high confidence before you spend time and effort on optimization and routing. restructuring or remapping the elements on the paths (or related portions of the design) can provide better timing results. CADENCE DESIGN SYSTEMS. It is best to get a baseline placement without constraining the placer. Given a gate-level netlist and o o COPYRIGHT © 2011. Floorplanning and Initial Placement The goals of floorplanning and initial placement include: • • • Creating prototypes using multiple iterations with a focus on routability Moving toward timing-driven placement as routability stabilizes Adding power routing once timing and congestion converge The initial floorplan and placement have a primary impact on the performance of a design. Early on use "setPlaceMode -fp true" to run placement in prototyping mode for faster turnaround. power. Use Automatic Floorplan Synthesis if your design contains a large number of hard macros. Prototyping involves multiple placement iterations that converge on a solution which meets a design's requirements for routability. The following steps outline a basic procedure for obtaining an initial placement.EDI Timing Closure Guide For designs where the logical structure of the critical paths or high congestion are the sources of closure problems. Run the initial placement without any regions and guides. Additional restructuring can be performed later in the flow using the EDI System optimization commands with more physical information. timing (including clocks). The initial floorplan drives the constraints leveraged by placement and partitioning to meet these objectives. 1. This is done by running netlist-to-netlist optimization using the runN2NOpt command on the initial netlist prior to place and route. EDI System allows you to use prototypes to analyze various placements and floorplans before you begin the optimization process. INC. and signal integrity. prototype floorplan. PAGE 17 . ALL RIGHTS RESERVED.

Use the following guidelines during floorplanning and placement to avoid congestion. Preplace I/Os and macros. and make necessary adjustments. See Automatic Floorplan Synthesis in the EDI System User Guide for more information. ALL RIGHTS RESERVED. placement blockages. Assess different floorplan styles such as hard macro placement in periphery. Keep the macro depth at 1 to 2 for best CTS. Designs which are congested are more likely to have timing jumps during timing and Signal Integrity (SI) closure. The placement engine automatically detects lowutilized designs and turns on the options required to achieve an optimal placement. 2. CADENCE DESIGN SYSTEMS. 1. obstructions. and Design-for-test (DFT) results. Ensuring Routability Initial prototype iterations should focus on routability as the key to achieving predictable timing closure. optimization. Automatic Floorplan Synthesis can analyze the signal flow and generate a floorplan that includes automatic module and macro placement for large chips. review a data flow diagram or a high-level design description from the chip designer to determine an appropriate floorplan style. Choose an appropriate floorplan style. block halos. INC. COPYRIGHT © 2011. • • If possible. and partial placement blockages (density screens) are used to control the efficient routing of the design. block placement. Consider using Automatic Floorplan Synthesis and relative floorplanning constraints to simplify floorplan iterations. Analyze the placement for timing and routability issues.EDI Timing Closure Guide design physical boundary. PAGE 18 . consider different aspect ratios to accommodate a shallower macro depth. Tools such as module guides. 3. or doughnut (periphery and island). and other techniques to refine the floorplan. island. 2. Employ module guides. You should attempt to resolve congestion before attempting timing closure. If possible.

These modules can typically have higher densities due to the inclusion of the memories. INC. PCI. Placement generally does not do a good job of placing cells between macros. high fanout. 6. Use module guides carefully.EDI Timing Closure Guide • • Review hard macro connectivity and placement based on the minimum distance from a hard macro to its target connectivity. CADENCE DESIGN SYSTEMS. ALL RIGHTS RESERVED. or Power management logic. Use block halos. Datapath logic can be a source of congestion problems due to poor aspect ratios. PAGE 19 . or fences only when greater control is required. Module guides should be used for floorplan refinement or hierarchical partitioning. DRV. and large amounts of shifting. Preplace high-speed and analog cores based on their special requirements for noise isolation and power domains. or SI fixing to add buffers. Review the placement of module guides related to memories. Place other cells such as endcaps. Be careful not to place too many module constraints early in the floorplanning process because it is time consuming and greatly constrains the placement. regions. 4. Reduce or remove halos and obstructions after placement to make sufficient space available around macros for optimization. Consider tuning the locations of these module guides and lowering the density to reduce congestion. • • • Allow space between I/Os and peripheral macros for critical logic such as JTAG. CTS. • • • Place module guides. welltaps and decaps prior to placement as required. Review the placement of module guides related to datapath and control logic relative to the associated hard macros. Reorder scan chains COPYRIGHT © 2011. 5. Use the specifyJtag and placeJtag commands prior to placing blocks. 3. Push down into module guides to further assess the quality of the floorplan and resulting placement. placement obstructions or fences around blocks prior to optimization or Clock Tree Synthesis (CTS). • Verify that logic blocks and hard macros which communicate with I/O buffers are properly placed and have optimal orientation for routability. Review I/O placement to identify I/O anchors and associated logic. Allow enough space between preplaced blocks.

no reordering is performed. ALL RIGHTS RESERVED. placeDesign performs scan tracing and scan reordering based on global or user-specified scan reorder settings and specified or imported scan chain information. o PINS marked with + SPECIAL cannot be optimized. Optimization treats nets in the SPECIALNETS as dont_touch. Failing to reorder the scan chain can cause a routable floorplan to appear unroutable. Timing-Driven Placement As the routability of the floorplan stabilizes. o Followpin routing should align to rows/cells with correct orientation (VDD pin to VDD followpin). Gaps between standard cells and blocks should be covered with soft or hard blockages. CADENCE DESIGN SYSTEMS. With a good floorplan you should be able to: • • Place the design in the floorplan without issues Create a routeable placement Make sure to consider the following when finalizing the floorplan: • • • • The power grid should be defined: o Global net connections properly defined using globalNetConnect command. PAGE 20 pre- . Tracks should match IO pins and placement grid (rows). Placement cannot place cells in the area of soft blockages but optimization and CTS can. INC. Use generateTracks to update the tracks. o Nets requiring optimization should be defined as signal (regular) nets. Timing-driven placement (setPlaceMode -timingDriven true) and placement optimization (buffer tree deletion) are enabled by default: placeDesign COPYRIGHT © 2011. All blocks should be marked fixed (setBlockPlacementStatus allHardMacros -status fixed). By default. If scan chain information is missing. make sure that scan chains are reordered to eliminate "false" hot spots in the design.EDI Timing Closure Guide • When evaluating congestion. you should shift your focus to timing-driven placement. Validating the Floorplan A congested or unroutable design at this stage will not get better during optimization.

keeping the existing buffer tree generates better timing results. ALL RIGHTS RESERVED.EDI Timing Closure Guide Following are additional tips for performing placement on high performance. For example. However. removing the existing buffer tree before placement produces better timing result and wire length for the majority of designs. PAGE 21 . Usually. You must read in the clock tree specification file prior to placeDesign for this option to work. high congestion and high utilization designs. these nets may benefit from higher net weights. "setOptMode allEndPoints true" enables optimization of all paths and replaces "setOptMode -criticalRange 1. Pre-CTS optimization has been improved in EDI 10. Overall. optDesign optimizes only the most critical paths. Tips for Placing High Performance Designs • By default. placeDesign –noPreplaceOpt The following option is useful when clock gating checks are in the critical paths and to help limit jumps seen by CTS moving gating elements. INC. the -inPlaceOpt option is ignored if "setOptMode -allEndPoints true" or "setDesignMode flowEffort high" is enabled. Use "specifyClockTree -file specFile".0" from previous releases. running "placeDesign + optDesign -preCTS" with "setOptMode -allEndPoints true" enabled reduces the run time of placement and pre-CTS optimization while achieving similar results as "placeDesign inPlaceOpt + optDesign -preCTS". setPlaceMode -clkGateAware true • Net weights can be used in specific situations to instruct the placer to minimize the distance between the driver and sinks. if there are half cycle paths to or from memories or latches. Or if you COPYRIGHT © 2011. Net weights should be used on a limited basis when the designer determines the placer needs to put more effort placing specified logic closer together.1 and therefore -inPlaceOpt is no longer needed. setOptMode -allEndPoints true Note in EDI 10. • The following will disable buffer tree deletion prior to placement. in some designs.1 we no longer recommend running "placeDesign inPlaceOpt". CADENCE DESIGN SYSTEMS. For high performance designs it can help to optimize all paths. Furthermore.

INC. It also automatically enables the congRepair command. Use specifyNetWeight to assign a greater weight to a net (default is 2). running in high effort mode helps (High utilization is typically associated with utilizations > 80%.EDI Timing Closure Guide need greater control over how the fanout of clock gating cells are placed. 70% might already start to be difficult to handle): setDesignMode -flowEffort high true The following option increases the numerical iterations and makes the instance bloating more aggressive. For example: specifyNetWeight netName 10 Tips for Placing Congested or High Utilization Designs When optimization contributes to the congestion or the design has high utilization. In high-effort mode. but depending on the technology. The reason timeDesign is called is to make sure CTE does the clock net marking to identify all the clocks: specifyClockTree -file <cts. it might add up to ten percent to the run time. Optimization can reduce the total wire length up to two percent without degrading placement. ALL RIGHTS RESERVED. setting the clock attributes before placement and allowing the placer and trialRoute to see the effect can help.spec> changeClockStatus -all -useClock timeDesign -prePlace -outDir RPT -prefix preplace dbForEachCellNet [dbgTopCell] net { if {[dbIsNetDefInClock $net]==1||[dbIsNetClock $net]==1} { setAttribute -net $net -non_default_rule <rule> \ -avoid_detour true -bottom_preferred_routing_layer 4 \ -top_preferred_routing_layer 6 \ -preferred_extra_space 1 } } COPYRIGHT © 2011. setPlaceMode -wireLenOptEffort high • If clock routing is a source of congestion due to NDRs or other rules. PAGE 22 . setPlaceMode -congEffort high The following optimizes wire length by swapping cells. CADENCE DESIGN SYSTEMS. Here is some example code that can be called before placement.

the default transition is 120ps. all nets with a fanout greater than 100 will be buffered with the exception of clock nets. COPYRIGHT © 2011. o For nets with a fanout higher than 1000. The command uses trialRoute + incremental placement. See "Data Preparation" for more information.5pf. o The defaults can be changed with the commands: setDefaultNetDelay.Worst Negative Slack) Design rule violations (DRVs) Setup times (TNS . and refer to the Optimizing Timing chapter in the EDI System User Guide for more procedures on optimizing the design. o During optimization. PAGE 23 . and setInputTransitionDelay. Guidelines for Pre-CTS Optimization Consider the following points during pre-CTS optimization: • • • Handle assign statements correctly. ALL RIGHTS RESERVED.Total Negative Slack) Use the "optDesign -preCTS" command only if optimization has not been done already. For more information on the optDesign command. see optDesign in the EDI System Text Command Reference. INC. So congRepair should be used with caution. During subsequent optimization runs. use the -incr option. the default delay is 1ns. Make sure all required views are active using set_analysis_view.EDI Timing Closure Guide • There is a standalone command called congRepair which can be called in any part of the pre-route flow to attempt to relieve congestion. setDefaultNetLoad. The use of the optDesign command for post-CTS optimization and post-route optimization is described in the corresponding sections of this document. This can have a significantly detrimental effect on timing and often will require additional optDesign calls (and may not converge). CADENCE DESIGN SYSTEMS. and the default capacitance is 0. Pre-CTS Optimization The goal of pre-CTS optimization is to repair • • • Setup slack (WNS . Set input transitions for the high fanout nets for delay calculation to use on high fanout networks.

PAGE 24 . Note "setDesignMode -flowEffort high" automatically sets "setOptMode -allEndPoints true". • To optimize timing placed designs for the first time (with ideal clocks). you may choose to optimize specific timing paths using path groups. If there is very large TNS or high number of violating paths this could significantly increase runtime and area. To further optimize a design after you have already run optDesign preCTS. See the section "Path Group Optimization" later in this document for details. Additionally. setOptMode -allEndPoints true COPYRIGHT © 2011. use the following command: optDesign -preCTS -incr • • The following are additional tips for performing preCTS optimization on high performance.EDI Timing Closure Guide Pre-CTS optDesign Command Sequences You can use optDesign for pre-CTS optimization in the following ways. ALL RIGHTS RESERVED. INC. but does not perform netlist restructuring. You can use any of these features separately or in combination. This should only be set if the WNS/TNS are manageable. use the following commands: setOptMode -effort low optDesign -preCTS In this mode optDesign performs gate resizing and global buffer insertion. use the following command: optDesign -preCTS To perform rapid timing optimization for design prototyping. congested and high utilization designs. CADENCE DESIGN SYSTEMS. Tips for Optimizing High Performance Designs • Enable optimization for all end points by setting the following.

Clock gate cloning duplicates clock gating cells and redistribute their gated loads. Use setUsefulSkewMode to control the buffer types and other options used by useful skew optimization.EDI Timing Closure Guide • Useful skew is often required on the toughest designs. Often clock gating checks don't become visibly critical until the tree is synthesized due to the larger clock skew between them and the enabling register. In postCTS. or over-constraining the clock gating paths. ALL RIGHTS RESERVED. In preCTS. CADENCE DESIGN SYSTEMS. useful skew optimization advances and delays sequential elements. To enable useful skew optimization run: setOptMode -usefulSkew true • The following option temporarily over constrains clock gating checks during preCTS optimization so the tool is able to work harder before the actual tree is inserted. Clock Gate Cloning & Decloning Clock gate decloning merges clock gating cells with the same inputs. setOptMode -clkGateAware true If clock gating cells are still on the critical path after performing placement and optimization using -clkGateAware true consider using clock gate decloning and/or cloning. INC. An example flow using clock gate decloning and cloning is: # Specify the clock tree constraints and run clock gate aware placement: specifyClockTree -file ctsConstraintsFile setPlaceMode -clkGateAware true placeDesign # Declone the clock gates (optional step) ckDecloneGate -ignoreDontTouch -ignorePreplaced # Clone the clock gates based on placement (optional step) COPYRIGHT © 2011. PAGE 25 . and often has little to no penalty in terms of the size of the tree. useful skew optimization delays sequential elements and physically adds additional delay through the use of buffers. This option requires the clock tree specification file to be specified prior to optDesign (specifyClockTree -file specFile).

15 # Turn on pathgroup flow setAnalysisMode -honorClockDomains false # Create separate reg2reg and clkgate groups group_path -name reg2reg -from [all_registers] -to [filter_collection [all_registers] "is_integrated_clock_gating_cell != true"] group_path -name clkgate -from [all_registers] -to [filter_collection [all_registers] "is_integrated_clock_gating_cell == true"] setPathGroupOptions reg2reg -effortLevel high -criticalRange 1 setPathGroupOptions clkgate -effortLevel high -targetSlack $clkgate_target_slack -criticalRange 1 Tips for Optimizing Congested and High Utilization Designs • The risk for timing optimization on designs with high routing congestion mainly comes from nets detouring that are unpredictable. CADENCE DESIGN SYSTEMS. ALL RIGHTS RESERVED. it is usually beneficial to identify the weak cells and to set them as dont_use. This considers the setup timing # to the clock gating cells. Use care when over constraining designs as it increases run time: # Set target overshoot slack for clock gating elements preCTS (in nanoseconds): set clkgate_target_slack 0. COPYRIGHT © 2011. INC. PAGE 26 .EDI Timing Closure Guide ckCloneGate # Perform preCTS optimization setOptMode -clkGateAware true optDesign -preCTS # Clone the clock gates in time driven mode. Following is a sample script to do this. In addition to floorplan and placement guidances made previously. ckCloneGate -timingDriven timeDesign -preCTS # Run preCTS optimization again (optional) optDesign -preCTS Over-constraining Clock Gating Paths You can create separate path groups for the clock gating cells and over constrain them. Set the clkgate_target_slack to your desired value.

it could be that some redundant or useless logic could be safely removed to reduce area. The following reduces local congestion during timing optimization: setOptMode -congOpt true • The following option will run additional iterations for resolving routing congestion in trialRoute: setTrialRouteMode -highEffort true Allowing M1 routing can help to reduce congestion and thus removes some pessimism during RC extraction: setTrialRouteMode -useM1 true • Monitor the density increase. INC. Properly setting the setup target slack will reduce area and improve runtime. If needed. This is because setDontUse applies to all operating modes while set_dont_use only affects the operating mode(s) it is applied to. The flow to create and optimize path groups is as follows. PAGE 27 .5ns.EDI Timing Closure Guide setDontUse cellName(s) Note it's recommended to use setDontUse rather than the SDC set_dont_use. if the target is -0. it might be helpful to set "setOptMode setupTargetSlack -0. Use setPathGroupOptions to control how optimization works on each path group: COPYRIGHT © 2011. CADENCE DESIGN SYSTEMS. reduce/remove extra margins on setup target and DRV. Usually the density starts blowing up when trying to fix the last tens of picoseconds and the better timing seen pre-CTS will lead to flow divergence later on. ALL RIGHTS RESERVED. setOptMode -simplifyNetlist true Path Group Optimization You can focus timing optimization on specific paths using path groups. The same applies to DRV fixing by using drcMargin option: setOptMode -setupTargetSlack <slack> -drcMargin <value> • Depending on the quality of the initial netlist.2". For example.

15 criticalRange 1 optDesign -preCTS [-incr] Checking & Debugging Timing You can use the command timeDesign -preCTS to check the current timing: timeDesign -preCTS -outDir preCTSOptTiming If timing violations exist using Global Timing Debug to analyze the violations. Following are suggestions for resolving common types of timing problems seen during pre-CTS optimization: • Some nets are not being optimized. Use COPYRIGHT © 2011. Run "reportIgnoredNets -outfile filename" to output a report of ignored nets during optimization. CADENCE DESIGN SYSTEMS.EDI Timing Closure Guide clearClockDomains setAnalysisMode -honorClockDomains false group_path [-name path_group_name] [-from from_list] [-to to_list] [through through_list] setPathGroupOptions . INC.. ALL RIGHTS RESERVED. PAGE 28 . The goal here is to over constrain the clock gating paths so optDesign works harder on them: setAnalysisMode -honorClockDomains false group_path -name reg2reg -from [all_registers] -to [filter_collection [all_registers] "is_integrated_clock_gating_cell != true"] group_path -name clkgate -from [all_registers] -to [filter_collection [all_registers] "is_integrated_clock_gating_cell == true"] setPathGroupOptions reg2reg -effortLevel high -criticalRange 1 setPathGroupOptions clkgate -effortLevel high -targetSlack 0.. you could create a path group to all the D inputs of SRAM instances using wildcards: clearClockDomains setAnalysisMode -honorClockDomains false group_path -name to_srams -to top/inst_sram*/D* setPathGroupOptions to_srams -slackAdjustment 1000 slackAdjustmentPriority 10 optDesign -preCTS [-incr] Here is another example where separate path groups are created for reg2reg and clock gating paths. optDesign -preCTS [-incr] For example.

EDI Timing Closure Guide the abbreviation in the last column with the key at the bottom of the file to determine why certain nets are not being optimized. PAGE 29 . Make sure cells intended for optimization are available to use. ALL RIGHTS RESERVED. CADENCE DESIGN SYSTEMS. Conformal Constraint Designer includes the following: Formal validation of SDC exceptions. If you see in the log file the worst negative slack (WNS) increases unexpectedly. which leverages both RTL and gate-level information Ability to identify false paths from critical paths Ability to validate the consistency between top-level and lowerlevel constraints • • • o o o o o • Evaluate Throughout the flow it is important to achieve desirable timing results at each step before proceeding. When running optDesign. Conformal Constraint Designer offers a complete. timing jumps may occur when it runs refinePlace or trialRoute. The goal as you proceed through each step is to achieve similar timing results as the previous step. functional constraint validation solution that enables rapid timing closure when working with implementation tools. or when going from one step to the next. Similar paths are not meeting timing. Evaluate the timing constraints and identify false paths that may be affecting the critical path. it's likely caused by one of three things: COPYRIGHT © 2011. Timing jumps are unexpected increases in negative slack which occur during or command. INC. • Monitor "reportFootprint -reportDontTouchNUse -outfile fileName" to identify cells with a set_dont_touch or set_dont_use attribute set. See "Path Group Optimization" earlier in this section. such as false paths (FPs). Critical path(s) go through congested area. Create a custom path group for these paths and optimize them separately. SDC Quality checks Extensive debug and analysis. Try using cell padding (specifyCellPad or specifyInstPad commands) or partial placement blockages (also known as density screens) to reduce the congestion. The file will identify these cells in the far right column.

mixed_steiner_tr saveDesign prects.EDI Timing Closure Guide 1. compare the worst path before and after refinePlace and observe how the cells are moved. You can debug this by running the following which will separate out the refinePlace and trialRoute steps from optDesign: setOptMode -allEndPoints false -rPlace false optDesign -preCTS -incr -outDir RPT -prefix prects. Discrepancies between optDesign's internal steiner router and trialRoute (the steiner router is used after a net has been modified by optimization). ALL RIGHTS RESERVED. is the net going over a hard macro? Lastly. This will be a mix of steiner and trialRoute nets so you can observe the optimized timing. Differences in layer selection between the steiner router and trialRoute. Large cell movements during refinePlace 2.enc timeDesign -preCTS -outDir RPT -prefix prects.mixed_steiner_tr. If the timing degrades a lot at this point. It includes the following jobs. If it has increased significantly. For example. Compare the timing after legalization. or between different calls to trialRoute. refinePlace is called to legalize the placement and re-trialRoute the design with timeDesign. the timing jump is due to discrepancies between steiner route and trialRoute. Next. trialRoute is run by timeDesign.tr_legal The initial optDesign will finish the design without calling refinePlace or trialRoute.tr_nonlegal refineplace timeDesign -preCTS -outDir RPT -prefix prects. INC. Is the moved in a congested area or is a cell having to be moved a large distance to avoid a blockage? Clock Tree Synthesis The goal of clock tree synthesis is to build a buffer distribution network to meet the timing requirements among the leaf pins. • • • Creating clock tree spec file Building a buffer distribution network Routing clock nets using NanoRoute COPYRIGHT © 2011. PAGE 30 . 3. You can compare the path after trialRoute to the same exact path in the mixed case to determine the net(s) causing the problem and attempt to identify what's happening. CADENCE DESIGN SYSTEMS.

ExcludedPin. PAGE 31 . the software uses the value COPYRIGHT © 2011. ClkGroup.Will add necessary ThroughPin statement to the CTS constraints file You can control the buffer types to build clock trees by listing the buffer types in the config file or use "createClockTreeSpec -bufferList bufferList".Becomes SrcLatency value in ns set_clock_uncertainty . skew. ALL RIGHTS RESERVED. LeafPin. Route types for nets connected to leaf cells and nets connected to non-leaf cells can be specified separately with LeafRouteType and Routetype. INC.Becomes SinkLeafTran and BufMaxTran (Default: 400 ps) set_clock_latency value . Note: Set the preferredExtraSpace to 0 in the LeafRouteType definition in the spec file. PreservePin. NoGating. you can use setCTSMode before running specifyClockTree to change the default routing type and global clock tree synthesis controls. If you do not set it to zero. Also.Becomes MaxDelay (Default: clock period) MinDelay (Default: 0) set_clock_latency -source value .EDI Timing Closure Guide Creating the Clock Specification File Clock tree synthesis (CTS) is a series of procedures to build a buffer distribution network to meet the design's timing targets. • • • • • • create_clock . The clock tree specification file is used to direct clock tree synthesis and includes: • • • • Design constraints including latency. and design rules Buffer and routing type definitions Trace and synthesis controls like: MacroModel.Becomes AutoCTSRootPin in CTS constraints file set_clock_transition . CADENCE DESIGN SYSTEMS. ThroughPin.Becomes MaxSkew (Default: 300 ps) create_generated_clock . You can also control the routing types for the clock nets. and GatingGroupInstances Flow controls like: o Whether or not to generate a detail report o Whether or not to route the clock net o Whether or not to perform post-CTS optimization You can generate the default clock tree spec file with the command: createClockTreeSpec -file filename Automatically generating a clock tree specification translates the following information from the timing constraint file into suitable records for the clock tree spec file.

Trace Pre-CTS Clock Tree) user interface can be used to traverse the clock tree structure logically and physically based on the applied clock specification file before committing clock tree synthesis. A good clock tree plan including suitable constraints and placement space can improve the results of clock tree synthesis and avoid problems for post-CTS timing closure. CADENCE DESIGN SYSTEMS. The table below compares the clockDesign settings to the default settings: Option clockDesign Setting Default Setting RouteClkNet Yes No PostOpt Yes Yes OptAddBuffer Yes No The clockDesign command generates the default clock tree specification file (if not specified). etc. This can cause congestion. deleteClockTree. calls NanoRoute to route the clock nets. The clock tree specification file is very important and directly affects the result of clock tree synthesis.) It's important to note clockDesign automatically sets some CTS options which are disabled by default. and then optimizes the clock tree to COPYRIGHT © 2011. use the clockDesign command. builds the clock tree. ckSynthesis. The Pre-CTS Clock Tree Tracer (Clock . ensure the settings are consistent. You can use it as a basis for changing the clock tree specification file to consolidate the clock tree structure and improve the results of clock tree synthesis. ALL RIGHTS RESERVED. So if you are comparing a clockDesign run to a run where each command is run separately.e. INC. Synthesizing the Clock Tree To generate the clock tree. createClockTreeSpec. PAGE 32 .EDI Timing Closure Guide specified in RouteType definition. This command performs the following operations during clock tree synthesis: • • • • Deletes any existing buffers on the clock nets Builds a buffer distribution network to distribute the clock signal(s) to the registers Routes the clock nets using NanoRoute Optimizes the clock tree clockDesign is a super-command which runs the commands in the CTS flow (i. which might be greater than zero. deletes existing clock trees. specifyClockTree.

but sometimes can come at the expense of common paths which get filtered via CPPR. INC. ALL RIGHTS RESERVED. Reducing latency often lessens the impact of derating. PAGE 33 . and honors the scheduling file while building the clock tree. or checks for "rda_Input ui_scheduling_file". It can increase runtime considerably and ignores MinDelay constructs: setCTSMode -synthLatencyEffort high • The following performs optimization after the tree construction mostly by optimizing the location of the tree elements and can also add significant runtime: setCTSMode -optLatency true • The following reduces the size of the tree by performing optimization after the tree construction to delete and downsize elements to recover area: setCTSMode -optArea true Routing layer selection • It is advised to have CTS route the clock nets and fix the wires. direct NanoRoute to follow the route guide by using the command "setCTSMode routeGuide true". slew and latency are the primary methods to get the highest performance design but there is a balance between tightening these constraints and getting the best clock tree (tighter values often increase the area/power of the tree). If you performed useful skew optimization (setOptMode -usefulSkew true). CADENCE DESIGN SYSTEMS. This is enabled by default. Tips for Performing CTS on High Performance Designs Skew. clockDesign automatically checks for any scheduling file in the working directory. This operation can improve the correlation between pre-route and post-route clock nets.EDI Timing Closure Guide improve the skew including resizing buffers or inverters. refining placement. Mode settings to reduce latency: • The following affects actual tree construction. If the clockDesign command calls NanoRoute to route the clock nets. adding buffers. COPYRIGHT © 2011. and correcting routing.

the primary coupling occurs between the cross over/under wires.e. o It is very common for the default library definition to have them marked dont_use and/or dont_touch. Using a preferred extra spacing of 1 helps to reduce capacitance and future SI impact. That is because once the wires are >1 track away from the clock. maxDelay and maxSkew value because it will help to balance the different clocks from each other. Make sure all clock gating cells are not marked dont_use or dont_touch otherwise they will not be resized.030pF + CLKINVX16 0. CADENCE DESIGN SYSTEMS. INC. Additionally. use those as the tree will be smaller and more SI immune. Setting constraints • Using MaxCap constraints on elements in the tree can help reduce the potential for large jumps through these cells. For example: MaxCap + SGCLATNX4 0. you can run tests to see if trees built with all buffers or all inverters are faster. ALL RIGHTS RESERVED. Buffer/Inverter selection • Limiting the list of available cells to 3 or 4 often improves both runtime and quality of results. If the tree can be built with LVT cells. • • Manual skewing COPYRIGHT © 2011. o Using values larger than 1 often do not improve the situation and often have no effect on SI pushouts. PAGE 34 . horizontal and vertical) with the same pitch/width/spacing so CTS estimation is more accurate. o Try to pair and limit the layers (i. The low drive clock cells typically shouldn't be used as they are susceptible to routing changes. Routing with wider widths (2 to 3 times the default width) is an effective way to reduce resistance which is a big factor for designs at 40nm and below.20pF Apply a realistic minDelay.EDI Timing Closure Guide • • • Using the upper thicker layers often improves performance due to the lower lateral capacitance.

5ns 0.5 A/B/RAM1/CLKA • To model this in the CTS spec file it would appear as follows. when too many cells are inserted. consider only using the rules for the non-sink levels (or using a less restrictive rule for the sinks) • In the CTS spec file: o RouteType controls the routing rules for non-sink levels o LeafRouteType controls the routing rules for the sink level COPYRIGHT © 2011. restricting the top layer so it cannot go over RAMS NDRs or other routing rules For CTS in high utilization designs. This can arise when preCTS useful skew is not enabled or preCTS cannot predict the magnitude of the problem due to skew/derating.5ns 0. typically the goal is to make the tree as small as possible. ALL RIGHTS RESERVED. In preCTS you can model this using the set_clock_latency SDC construct. PAGE 35 . The following setting is used to reduce the size of the tree. CADENCE DESIGN SYSTEMS. CTS performs optimization after the tree construction to delete and downsize elements to recover area.5ns 0.EDI Timing Closure Guide • Sometimes certain elements must be manually skewed. The following example show the clock delay to A/B/RAM1/CLKA is pulled in 500ps: set_clock_latency -0.5ns 0pF Tips for Performing CTS on Congested and High Utilization Designs CTS congestion normally results from either: • • • Too many cells inserted due to overly tight constraints Poor choice of top/bottom preferred routing layers o For example.5ns means that 500ps of latency is "inside" the CLKA pin of A/B/RAM1: MacroModel pin A/B/RAM1/CLKA 0. The +0. INC. try relaxing the constraints (typically the Buf/Sink MaxTran): setCTSMode -optArea true When routing rules are causing the problems. Also.

See How to Generate Scaling Factors for RC Correlation. in the Encounter Menu Reference for descriptions of the forms and fields of the user interface. Synthesizing Clock Trees. CADENCE DESIGN SYSTEMS. Refer to the chapter. ckECO can be used to improve the tree based on the parasitics and timing seen by the optimizer. in the EDI System User Guide for more information. Clock Menu.EDI Timing Closure Guide • MaxTran constraints typically have the largest effect on size of tree so relaxing these helps reduce impact. Buffer/Inverter selection • If the tree can be built with LVT cells. Optimizing the Clock Tree After clockDesign. see the chapter.Debug Clock Tree) to debug the timing result. Sometimes a degradation in clock delay or skew occurs during CTS when comparing the results before and after the clocks are routed. • ckECO by default can use all the allowed buffers/inverters. ALL RIGHTS RESERVED.Browse Clock Tree) user interface to fine tune the clock tree to improve the results. Use displayClockMinMaxPaths with the -preRoute and -clkRouteOnly options to compare pre-route and clock route paths. PAGE 36 . use those as the tree will be smaller and more SI immune. Constraining the routing to two layers reduces differences in layer assignment between CTS and NanoRoute. COPYRIGHT © 2011. Constrain the routing to two upper routing layers using a RouteType in the CTS specification file. To limit it to only those in the CTS spec file use the -useSpecFileCellsOnly option. INC. From the user interface you can perform the following operations: • • • • Add buffers Delete buffers Size cells Change net connections Use Global Clock Tree Debug (Clock . Also. If this occurs try the following: • • • Confirm the RC scaling factors for the clocks are set properly. Analyzing and Debugging the Clock Tree Results You can use the Clock Tree Browser (Clock .

ALL RIGHTS RESERVED. # # FirstEncounter(TM) Clock Synthesis Technology File Format # MacroModel pin freg/mod004048/CLK 20ps 18ps 20ps 18ps 30ff ClkGroup + CGEN_1 + CGEN_2 RouteTypeName CK1 PreferredExtraSpace 1 TopPreferredLayer 4 COPYRIGHT © 2011.EDI Timing Closure Guide ckECO -postCTS –useSpecFileCellsOnly • A similar flow can be used after detailed routing. CADENCE DESIGN SYSTEMS. PAGE 37 . Be aware that if useful skew was applied during post-CTS optimization. "ckECO postRoute" may undo this because its goal is to minimize skew.: ckECO -postRoute [-useSpecFileCellsOnly] • If you are looking for local skew reduction (skew between talking flipflops) use the -localSkew option: ckECO -postCTS -useSpecFileCellsOnly –localSkew • Check the CTS log file for clock gating element movement during optDesign -postCTS: o Use setPlaceMode "-clockGateAware true" option in placement (see placeDesign section) o Or don't allow gated elements to move during CTS: setCTSMode -optLatencyMoveGate false Clock Specification File Example The following example shows a clock specification file. INC.

INC.EDI Timing Closure Guide BottomPreferredLayer 3 End RouteTypeName LF1 PreferredExtraSpace 0 TopPreferredLayer 4 BottomPreferredLayer 3 End AutoCTSRootPin cgen/i_5/Y MaxDelay 5.0ns MinDelay 0ns MaxFanout 2 MaxSkew 250ps SinkMaxTran 550ps BufMaxTran 550ps NoGating NO DetailReport YES Obstruction YES useCTSRouteGuide YES RouteType CK1 LeafRouteType LF1 RouteClkNet YES PostOpt YES OptAddBuffer YES OptAddBufferLimit 100 Buffer BUFX4 BUFX8 BUFX12 INVX1 MaxCap + BUFX4 1pf + BUFX8 1pf + BUFX12 1pf ThroughPin + df/mod000446/CK ThroughPort + df/mod002300/ax2 LeafPin + PCLK66_gate_i/A rising LeafPort + ssfd2s/D rising PreservePin + cgen/mod000043/A ExcludedPin + freg/mod004048/CLK ExcludedPort COPYRIGHT © 2011. ALL RIGHTS RESERVED. CADENCE DESIGN SYSTEMS. PAGE 38 .

you should adjust the timing constraints as follows. You may need to adjust the clock latencies on the IOs so IO timing does not become the critical path by either adjusting the virtual clock source latencies: set_clock_latency -source xxx <clock> Or adjust IO constraints directly (set_input_delay/set_output_delay) or use the update_io_latency command. INC.EDI Timing Closure Guide + DFF_B/CLK End Post-CTS Optimization The goals of post-CTS optimization include: • • • Fixing remaining design rule violations Optimizing remaining setup violations Correcting timing with propagated clocks At this point in the design flow. • Remove or change the SDC constraints that are not valid postCTS like clock_uncertainty or clock_latency. Typically. COPYRIGHT © 2011. Remember that. since the actual clock skew data is now available. ALL RIGHTS RESERVED. PAGE 39 . You need to update the constraints after clock tree synthesis to adjust clock jitter according to the design. Modeling only the jitter avoids making the timing appear worse than it is. Since timing analysis uses the actual clock delays. it is possible that critical path timing will be worse. CADENCE DESIGN SYSTEMS. the clocks are inserted and preferably routed. • Set the clocks to propagated by adding the following to your SDC file(s): set_propagated_clock [all_clocks] • Adjust the clock uncertainty (set_clock_uncertainty SDC) to model only jitter. users have separate SDC files for pre-CTS and post-CTS timing analysis. Use the update_constraint_mode command to update the SDC files for each operating mode.

• Make sure RC scaling factors are tuned properly. Run timing analysis to check the timing: timeDesign -postCTS -outDir ctsTimingReports If the timing is not similar to pre-CTS timing results check the following: • Was CTS able to achieve the skew constraints? Are these skew constraints within the set_clock_uncertainty set during preCTS timing? • Was clock uncertainty adjusted after CTS to only model jitter? Post-CTS Optimization Command Sequences Typically the same options applied during preCTS optimization are used for postCTS optimization. A jump in negative slack may occur for latches now that their real skew is used for timing analysis.  Signal nets use -preRoute_cap  Clock nets use -postRoute_clkcap (if defined) or postRoute_cap.EDI Timing Closure Guide • Adjust derating applied per each delay corner. COPYRIGHT © 2011. investigate whether the end points are latches. INC. CADENCE DESIGN SYSTEMS. Double-check the clocks are propagated and that the skew is within your specifications. ALL RIGHTS RESERVED. • Use the timeDesign command to check the post-CTS timing: timeDesign -postCTS -outDir postctsTimingReports The timing at this point should be similar to the pre-CTS timing results. o Clock routing will use a different scale factor than the signal nets. PAGE 40 . If the large slack is occurring at other points used GTD to analyze the paths. If there is a large jump in negative slack.

PAGE 41 . COPYRIGHT © 2011. CADENCE DESIGN SYSTEMS. This is recommended if your design has a significant number of hold violations because they are easier to fix prior to routing. EDI System performs trial routing to estimate clock delays. use the following commands: optDesign -postCTS -outDir postctsOptTimingReports • To take advantage of useful skew when optimizing timing in post-CTS mode. INC. • If clock gating cells are on the critical path you can enable clock gate cloning during post-CTS optimization: setOptMode -postCtsClkGateCloning true Hold Optimization At this point run timing analysis to report hold violations: timeDesign -postCTS -hold -outDir postctsHoldTimingReports Timing optimization to fix hold violations can be performed at this point.EDI Timing Closure Guide • To optimize timing after the clock tree has been built. If the number of hold violation is low you can wait until after routing the signal nets. ALL RIGHTS RESERVED. If you do not want EDI System to do this. use the following commands: setOptMode -usefulSkew true optDesign -postCTS [-incr] If you have already performed detail routing on the clock tree. specify the -noECORoute parameter as follows: setOptMode -usefulSkew true optDesign -postCTS -noECORoute [-incr] If you specify -noECORoute before running optimization. EDI System performs global and detailed ECO routing automatically using NanoRoute in post-CTS useful skew mode.

use postRoute hold fixing to fix the remaining violations. it is highly recommended to run hold fixing at postCts stage already (although there is no need to achieve 0ns slack at this stage).. ALL RIGHTS RESERVED. the following sets a hold target slack of -200ps: setOptMode -holdTargetSlack -0.} COPYRIGHT © 2011. • For a design with many hold violated paths. You can use a negative hold target slack to focus hold fixing on the paths with large violations and fix the remaining hold violations after routing. CADENCE DESIGN SYSTEMS.. Then. make sure to run leakage optimization (through optDesign or optLeakagePower) before running Hold fixing since leakage reduction improves Hold timing.EDI Timing Closure Guide To perform hold optimization: optDesign -postCTS -hold -outDir postctsOptHoldTimingReports Tips for Performing Hold Optimization on High Peformance Designs • Try to avoid providing very weak buffers for Hold fixing because they are more sensitive to routing detour and SI. PAGE 42 . • For Multi-Vth design.2 • By default Hold fixing can degrade setup TNS (but not Setup WNS). For example. This can be changed through: setOptMode -fixHoldAllowSetupTnsDegrade true|false • To exclude some path_group/clockDomains from hold fixing you can apply: setOptMode -ignorePathGroupsForHold {groupA groupB . INC.

PAGE 43 . Hold fixing will print a detailed report where each net not buffered will be sorted through several categories. o This will allow the user to identify what are the most critical issues to resolve. o If you want to allow Setup WNS degradation. *info: XXX net(s): Could not be "Degrade max_cap violations". o Avoid over constraining the clock uncertainty. *info: XXX net(s): Could not be fixed because of 'no legal fixed because they would fixed because they would fixed because they would fixed because they would further fixed because they would fixed because they would fixed because they already have fixed because they are set as fixed because they are flagged fixed because they are Multifixed because they are clock fixed because no Always-On- • COPYRIGHT © 2011. INC. o It will help the user in understanding why a given net was not buffered. o Reduce local placement congestions. *info: XXX net(s): Could not be "Degrade max_tran violations".EDI Timing Closure Guide • Things to watch out for: o Make sure that the clock trees are well balanced (inter and intra clock trees). o The different categories listed in the log file are : *info: XXX net(s): Could not be location' *info: XXX net(s): Could not be "degrade setup reg2reg WNS". *info: XXX net(s): Could not be as badly routed. Adding cell padding may sometime help. ALL RIGHTS RESERVED. *info: XXX net(s): Could not be "Degrade Hold". *info: XXX net(s): Could not be "Violating DRV". *info: XXX net(s): Could not be dont_touch. you should set a negative setup target slack (setOptMode -setupTargetSlack ) In Verbose mode (setOptMode -verbose true). *info: XXX net(s): Could not be nets. *info: XXX net(s): Could not be "degrade setup TNS" *info: XXX net(s): Could not be "degrade setup WNS". *info: XXX net(s): Could not be Driver nets. CADENCE DESIGN SYSTEMS.

Tips for Performing Hold Optimization on Congested and High Utilization Designs • In a multi-Vth library scenario. CADENCE DESIGN SYSTEMS. make sure that Leakage Optimization was run before Hold fixing. INC.EDI Timing Closure Guide Buffers are usable. To allow overlaps during post-route optimization as well set the following: setOptMode -fixHoldAllowOverlap true This can be also used post-route but should not be used with SI optimization because the refinePlace call may not be made. delay buffer addition rate increases exponentially o Try useful skew optimization for RAM and Register files COPYRIGHT © 2011. This provides optimization more opportunity to fix violations. *info: XXX net(s): Could not be fixed because of "internal failure". PAGE 44 . To enable overlaps during post-route optimization as well set the following: setOptMode -fixHoldAllowOverlap true • Control hold time margins o Beyond certain hold margin. *info: XXX net(s): Could not be fixed because "no valid node" were found on net. • "setOptMode -fixHoldAllowOverlap" controls if hold fixing is limited to purely legal moves (no overlaps). ALL RIGHTS RESERVED. When set to "true" hold optimization allows initial cell insertion to overlap cells and then refinePlace legalizes the cells placement. • Hold fixing is allowed to overlap cells during post-CTS hold optimization but not during post-route optimization. When set to the default value of "auto" hold optimization is allowed to create overlaps during post-CTS optimization but not during post-route optimization.

NanoRoute performs a DRC and cleans up violations. • • • • • • Make sure the LEF file contains a sufficient number and variety of vias (hammer-head. o Check with your library provided or foundry for the latest technology LEF to use. there should be few. NanoRoute can perform timing-driven and SI-driven routing concurrently.EDI Timing Closure Guide Checking Timing You can use the following commands to report setup and hold time violations after post-CTS optimization. regenerate tracks with the generateTracks command. NanoRoute routes the signals which are critical for signal integrity appropriately to minimize cross-coupling between these nets which would lead to post-route signal integrity issues. timing violations left in the design. timeDesign -postCTS -outDir postctsOptTimingReports timeDesign -postCTS -hold -outDir postctsOptTimingReports Detailed Routing After post-CTS optimization. ALL RIGHTS RESERVED. Unfix the clock nets before using NanoRoute Make sure the top max routing later is set appropriately. stacked. Routing the design without degrading timing or creating signal integrity violations. Check the definition of tracks in the DEF file. and so forth). PAGE 45 . Improving Timing during Routing The following tips can help achieve better timing results during the routing phase of the design. if any. INC. If timing is way off and/or there is local or global congestion. The goals of detailed routing include: • • Routing the design without DRC or LVS violations. If the tracks are poorly defined. COPYRIGHT © 2011. return to post-CTS optimization and optimize further or run non-timing-driven routing. CADENCE DESIGN SYSTEMS. Routing Command Sequence The following example shows the use of NanoRoute to do detailed routing. Specify required NonDefaultRules (NDRs) and/or shield routing.

vias are extremely expensive for resistance. o After routeDesign. setNanoRouteMode -routeWithTimingDriven false setNanoRouteMode -droutePostRouteSpreadWire true routeDesign -wireOpt setNanoRouteMode -droutePostRouteSpreadWire false COPYRIGHT © 2011. Achieving the highest possible double cut coverage helps reduce resistance for vias that cannot be eliminated: setNanoRouteMode –routeConcurrentMinimizeViaCountEffort medium setNanoRouteMode -drouteUseMultiCutViaEffort medium | high • When using routeDesign. use non-timing driven wire spread to spread all potential wires (for best SI results). PAGE 46 . INC.EDI Timing Closure Guide changeUseClockNetStatus -noFixedNetWires routeDesign Note: routeDesign automatically sets "setNanoRouteMode –routeWithTimingDriven true -routeWithSiDriven true". ALL RIGHTS RESERVED. If you are using globalDetailRoute in place of routeDesign make sure you manually set these options to true. CADENCE DESIGN SYSTEMS. • Post route wire spreading significantly reduces SI impact. Tips for Routing High Performance Designs • For many RC corners at 40nm and below. by default timing driven and SI driven are enabled. make sure they are inserted prior to the initial route. High effort SI routing can be enforced using: setNanoRouteMode -routeSiEffort high • If filler cells containing metal obstruction other than the followpins are to be used.

PAGE 47 . This engine supports distributed processing.Invokes the Turbo QRC (TQRC) extraction mode. high . It is important to now set the extraction mode to post-route and specify the extractor to use. PostRoute Extraction All nets are now routed. we recommend cover blockage over MACRO's (RAM/ROM) rather than pin cut-outs from OBS (blockage). o o COPYRIGHT © 2011.Invokes the Integrated QRC (IQRC) extraction engine. ALL RIGHTS RESERVED. TQRC performance and accuracy falls between native detailed extraction and IQRC engine.  TQRC engine is recommended for process nodes < 65nm. CADENCE DESIGN SYSTEMS. INC. In addition. • Specify the engine to be postRoute: setExtractRCMode -engine postRoute • Set -effortLevel so extractRC uses your desired extractor: setExtractRCMode -effortLevel low|medium|high o low .EDI Timing Closure Guide Tips for Routing Congested Designs • The following will help the routing with some runtime impact and setup timing degradation as NanoRoute will detour some of the nets to ease the congestion: setNanoRouteMode -grouteMinimizeCongestion true • For 65nm and below. IQRC is recommended for extraction after ECO. medium .  IQRC provides superior accuracy compared to TQRC. This is the same as specifying the "-engine postRoute" setting.Invokes the native detailed extraction engine. Note: This setting does not require a QRC license.

In addition to the timing violations caused by inaccurate route topology modeling. it is critical at this point not to introduce any additional topology changes beyond those needed to fix the existing violations.EDI Timing Closure Guide IQRC supports distributed processing. Note: IQRC requires a QRC license. INC. Checking Timing Use the following command to do a post-route timing check: timeDesign -postRoute -outDir postrouteTimingReports timeDesign -postRoute -hold -outDir postrouteTimingReports If timing jumps at this point compared to timing before routing check the following: Are the post-route RC scaling factors set properly? Is the routing topology similar between trialRoute and NanoRoute? Compare the same paths between post-CTS and post-Route databases and for large differences in loads. create the new RC graph at the corresponding point. The primary sources of these timing violations include: • • Inaccurate prediction of the routing topology during optimization due to congestion-based detour routing Incremental delays due to parasitics coupling pre-route Since the violations at this stage are due to inaccurate modeling of the final route topology and the attendant parasitics. One of the strengths of post-route optimization is the ability to simultaneously cut a wire and insert buffers. CADENCE DESIGN SYSTEMS. there should be very few violations that need correction. ALL RIGHTS RESERVED. Making unnecessary changes to the routing at this point can lead to a scenario where fixing one violation leads to the creation of others. • • Post-Route Optimization During post-route optimization. the parasitics cross-coupling of neighboring nets can cause the following problems that need to be addressed in high speed designs: COPYRIGHT © 2011. and modify the graph to estimate the new parasitics for the cut wire without re-doing extraction. This cascading effect creates a situation where it becomes impossible to close on a final timing solution with no design rule violations. PAGE 48 .

ECHO. PAGE 49 .EDI Timing Closure Guide • • An increase or decrease in incremental delay on a net due to the coupling of its neighbors and their switching activity. • • • • Watch for routing congestion during floorplanning and especially after detailed routing. o Consider running the congOpt command on the design to eliminate local hot spots or adjust your floorplan Use NanoRoute advanced timing with SI-driven routing options during detailed routing. CADENCE DESIGN SYSTEMS. They are magnified in designs with small geometries and in designs with high clock speeds. For example: o setNanoRouteMode -routeWithTimingDriven true o setNanoRouteMode -routeWithSiDriven true Fix transition time violations. o Slow transitions introduce a larger delay penalty or incremental delay. INC. Data Preparation SI optimization requires certain preparation: • • • • • Make sure cdB libraries are specified for each cell for each delay corner. Glitches (voltage spikes) that can be caused in one signal route by the switching of a neighbor resulting in a logic malfunction. These effects need to be analyzed and corrected before a design is completed. You must be in On Chip Variation (OCV) mode to see simultaneous clock pushout / pullin. o Highly-accurate CeltIC analysis requires the use of accurate noise models like cdB. Prepare all of the required noise models. consider the following techniques if you have difficulty achieving signal integrity closure on your design. COPYRIGHT © 2011. or xILM. ALL RIGHTS RESERVED. The use of blackbox (missing) models could lead to a significant number of false violations. Enable this using "setAnalysisMode analysisType onChipVariation" Confirm your CeltIC settings match your signoff tool Confirm coupling filter settings match your signoff tool Enable SI CPPR through "set_global timing_enable_si_cppr true" (this is the default) Additionally.

 Post-Route Optimization Command Sequences The Advanced Analysis Engine (AAE) is a new unified delay calculation engine that simultaneously computes base and SI delays.cdB file. CADENCE DESIGN SYSTEMS. Characterize your memory and analog block using the make_cdb utility. Unlike the default flow. New features may not function properly when used with an old . ALL RIGHTS RESERVED. Create XILM models for sub blocks to model their noise sensitivity at the chip level. AAE based optimization does not require four steps optimization: Default: optDesign optDesign optDesign optDesign -postRoute -postRoute -hold -postRoute -si -hold -postRoute -si AAE (recommended): optDesign -postRoute optDesign -postRoute -hold To run AAE based SI fixing: <Load routed data base with MMMC setup> setAnalysisMode -analysisType onChipVariation -cppr both setDelayCalMode -engine default -SIAware true optDesign -postRoute optDesign -postRoute -hold For more information on the AAE flow see the application note: PostRoute Optimization Using the Advanced Analysis Engine (AAE). AAE can perform incremental SI delay computation during timing optimization.EDI Timing Closure Guide o o You must recalibrate the noise library with each release of CeltIC. AAE also capable of multithreading thus gives substantial runtime gains in timing closure. PAGE 50 . Tips for Performing Post-Route Optimization High Performance Designs COPYRIGHT © 2011. INC. hence provide accurate feedback to optimization engine.

INC. To temporarily set them as + PLACED during optDesign. PAGE 51 . CADENCE DESIGN SYSTEMS. The registers by default are marked + FIXED by clockDesign and cannot be resized eventhough postRoute optimization can resize flops.0 Make sure you are in OCV analysis (MMMC setup required) to calculate pushin/pullout timing properly: setAnalysisMode -analysisType onChipVariation Note if the design is not in OCV mode.EDI Timing Closure Guide • For multi-VT designs. ALL RIGHTS RESERVED. you can apply: setOptMode -unfixClkInstForOpt true The local density by default is limited to 98%. after routing there can be large WNS/TNS jumps due to the sensitivity of HVT cells o runtime of postRoute optimization can be significantly impacted by large TNS o Using optLeakagePower -fixTimingOnly prior to optDesign postRoute can massively speed up closure  Only works for multi-VT  Does not have much impact when designs has already mainly LVT cells. clock SI pushout/pullin will not be correct. If optimization is prematurely exiting due to local placement hotspots this can be increased to 100% using setOptMode -maxLocalDensity 1. Make sure your extraction filters correlate to your signoff extraction o when using iQRC the filters typically can be set to the exact signoff values  make sure to use setExtractRCMode -capFilterMode relAndCoup  StarRC has no total_c_th equivalent so set this to 0 for these flows For postRoute optimization. you may want to force the tool • • • • COPYRIGHT © 2011.

So there is a tendency to be pessimistic compared to Celtic. you need to run signalStorm+Celtic based timeDesign between setup and hold optimization or at the end of hold optimization. make sure it correlates with EDI System by verifying SDC constraints are applied consistently between the tools. So if you want to check your QOR. ALL RIGHTS RESERVED. Optimization final summary is AAE estimation based report only. Optimizing With 3rd Party SPEF or SDF If you are using a 3rd Party tool for extraction or timing analysis the most important step is to make sure they correlate with EDI System's corresponding function. CADENCE DESIGN SYSTEMS. Being a fast SI engine. If you are using PrimeTime-SI for signoff set "setSIMode -analysisType pessimistic" prior to timeDesign for better correlation. Please use 'setSIMode -analysisType default' in AAE and Celtic flows for better correlation. if you are using a 3rd Party extractor make sure the RC scaling factors are set properly within EDI System. If you are using a 3rd Party timing analysis tool. AAE being pessimistic compared to Celtic means it does not need 'setSIMode -analysisType pessimistic' setting for Primetime correlation. The delay calculation and timing analysis results between EDI System and the 3rd Party tool should also correlate.EDI Timing Closure Guide to only allow legal resizing to avoid placement legalization and thus limit routing changes: setOptMode -postRouteAllowOverlap false Checking Timing AAE is a fast SI engine so it does not perform circuit simulations to compute SI delays. INC. For example. PAGE 52 . it does not completely correlate with Celtic (signoff SI engine). AAE is tuned well to work with optimization engine in order to provide better QOR. COPYRIGHT © 2011. For example: timeDesign -postRoute -si -outDir final_setup timeDesign -postRoute -si -hold -outDir final_hold If you are using Encounter Timing System (ETS) for signoff timing make sure the CeltIC settings are consistent between EDI System and ETS.

o Use -hold if you need to perform hold fixing based on the the SPEF. The delays in the SDF will be used.sdf read_sdf -view view2 sdf2. If a view was not given an SDF file.spef -rc_corner rc_corner2 .. CADENCE DESIGN SYSTEMS. INC.EDI Timing Closure Guide If timing violations occur when using SPEF from a 3rd Party extractor you can import the SPEF into EDI System and perform optimization. optDesign -postRoute [-si] [-hold] -outDir spefFlowTimingReports • • The -si and -hold options are optional in the above command. This is accomplished by first using QRC to generate detailed extraction data and then using the specified timing analysis engine for a final analysis of setup and hold data. COPYRIGHT © 2011. optDesign will use the SPEF for initial timing to determine the best location to optimize the paths. optDesign can also optimize based on SDF from a 3rd Party timing analyzer. o Use -si if you need to perform SI fixing based on the SPEF.. The flow is: spefIn rc_corner1. You must import a SPEF for each RC corner. EDI System will run detail extraction and delay calculation for that specific view.spef -rc_corner rc_corner1 spefIn rc_corner2. ALL RIGHTS RESERVED. you should provide an SDF file for each active view in the design. but the slews must be generated. PAGE 53 .sdf optDesign -postRoute -useSDF [-hold] -outDir sdfFlowTimingReports • • Note in order to use SDF information in MMMC analysis mode. The flow to optimize based on SDF is: read_sdf -view view1 sdf1. You can also spefIn to avoid the extraction. Timing Sign Off The goal of timing sign off is to verify that the design meets the specified timing constraints. This is useful when the timing analyzer reports timing violations EDI System did not. optDesign will run extraction to calculate slew values because SDF doesn't contain slews.

spef -rc_corner rc_corner1 spefIn rc_corner2. These can be found at http://support. • • If you are using a 3rd party extractor use spefIn to read the SPEF for each RC corner then run timeDesign using the -reportOnly option: spefIn rc_corner1.spef -rc_corner rc_corner2 . you need to ensure that the EDI System configuration file includes a technology file and a LibGen cell library database created with the runLibGen command. training and documentation related to timing closure..EDI Timing Closure Guide At this point in the design process. (?? To Do?) For more information about setting up the libraries for QRC. PAGE 54 . If the timing degrades compared to post-route timing check the following: Were the post-route RC scaling factors properly set which correlate to the signoff extractor? See the Application Note "EDI to ETS Correlation: Guidelines on How to Debug and Correlate Timing and SI results" at the end of this document.cadence. INC. Generates the hold timing reports. final routing and post-route optimization is complete.. timeDesign -signoff -reportOnly -outDir signOffTimingReports timeDesign -signoff -hold -reportOnly -outDir signOffTimingReports Additional Resources Following are additional application notes. ALL RIGHTS RESERVED. Runs QRC to generate detailed parasitics. The following command sequence generates the reports needed to verify timing: timeDesign -signoff -outDir signOffTimingReports timeDesign -signoff -hold -reportOnly -outDir signOffTimingReports These commands perform the following operations: 1. 2. For QRC to run. 3. Uses the detailed parasitics and generates the setup timing reports. CADENCE DESIGN SYSTEMS. refer to the chapter RC Extraction in the EDI System User Guide.com: COPYRIGHT © 2011.

ALL RIGHTS RESERVED.Guidelines on How to Debug and Correlate Timing and SI results • • • • • COPYRIGHT © 2011. CADENCE DESIGN SYSTEMS. PAGE 55 .EDI Timing Closure Guide • NanoRoute Recommended Options with emphasis on 32nm and below advance node/technology (EDI) Encounter Digital Implementation System Foundation Flows Guide How to Generate Scaling Factors for RC Correlation PostRoute Optimization Using the Advanced Analysis Engine (AAE) Guide to Clock Tree Synthesis (CTS) in a block or flat chip using EDI system EDI to ETS Correlation . INC.

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