VARIOUS ABSTRACTION LEVEL OF VHDL

1. BEHAVIORAL SIMULATION : In this large pieces of a system as black boxes with
inputs and outputs. (often using VHDL or Verilog)

2. FUNCTIONAL SIMULATION: ignores timing and includes unit-delay simulation ,
which sets delays to a fixed value (for example, 1 ns). 3. STATIC TIMING ANALYSIS In order to check the timing performance. a system is partitioned into ASICs and a timing simulation is performed for each ASIC separately (otherwise the simulation run times become too long). static timing analysis analyse logic in a static manner, computing the delay times for each path, named as static timing analysis because it does not require the creation of a set of test (or stimulus) vectors (an enormous job for a large ASIC). 4. LOGIC LEVEL STIMULATION a. GATE LEVEL ANALYSIS be used to check the timing performance of an ASIC. In a gate-level simulator a logic gate or logic cell (NAND, NOR, and so on) is treated as a black box modeled by a function whose variables are the input signals. The function may also model the delay through the logic cell. Setting all the delays to unit value is the equivalent of functional simulation. b. SWTITCHING ANALYSIS which models transistors as switches—on or off. Switch-level simulation can provide more accurate timing predictions than gate-level simulation, but without the ability to use logic-cell delays as parameters of the models. 5. TRANSISTOR LEVEL OR CIRCUIT LEVEL SIMULATION the most complex and time-consuming, requires models of transistors, describing their nonlinear voltage and current characteristics.

and outstanding product support. Process. aided by dynamically updated windows. An easy-to-use graphical user interface enables you to quickly identify and debug problems. and re-simulate without leaving the simulator. HDL simulation now can be an even more fundamental step within your design flow with the tight integration of the ISim within your design environment. MODELSIM ALTERA is the industry-leading.PE. our entry-level simulator. Once a problem is found. recompile. . Verilog. Signals. or mixed-language simulation environments.VARIOUS TYPES OF SIMULATORS AT VARIOUS ABSTRACTION LEVELS: BEHAVIORAL SIMULATORS: 1. Coupled with the most popular HDL debugging capabilities in the industry. offers VHDL. and Variables windows. Windows-based simulator for VHDL. selecting a design region in the Structure window automatically updates the Source. XILINX ISE SIMULATOR (I SIM) VHDL provides a complete. VHDL and SystemVerilog Design Mixed-HDL Simulation option Code Coverage option Enhanced debug option Windows 32-bit 2. full-featured HDL simulator integrated within ISE. Verilog. ease of use. These cross linked ModelSim windows create a powerful easy-to-use debug environment. ModelSim PE is known for delivering high performance. you can edit. FEATURES:             Partial VHDL 2008 support Transaction wlf logging support in all languages including VHDL Windows7 Support SecureIP support SystemC option RTL and Gate-Level Simulation Integrated Debug Verilog. ModelSim. For example. or mixed-language simulation.

the digital engine for mixed-signal verification working with Virtuoso simulators. MGT. 5.FEATURES:                       Mixed language support Supports VHDL-93 and Verilog 2001 Native support for all HardIP blocks PPC. 6. and convergence needed to speed silicon realization.One-click compilation and simulation Hardware Cosimulation capability Offload a design or a portion of the design to hardware Accelerate RTL simulation by up to 50x Xilinx simulation libraries “built-in” Additional mapping or compilation not required 3. 4. PCIe. No special license requirements Supports AXI Bus Functional Model (BFM) Multi-Threaded compilation Post-Processing capabilities Tcl scriptable GUI and batch mode simulation run Standalone Waveform viewing capabilities Debug capabilities Waveform tracing. etc. QUARTUS II SIMULATOR SYNOPSIS VHDL SYSTEM SIMULATOR EXPRESSO CADENCE NC VHDL Incisive Enterprise Simulator Multi-language simulation fuels testbench automation. waveform viewing. low-power. metric driven verification. HDL source debugging Power Analysis and optimization using SAIF Memory Editor for viewing and debugging memory elements Single click re-compile and re-launch of simulation Integrated with ISE Design Suite and PlanAhead application Easy to use . IES is the core engine for lowpower verification working closely with Conformal LP. the testbench engine . and mixed-signal verification Incisive Enterprise Simulator (IES) provides the most comprehensive IEEE language support with unique capabilities supporting the intent. abstraction.

and the five most common semiconductor devices: diodes. Verilog®. SystemVerilog/e class libraries. inductors. lossless and lossy transmission lines (two separate implementations). and CPF  Delivers the highest possible performance for mixed-language. SPICE has built-in models for the semiconductor devices. and the user need specify only the pertinent model parameter values. and low-power designs. and linear ac analyses. capacitors. transactional. and reuse for increased productivity  Ensures verification quality by tracking industry-standard coverage metrics. uniform distributed RC lines. ALDEC 8. mixed-signal. . and HDL code. SystemVerilog. VHDL.for simulation acceleration with Xtreme and Palladium. plus automatic data and assertion checking  Drives and guides verification with an automatically backannotated and executable verification plan  Creates reusable sequences and multi-channel virtual sequences on top of a multilanguage verification environment  Configures existing Universal Verification Components (UVCs) or quickly constructs all-new UVCs  Enables advanced debug using SimVision for transaction-level models. including the ability to “hot swap” the RTL simulation in/out of thePalladium XP series of accelerators/emulators  7. four types of dependent sources. Circuits may contain resistors. low-power. BJTs.  Fuels testbench automation. PSL. emerging UVM class library. low-power.6. OVM class library. MESFETs. independent voltage and current sources. SystemC®. While SPICE3 is being developed to include new features. analysis. and the RTL engine working with TLM verification solutions. across multiple levels of abstraction. and MOSFETs. including functional. SVA. Open Verification Library (OVL). it continues to support those capabilities and models which remain in extensive use in theSPICE2 program. transient mixed-signal. HSPICE : SPICE is a general-purpose circuit simulation program for nonlinear dc. SystemC Verification Library. JFETs. mutual inductors. switches. and traditional waveform analysis  Supports e. The SPICE3 version is based directly on SPICE 2G. nonlinear transient.

e.     .mode. MENTOR GRAPHICS SIMULATOR TOOLS FOR ASIC DESIGN 2.FUNTIONAL SIMULATORS : 1. 2.SPICE . A functional model is obtained to represent the new altered circuit. For "quick" simulations of digital circuits Useful for confirming basic operation of digital circuit layouts. COMPASS MIXSIM 2. The addition of scheduling commands ("at". IRSIM VERSION 9. It is much easier to write complicated testbench simulations using IRSIM. and "whenever") put IRSIM into the same class as Verilog simulators. FUNCTIONAL FAULT SIMULATION OF VHDL GATE LEVEL A gate level circuit is modified to include logic gates where faults are to be injected. BSIM3 and BSIM4.sim" file format.7 SWITCH-LEVEL SIMULATOR:     "switch-level" simulator For simulating digital circuits Fesigned to read. This faultable model can be simulated using a standard VHDL simulator. SYNOPSYS 4. 3. MODELSIM ALTERA QUARTUS II SIMULATOR CADENCE NC VHDL EXPRESSO GATE LEVEL SIMULATORS: 1. EXPRESSO 5. Parts of Magic were developed especially for use with IRSIM. a forked process communicating through a pipe). FILETYPE . THE SWITCH-LEVEL SIMULATION 1. Values assigned to the inputs of the new additions of the circuit have the effect of injecting stuck-at faults at various lines of the original circuit. while displaying information about the values of signals directly on the VLSI layout. 4. allowing IRSIM to run a simulation in the "background" (i.. the ". "every". Bipolar simulation models for nmos and pmos level=9 and level=14 for spice3f5 and spice3e2 3. "when".

the analysis of the time spent by engineers to complete their designs shows that most of their valuable time can be saved with a simulator offering appropriate design bug detection features as well as debugging features. These features address the request from designers to rely on a simulator which can truly help them improve their design productivity for as faster and safer time-to-fab. to optimize system performance as early as possible in the design cycle and before the prototyping stage Interoperability o o o Compatibility with frameworks and complementary solutions (HSPICE. SMASH is the mixedsignal simulator of choice for designers eager to improve their productivity! FEATURES       Simultaneous display of analog and logic simulation results in an interactive waveform viewer both interactively during the analysis runtime and in postprocessing Easy setup of trade-off between speed and accuracy plus added-value features for design bug detection and eradication IEEE model encryption for source code protection in order to exchange data safely Simulation results calibrated against Silicon measurements Required flexibility to model the IC with its application schematics of reference.TRANSISTOR LEVEL OR CIRCUIT LEVEL SIMULATOR  Virtually all circuit-level simulators used for ASIC design are commercial versions of the SPICE (or Spice . ModelSim. per the Application Hardware Modeling (AHM) approach. With the mixed-signal simulator SMASH. Simulation Program with Integrated Circuit Emphasis ) developed at UC Berkeley OTHER SIMULATORS SMASH Mixed-Signal Simulator SMASH is a seamless IC-PCB mixed-signal simulator enabling the development and verification of analog and mixed-signal Silicon IPs and Integrated Circuits (IC) as well as the optimization of application schematics thanks to its unique multi-domain capabilities. Indeed. PSpice) to add new modeling and simulation capabilities to an existing design flow SMASH integrated as Laysim in Laytools suite from TexEDA Schematic-driven Layout between SLED and DW2000 from Design Workshop Technologies . designers benefit from innovative features which enable efficient and fast detection of design defects with a fine control for tuning the speed accuracy trade-offs.

o Easy communication between S-Edit from Tanner EDA and SMASH .

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