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An Flag Final

An Flag Final

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Published by Nirjhar Ghosh

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Published by: Nirjhar Ghosh on Sep 09, 2012
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09/09/2012

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library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.

ALL;

entity an is Port ( x : in std_logic_vector(3 downto 0); y : in std_logic_vector(3 downto 0); z : out std_logic_vector(3 downto 0); f: out std_logic_vector(2 downto 0));

end an; architecture Behavioral of an is begin process(x,y) variable p:std_logic; variable s:std_logic_vector(3 downto 0); constant c:std_logic:='0'; begin s := x and y; z<=s; p:=not (((s(3)xor s(2))xor s(1))xor s(0)); f(0)<=p;

end process.if c='1'then f(2)<= '1'. end Behavioral. if s="0000" then f(1)<='1'. end if. end if. . else f(1)<='0'. else f(2)<='0'.

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