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M.E. DEGREE EXAMINATION, JANUARY 2010 First Semester Applied Electronics

AP 9212 — ADVANCED DIGITAL SYSTEM DESIGN (Common to M.E. VLSI Design) (Regulations 2009) Time: Three hours Answer ALL Questions

PART A — (10 × 2 = 20 Marks) 1. 2. 3. 4.

What is the difference between a mealy machine and a Moore machine? State two reasons why a state table might be incompletely specified.

What is the most important consideration in making state assignments for asynchronous networks? Define test coverage. What are propagation D-cuts?

5. 6. 7. 8. 9.

What are the limitations of PLDs using AND OR structure? Write down the syntax for declaring a package. Define test bench.

4

0

10.

1

Differentiate the three basic types of PLD.

4

Define a primitive flow table.

0

1

4
Maximum: 100 Marks

0

Question Paper Code: W7602

1

PART B — (5 × 16 = 80 Marks) 11. (a) Design a sequential circuit to convert BCD to excess 3 codes. Or (b)

A Moore sequential network has one input and one output. The output should be 1 if the total number of 1’s received is odd and the total number of 0’s received is an even number greater than 0. Derive the state graph and table. (16) How can essential hazards be determined and eliminated from a network? (16) Or

12.

(a)

(b) 13. (a)

Design a vending machine controller with suitable circuits.

4

Explain the procedure for designing fault-secure PLA with suitable example. (16) Or

(ii) 14. (a)

Explain the logic diagram of built in logic block observer.

0
Or Or ———————— 2

(b)

(i)

Explain how the Boolean difference method is used for test generation with example. (8) (8) (16)

Design a 4 bit binary counter using PAL chip.

(b)

Explain how FPGA can be programmed to implement a finite state machine. (16) Using structural modeling write a VHDL for a 4 bit shift register. Also write a test bench for it. (16)

15.

(a)

(b)

Write a VHDL code for the following circuits:

1

(i)

8 : 1 multiplexer Serial added using finite state machine approach.

4

1

(ii)

4

0

0
(16) (4) (12)

1
(16)

W 7602

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