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Power Dissipation
Outline
• Motivation to estimate power dissipation
• Sources of power dissipation
• Dynamic power dissipation
• Static power dissipation
• Metrics
• Conclusion
Need to estimate power dissipation
Power dissipation affects
• Performance
• Reliability
• Packaging
• Cost
• Portability
Where Does Power Go in CMOS?
• Dynamic Power Consumption
• Short Circuit Currents
• Leakage
Charging and Discharging Capacitors
Short Circuit Path between Supply Rails during Switching
Leaking diodes and transistors
Node Transition Activity and Power
Consider switching a CMOS gate for N clock cycles
E
N
C
L
V
dd

2
n N ( )  =
n(N): the number of 0>1 transition in N clock cycles
E
N
: the energy consumed for N clock cycles
P
avg
N · ÷
lim
E
N
N
 f
clk
 =
n N ( )
N

N · ÷
lim
\ .
 
C 
L
V
dd

2
f
clk
 =
o
0 1 ÷
n N ( )
N

N · ÷
lim =
P
avg
= o
0 1 ÷
C 
L
V
dd

2
f
clk

•Due to charging and discharging of capacitance
Activity factors of basic gates
• AND
• OR
• XOR
B A B A
p p p p ) 1 ( ÷ = o
)] 1 )( 1 ( 1 )[ 1 )( 1 (
B A B A
p p p p ÷ ÷ ÷ ÷ ÷ = o
) 2 )]( 2 ( 1 [
B A B A B A B A
p p p p p p p p ÷ + ÷ + ÷ = o
Dynamic Power dissipation
• Power reduced by reducing V
dd,
f, C and also activity
• A signal transition can be classified into two categories
a functional transition and
a glitch
Glitch Power Dissipation
• Glitches are temporary changes in the value of the
output – unnecessary transitions
• They are caused due to the skew in the input signals to a
gate
• Glitch power dissipation accounts for 15% – 20 % of the
global power
• Basic contributes of hazards to power dissipation are
– Hazard generation
– Hazard propagation
Glitch Power Dissipation
• P = 1/2 .CL.Vdd . (Vdd – Vmin) ;
Vmin : min voltage swing at the output
• Glitch power dissipation is dependent on
– Output load
– Input pattern
– Input slope
Glitch Power Dissipation
• Hazard generation can be reduced by gate sizing and
path balancing techniques
• Hazard propagation can be reduced by using less
number of inverters which tend to amplify and
propagate glitches
Short Circuit Power Dissipation
• Short circuit current occurs during signal transitions
when both the NMOS and PMOS are ON and there is a
direct path between V
dd
and GND
• Also called crowbar current
• Accounts for more than 20% of total power dissipation
• As clock frequency increases transitions increase
consequently short circuit power dissipation increases
• Can be reduced :
– faster input and slower output
– V
dd
<= V
tn
+ V
tp

• So both NMOS and PMOS are not on at the same time
Static Power Consumption
V
in
=5V
V
out
C
L
Vdd
I
stat
P
stat
= P
(In=1)
.V
dd
. I
stat
• Dominates over dynamic consumption
• Not a function of switching frequency
Wasted energy …
Should be avoided in almost all cases
Static Power Dissipation
• Power dissipation occurring when device is in standby
mode
• As technology scales this becomes significant
• Leakage power dissipation
• Components:
– Reverse biased pn junction
– Sub threshold leakage
– DIBL leakage
– Channel punch through
– GIDL Leakage
– Narrow width effect
– Oxide leakage
– Hot carrier tunneling effect
Principles for Power Reduction
• Prime choice: Reduce voltage!
– Recent years have seen an acceleration in
supply voltage reduction
– Design at very low voltages still open
question (0.6 … 0.9 V by 2010!)
• Reduce switching activity
• Reduce physical capacitance
– Device Sizing
Factors affecting leakage power
• Temperature
– Subthreshold current increases exponentially
• Reduction in Vt
• Increase in thermal voltage
– BTBT increases due to band gap narrowing
– Gate leakage is insensitive to temperature change
Factors affecting leakage power
• Gate oxide thickness
– Subthreshold current decreases in long channel transistors and
increases in short channel
– BTBT is insensitive
– Gate leakage increases as thickness reduces
Solutions
• MTCMOS
• Dual Vt
• Dual Vt domino logic
• Adaptive Body Bias
• Transistor stacking
Metrics
• Power Delay product
• Energy Delay Product
– Average energy per instruction x average inter
instruction delay
• C
unit_area
– Capacitance per unit area
Conclusion
• Power dissipation is unavoidable especially as
technology scales down
• Techniques must be devised to reduce power dissipation
• Techniques must be devised to accurately estimate the
power dissipation
• Estimation and modeling of the sources of power
dissipation for simulation purposes
Outline • • • • • • Motivation to estimate power dissipation Sources of power dissipation Dynamic power dissipation Static power dissipation Metrics Conclusion .
Need to estimate power dissipation Power dissipation affects • Performance • Reliability • Packaging • Cost • Portability .
Where Does Power Go in CMOS? • Dynamic Power Consumption Charging and Discharging Capacitors • Short Circuit Currents Short Circuit Path between Supply Rails during Switching • Leakage Leaking diodes and transistors .
fclk = lim .Node Transition Activity and Power •Due to charging and discharging of capacitance Consider switching a CMOS gate for N clock cycles E N = CL V dd2 n N EN : the energy consumed for N clock cycles n(N ): the number of 0>1 transition in N clock cycles EN 2 n N P avg = lim . C Vdd f clk N N N N L 0 1 = n N lim N N P avg = 0 1 C Vdd 2 f clk L .
Activity factors of basic gates • AND • OR • XOR (1 p A p B ) p A p B (1 p A )(1 p B )[1 (1 p A )(1 p B )] [1 ( p A p B 2 p A p B )]( p A p B 2 p A p B ) .
f. C and also activity A signal transition can be classified into two categories a functional transition and a glitch .Dynamic Power dissipation • • Power reduced by reducing Vdd.
Glitch Power Dissipation • Glitches are temporary changes in the value of the output – unnecessary transitions • They are caused due to the skew in the input signals to a gate • Glitch power dissipation accounts for 15% – 20 % of the global power • Basic contributes of hazards to power dissipation are – Hazard generation – Hazard propagation .
(Vdd – Vmin) . Vmin : min voltage swing at the output Glitch power dissipation is dependent on – Output load – Input pattern – Input slope .Glitch Power Dissipation • • P = 1/2 .CL.Vdd .
Glitch Power Dissipation • • Hazard generation can be reduced by gate sizing and path balancing techniques Hazard propagation can be reduced by using less number of inverters which tend to amplify and propagate glitches .
Short Circuit Power Dissipation • Short circuit current occurs during signal transitions when both the NMOS and PMOS are ON and there is a direct path between Vdd and GND • Also called crowbar current • Accounts for more than 20% of total power dissipation • As clock frequency increases transitions increase consequently short circuit power dissipation increases • Can be reduced : – faster input and slower output – Vdd <= Vtn + Vtp • So both NMOS and PMOS are not on at the same time .
Istat • Dominates over dynamic consumption Wasted energy … • Not a function of switching frequency Should be avoided in almost all cases .Static Power Consumption Vd d Istat Vo ut CL Vin =5V Pstat = P(In=1).Vdd .
Static Power Dissipation • Power dissipation occurring when device is in standby mode • As technology scales this becomes significant • Leakage power dissipation • Components: – Reverse biased pn junction – Sub threshold leakage – DIBL leakage – Channel punch through – GIDL Leakage – Narrow width effect – Oxide leakage – Hot carrier tunneling effect .
Principles for Power Reduction • Prime choice: Reduce voltage! – Recent years have seen an acceleration in supply voltage reduction – Design at very low voltages still open question (0.6 … 0.9 V by 2010!) • Reduce switching activity • Reduce physical capacitance – Device Sizing .
Factors affecting leakage power • Temperature – Subthreshold current increases exponentially • Reduction in Vt • Increase in thermal voltage – BTBT increases due to band gap narrowing – Gate leakage is insensitive to temperature change .
Factors affecting leakage power • Gate oxide thickness – Subthreshold current decreases in long channel transistors and increases in short channel – BTBT is insensitive – Gate leakage increases as thickness reduces .
Solutions • • • • • MTCMOS Dual Vt Dual Vt domino logic Adaptive Body Bias Transistor stacking .
Metrics • Power Delay product • Energy Delay Product – Average energy per instruction x average inter instruction delay • Cunit_area – Capacitance per unit area .
Conclusion • Power dissipation is unavoidable especially as technology scales down • Techniques must be devised to reduce power dissipation • Techniques must be devised to accurately estimate the power dissipation • Estimation and modeling of the sources of power dissipation for simulation purposes .
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