P. 1
NVIDIA CUDA ProgrammingGuide

NVIDIA CUDA ProgrammingGuide

|Views: 376|Likes:
Published by gavzan
CUDA programming
CUDA programming

More info:

Published by: gavzan on Sep 23, 2012
Copyright:Attribution Non-commercial

Availability:

Read on Scribd mobile: iPhone, iPad and Android.
download as PDF, TXT or read online from Scribd
See more
See less

11/22/2012

pdf

text

original

The execution context (program counters, registers, etc) for each warp processed by
a multiprocessor is maintained on-chip during the entire lifetime of the warp.
Switching from one execution context to another therefore has no cost, and at every
instruction issue time, the warp scheduler selects a warp that has threads ready to
execute (active threads) and issues the next instruction to those threads.
In particular, each multiprocessor has a set of 32-bit registers that are partitioned
among the warps, and a parallel data cache or shared memory that is partitioned among
the thread blocks.
The number of blocks and warps that can reside and be processed together on the
multiprocessor for a given kernel depends on the amount of registers and shared
memory used by the kernel and the amount of registers and shared memory
available on the multiprocessor. There are also a maximum number of resident
blocks and a maximum number of resident warps per multiprocessor. These limits
as well the amount of registers and shared memory available on the multiprocessor

Chapter 4: Hardware Implementation

CUDA Programming Guide Version 3.0

79

are a function of the compute capability of the device and are given in Appendix G.
If there are not enough registers or shared memory available per multiprocessor to
process at least one block, the kernel will fail to launch.
The total number of warps Wblock in a block is as follows:

)

1,

(

size

block

W

T

ceil

W

T is the number of threads per block,
Wsize is the warp size, which is equal to 32,
ceil(x, y) is equal to x rounded up to the nearest multiple of y.
The total number of registers Rblock allocated for a block is as follows:
For devices of compute capability 1.x:

)

,

)

,

(

(

T

k

size

W

block

block

G

R

W

G

W

ceil

ceil

R

For devices of compute capability 2.0:

block

T

size

k

block

W

G

W

R

ceil

R

)

,

(

GW is the warp allocation granularity, equal to 2 (compute capability 1.x only),
Rk is the number of registers used by the kernel,
GT is the thread allocation granularity, equal to 256 for devices of compute
capability 1.0 and 1.1, and 512 for devices of compute capability 1.2 and 1.3,
and 64 for devices of compute capability 2.0.
The total amount of shared memory Sblock in bytes allocated for a block is as follows:

)

,
( S
k

block

G

S

ceil

S

Sk is the amount of shared memory used by the kernel in bytes,
GS is the shared memory allocation granularity, which is equal to 512 for devices
of compute capability 1.x and 128 for devices of compute capability 2.0.

You're Reading a Free Preview

Download
scribd
/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->