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ICM7555

ICM7555

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ICM7555

General purpose CMOS timer
Rev. 02 — 3 August 2009 Product data sheet

1. General description
The ICM7555 is a CMOS timer providing significantly improved performance over the standard NE/SE555 timer, while at the same time being a direct replacement for those devices in most applications. Improved parameters include low supply current, wide operating supply voltage range, low THRESHOLD, TRIGGER, and RESET currents, no crowbarring of the supply current during output transitions, higher frequency performance and no requirement to decouple CONTROL_VOLTAGE for stable operation. The ICM7555 is a stable controller capable of producing accurate time delays or frequencies. In the one-shot mode, the pulse width of each circuit is precisely controlled by one external resistor and capacitor. For astable operation as an oscillator, the free-running frequency and the duty cycle are both accurately controlled by two external resistors and one capacitor. Unlike the NE/SE555 device, the CONTROL_VOLTAGE terminal need not be decoupled with a capacitor. The TRIGGER and RESET inputs are active LOW. The output inverter can source or sink currents large enough to drive TTL loads or provide minimal offsets to drive CMOS loads.

2. Features
I I I I I I I I I I I I I Exact equivalent in most applications for NE/SE555 Low supply current: 80 µA (typical) Extremely low trigger, threshold, and reset currents: 20 pA (typical) High-speed operation: 500 kHz guaranteed Wide operating supply voltage range guaranteed 3 V to 16 V over full automotive temperatures Normal reset function; no crowbarring of supply during output transition Can be used with higher-impedance timing elements than the NE/SE555 for longer time constants Timing from microseconds through hours Operates in both astable and monostable modes Adjustable duty cycle High output source/sink driver can drive TTL/CMOS Typical temperature stability of 0.005 % / °C at 25 °C Rail-to-rail outputs

NXP Semiconductors

ICM7555
General purpose CMOS timer

3. Applications
I I I I I I I Precision timing Pulse generation Sequential timing Time delay generation Pulse width modulation Pulse position modulation Missing pulse detector

4. Ordering information
Table 1. Ordering information Temperature range Tamb = 0 °C to +70 °C Tamb = −40 °C to +85 °C Tamb = 0 °C to +70 °C Tamb = −40 °C to +85 °C DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1 Package Name ICM7555CD ICM7555ID ICM7555CN ICM7555IN SO8 Description plastic small outline package; 8 leads; body width 3.9 mm Version SOT96-1 Type number

5. Functional diagram
flip-flop VDD 8 R comparator A 6 THRESHOLD 5 CONTROL_VOLTAGE R comparator B TRIGGER 2 R 1 GND DISCHARGE 7 N 1 GND RESET 4

output drivers 3 OUTPUT

002aae403

Remark: Unused inputs should be connected to appropriate voltage from Table 3.

Fig 1.

Functional diagram

ICM7555_2

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 02 — 3 August 2009

2 of 22

V. Pin configuration for SO8 Fig 3. Pinning information 6.NXP Semiconductors ICM7555 General purpose CMOS timer 6. All rights reserved.1 Function selection Table 3. (active LOW) timer logic level output timer inhibit input. 7. Pin configuration for DIP8 6. 2009. Symbol GND TRIGGER OUTPUT RESET CONTROL_VOLTAGE THRESHOLD DISCHARGE VDD Pin description Pin 1 2 3 4 5 6 7 8 Description supply ground start timer input.1 Pinning GND TRIGGER OUTPUT RESET 1 2 3 4 002aae400 8 VDD DISCHARGE THRESHOLD CONTROL_VOLTAGE GND TRIGGER OUTPUT RESET 1 8 VDD DISCHARGE THRESHOLD CONTROL_VOLTAGE ICM7555CD 7 ICM7555ID 6 5 2 ICM7555CN 7 3 4 002aae401 ICM7555IN 6 5 Fig 2. ICM7555_2 © NXP B. 02 — 3 August 2009 3 of 22 .2 Pin description Table 2. TRIGGER will dominate over THRESHOLD. (active LOW) timing capacitor upper voltage sense input timing capacitor lower voltage sense input timing capacitor discharge output supply voltage 7. Product data sheet Rev. don’t care > 2⁄3 V+ Vth < 2⁄3 V+ don’t care [1] Function selection TRIGGER voltage don’t care > 1⁄3 V+ Vtrig > 1⁄3 V+ < 1⁄ 3 THRESHOLD voltage RESET[1] L H H H OUTPUT L L stable H Discharge switch on on stable off V+ RESET will dominate all other inputs. Functional description Refer to Figure 1 “Functional diagram”.

Characteristics Tamb = 25 °C unless otherwise specified.4VDD 1.1 50 75 100 0.65VDD 0.2 “Power supply considerations” section.3 V or less than GND − 0. connecting any terminal to a voltage greater than VDD + 0.67VDD 1. Above 25 °C. In multiple systems. Characteristics Table 5.3 100 1160 780 +150 300 Unit V V V V V mA mW mW °C °C storage temperature solder point temperature soldering 60 s Due to the SCR structure inherent in the CMOS process used to fabricate these devices. [2] [3] 9. All rights reserved.3 VDD + 0. derate at the following rates: DIP8 package at 9.3 VDD + 0.3 −0. Symbol VDD VI Parameter supply voltage input voltage TRIGGER CONTROL_VOLTAGE THRESHOLD RESET IO P output current power dissipation Tamb = 25 °C (still air) DIP8 package SO8 package Tstg Tsp [1] [2][3] [1] Conditions Min −0. 2009.63VDD 0.3 VDD + 0.V. For this reason it is recommended that no inputs from external sources not operating from the same power supply be applied to the device before its power supply is established.62VDD 0.7VDD 5.3 −0. Limiting values Table 4. Product data sheet Rev. the supply of the ICM7555 must be turned on first.0 3.3 −0.0 0.3 −65 - Max 18 VDD + 0. 02 — 3 August 2009 4 of 22 .2 mW / °C Refer to Section 11. Sym bol VDD IDD Parameter supply voltage supply current[1] Conditions Tmin ≤ Tamb ≤ Tmax VDD = Vmin VDD = Vmax Astable mode timing[2][3] ∆f/f frequency stability VDD = 5 V VDD = 10 V VDD = 15 V VI input voltage TRIGGER: VDD = 5 V CONTROL_VOLTAGE: VDD = 5 V THRESHOLD: VDD = 5 V RESET: VDD = Vmin and Vmax 0.3 V may cause destructive latch-up.67VDD 0.NXP Semiconductors ICM7555 General purpose CMOS timer 8.0 0.3 mW / °C SO8 package at 6.65VDD 0.29VDD 0.34VDD 0. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).0VDD % %/V ppm/°C ppm/°C ppm/°C V V V V ∆f/∆V frequency variation with voltage ∆f/∆T frequency variation with temperature[4] Min 3 Typ 50 180 Max 16 200 300 Unit V µA µA ICM7555_2 © NXP B.31VDD 0.

ICM7555_2 © NXP B. CL = 10 pF. VDD = 5 V astable mode - The supply current value is essentially independent of the TRIGGER. Product data sheet Rev. IDIS = 10 mA RL = 10 MΩ.7 4.1 0. [3] [4] RA.0 mA VDD = Vmax VDD = 5 Vmax Vo tr(o) tf(o) fosc [1] [2] Min Typ Max Unit 15.4 0.NXP Semiconductors ICM7555 General purpose CMOS timer Table 5.4 0.V. Astable timing is calculated using the following equation: 1.2 mA VDD = 5 V.2 45 20 - 0.0 - 50 10 1 50 10 1 100 20 2 0. Isink = 3.38 f = -------------------------------( R A + 2R B )C The components are defined in Figure 15. 5 V < VDD < 15 V Parameter is not 100 % tested. All rights reserved. RB = 1 kΩ to 100 kΩ.2 mA Isource = −1. Sym bol II Parameter input current Conditions TRIGGER VDD = Vtrig = Vmax VDD = Vtrig = 5 V VDD = Vtrig = Vmin THRESHOLD VDD = Vth = Vmax VDD = Vth = 5 V VDD = Vth = Vmin RESET VDD = Vrst = Vmax VDD = Vrst = 5 V VDD = Vrst = Vmin VOL VOH LOW-level output voltage HIGH-level output voltage VDD = Vmax. THRESHOLD and RESET voltages. C = 0. 02 — 3 August 2009 5 of 22 .5 0.2 15.25 4.1 µF. Isink = 3. Characteristics …continued Tamb = 25 °C unless otherwise specified. 2009.4 75 75 500 pA pA pA pA pA pA pA pA pA V V V V V ns ns kHz output voltage output rise time[4] output fall time[4] oscillator frequency DISCHARGE: VDD = 5 V.

High output voltage drop versus output source current 102 IDIS (mA) 10 002aae406 1 VDD = 18 V 5V 2V 10−1 10−1 1 VDIS (V) 10 Tamb = +25 °C. Fig 6. Fig 5. Supply current versus supply voltage 102 002aae405 Io(source) (mA) 10 VDD = 18 V 5V 2V 1 10−1 10−1 1 10 VDD − VO (V) 102 Tamb = +25 °C.V. 02 — 3 August 2009 6 of 22 . All rights reserved. Discharge low output voltage versus discharge sink current ICM7555_2 © NXP B. Typical performance curves 002aae404 250 IDD (µA) 200 150 Tamb = −55 °C +25 °C +125 °C 100 50 0 0 5 10 15 VDD (V) 20 Fig 4.NXP Semiconductors ICM7555 General purpose CMOS timer 10. 2009. Product data sheet Rev.

02 — 3 August 2009 7 of 22 . Tamb = +125 °C. Product data sheet Rev. Low output voltage versus output sink current ICM7555_2 © NXP B. Tamb = −55 °C. 2009. Fig 7.NXP Semiconductors ICM7555 General purpose CMOS timer 102 Io(sink) (mA) 10 VDD = 18 V 5V 2V 002aae407 1 10−1 10−1 1 VOL (V) 10 a. Tamb = +25 °C. 102 Io(sink) (mA) 10 VDD = 18 V 5V 2V 002aae408 1 10−1 10−1 1 VOL (V) 10 b. All rights reserved. 102 Io(sink) (mA) 10 VDD = 18 V 5V 2V 002aae409 1 10−1 10−1 1 VOL (V) 10 c.V.

Propagation delay versus voltage level of TRIGGER pulse (VDD = 5 V) ICM7555_2 © NXP B.NXP Semiconductors ICM7555 General purpose CMOS timer 500 TRIGGER pulse width (ns) 400 VDD = 18 V 5V 2V 002aae410 300 200 100 0 0 10 20 30 40 lowest voltage level of TRIGGER pulse (% VDD) Fig 8. 02 — 3 August 2009 8 of 22 . All rights reserved. Product data sheet Rev. Minimum pulse width for triggering 1000 002aae411 tPD (ns) 750 Tamb = −55 °C +25 °C +125 °C 500 250 0 0 10 20 30 40 lowest voltage level of TRIGGER pulse (% VDD) Fig 9. 2009.V.

Normalized frequency stability as a function of temperature (astable mode) ICM7555_2 © NXP B. 2009. Product data sheet Rev. Normalized frequency stability as a function of supply voltage (astable mode) 4 normalized frequency (%) 2 VDD = 18 V 5V 2V 002aae414 0 −2 −4 −75 −25 25 75 Tamb (°C) 125 RA = RB = 1 kΩ C = 0. All rights reserved.1 µF Fig 10.NXP Semiconductors ICM7555 General purpose CMOS timer 6 normalized frequency (%) 4 002aae413 2 0 −2 −4 0 5 10 15 VDD (V) 20 Tamb = +25 °C RA = RB = 10 kΩ C = 0. 02 — 3 August 2009 9 of 22 .1 µF Fig 11.V.

V. 02 — 3 August 2009 10 of 22 . Monostable time delay versus RA resistance and external capacitance ICM7555_2 © NXP B. Tamb = +25 °C Fig 13. Tamb = +25 °C Fig 12. 2009. Product data sheet Rev. Free-running frequency as a function of RA.NXP Semiconductors ICM7555 General purpose CMOS timer 102 C (µF) 10 1 10−1 10−2 10−3 10−4 10−5 10−1 1 kΩ 10 kΩ 100 kΩ 1 MΩ 10 MΩ 002aae415 1 10 102 103 104 105 106 f (Hz) 107 VDD = 5 V. RB resistance and external capacitance 102 C (µF) 10 1 10−1 10−2 10−3 10−4 10−5 10−7 1 kΩ 10 kΩ 100 kΩ 1 MΩ 10 MΩ 002aae416 10−6 10−5 10−4 10−3 10−2 10−1 1 td (s) 10 VDD = 5 V. All rights reserved.

3 Output drive capability The output driver consists of a CMOS inverter capable of driving most logic families including CMOS and TTL. in most instances. 11.V. the CONTROL_VOLTAGE decoupling capacitors are not required since the input impedance of the CMOS comparators on chip are very high. Secondly. in most instances.1 General The ICM7555 device is. it is possible to effect economies in the external component count using the ICM7555. the total system supply can be high unless the timing components are high-impedance. if driving CMOS. Thus.2 Power supply considerations Although the supply current consumed by the ICM7555 device is very low. 2 capacitors can be saved using an ICM7555. Supply current transient compared with a standard NE/SE555 device during an output transition 11. high values for R and low values for C in Figure 15 and Figure 16 are recommended. As such. 500 IDD (mA) 300 002aae417 (1) 100 (2) −100 0 200 400 600 time (ns) 800 Tamb = +25 °C (1) NE/SE555 (2) ICM7555 Fig 14. 2009. Therefore. the ICM7555 will drive at least 2 standard TTL loads. the output swing at all supply voltages will equal the supply voltage. Product data sheet Rev. ICM7555_2 © NXP B. 02 — 3 August 2009 11 of 22 . a direct replacement for the NE/SE555 device. See Figure 14. Because the NE/SE555 device produces large crowbar currents in the output driver. At a supply voltage of 4. The ICM7555 produces supply current spikes of only 2 mA to 3 mA instead of 300 mA to 400 mA and supply decoupling is normally not necessary. for many applications.5 V or more. All rights reserved. Application information 11. The ICM7555 device produces no such transients.NXP Semiconductors ICM7555 General purpose CMOS timer 11. However. it is necessary to decouple the power supply lines with a good capacitor close to the device.

the external capacitor charges and drives the OUTPUT HIGH.4 Astable operation If the circuit is connected as shown in Figure 15.38 f = ------------------------------------( R A + 2R B ) × C R A + RB δ = ---------------------R A + 2R B (1) (2) VDD 1 2 3 GND TRIGGER OUTPUT RESET VDD DISCHARGE THRESHOLD CONTROL_VOLTAGE 8 7 6 5 VDD RA OUTPUT RB VDD 4 C 002aae418 Fig 15. The voltage across the capacitor increases exponentially with a time constant t = RAC. Astable operation 11. 1. The external capacitor charges through RA and RB and discharges through RB only. Initially. Since the charge rate and the threshold levels are directly proportional to the 3 DD supply voltage. 2009. When the voltage across the capacitor equals 2⁄3 V+.5 Monostable operation In this mode of operation. Product data sheet Rev. the duty cycle (δ) may be precisely set by the ratio of these two resistors. the external capacitor (C) is held discharged by a transistor inside the timer. 02 — 3 August 2009 12 of 22 . which releases the low-impedance on DISCHARGE. the internal flip-flop is set. the capacitor charges and discharges between 1⁄3 VDD and 2⁄ V . the frequency of oscillation is independent of the supply voltage. which in turn discharges the capacitor rapidly and also drives the OUTPUT to its LOW state.V. the comparator resets the flip-flop. the timer functions as a one-shot. ICM7555_2 © NXP B. Thus. All rights reserved. TRIGGER must return to a HIGH state before the OUTPUT can return to a LOW state.NXP Semiconductors ICM7555 General purpose CMOS timer 11. it will trigger itself and free run as a multivibrator. TRIGGER. In this mode of operation. Upon application of a negative pulse to pin 2.

Product data sheet Rev.V. which in turn controls simultaneously the state of the OUTPUT and DISCHARGE pins.e. 2009. i. This avoids the multiple threshold problems sometimes encountered with slow falling edges in the NE/SE555 devices. At all supply voltages it represents an extremely high input impedance.6 V to 0. ICM7555_2 © NXP B.7 V.NXP Semiconductors ICM7555 General purpose CMOS timer VDD 1 2 3 4 8 7 6 5 optional capacitor C RA GND TRIGGER OUTPUT RESET VDD DISCHARGE THRESHOLD CONTROL_VOLTAGE 002aae419 VDD ≤ 18 V. 02 — 3 August 2009 13 of 22 . In the monostable mode.05 RAC Fig 16. The mode of operation of the RESET function is. however. This provides the possibility of oscillation frequency modulation in the astable mode. t = 1. 0. delay times can be changed by varying the applied voltage to the CONTROL_VOLTAGE pin. Monostable operation 11.. All rights reserved. 11. depending on the applied voltage. much improved over the standard NE/SE555 device in that it controls only the internal flip-flop.7 RESET The RESET terminal is designed to have essentially the same trip voltage as the standard NE/SE555 device.6 Control voltage The CONTROL_VOLTAGE terminal permits the two trip voltages for the THRESHOLD and TRIGGER internal comparators to be controlled. or even inhibition of oscillation.

25 mm (0.039 0.7 0.05 Lp 1. Package outline SOT96-1 (SO8) ICM7555_2 © NXP B.25 0. Product data sheet Rev.49 0.45 1. 8 leads.1 0.20 0.8 0.25 A3 0.028 0.0 3.0100 0.05 HE 6.006 inch) maximum per side are not included.4 Q 0.19 D (1) 5. Package outline SO8: plastic small outline package. All rights reserved. body width 3.27 0.9 mm SOT96-1 D E A X c y HE v M A Z 8 5 Q A2 A1 pin 1 index θ Lp 1 e bp 4 w M L detail X (A 3) A 0 2.36 c 0.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Notes 1.0075 0.012 θ 0.244 0.004 Z (1) 0. 2009.014 0.010 0. Plastic or metal protrusions of 0.25 0.8 L 1.NXP Semiconductors ICM7555 General purpose CMOS timer 12.01 y 0.069 A1 0.024 8o o 0 ISSUE DATE 99-12-27 03-02-18 Fig 17.25 0.10 A2 1.2 5.75 0.0 0.01 inch) maximum per side are not included.019 0.15 mm (0.057 0.049 0.7 0.028 0.041 0.3 0. 2.25 0.004 0.01 w 0.016 0. 02 — 3 August 2009 14 of 22 .8 0.25 0.V. Plastic or metal protrusions of 0.0 4. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max.15 e 1.01 bp 0.19 E (2) 4. 1.228 0.6 v 0.16 0.

NXP Semiconductors ICM7555 General purpose CMOS timer DIP8: plastic dual in-line package.02 A2 max.1 e1 7.80 0. 1.39 0.2 0.14 0.39 0.15 0.035 c 0.36 0.54 0.01 Z (1) max.24 e 2.015 b2 1.12 ME 8. 8 leads (300 mil) SOT97-1 D seating plane ME A2 A L A1 c Z e b1 w M (e 1) b2 5 MH b 8 pin 1 index E 1 4 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max.60 3. 2009. Product data sheet Rev.01 inch) maximum per side are not included.25 7.021 0. 0.31 MH 10.3 L 3.36 E (1) 6.V.62 0.8 9.73 1.38 0.20 0.32 0.48 6.009 D (1) 9.23 0.045 b1 0. 4.3 0.14 0.89 0. Plastic or metal protrusions of 0.045 Note 1.07 0.042 0.25 mm (0.254 0.05 0.13 b 1. Package outline SOT97-1 (DIP8) ICM7555_2 © NXP B.0 8.2 0.33 w 0.068 0.17 A1 min.51 0.26 0. 3. OUTLINE VERSION SOT97-1 REFERENCES IEC 050G01 JEDEC MO-001 JEITA SC-504-8 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Fig 18.53 0.2 0.014 0. All rights reserved. 02 — 3 August 2009 15 of 22 .

There is no single soldering method that is ideal for all IC packages. including temperature and impurities ICM7555_2 © NXP B. solder masks and vias Package footprints.6 mm cannot be wave soldered. 13. The soldered joint provides both the mechanical and the electrical connection. and leadless packages are all reflow solderable.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. clinching of leads. Leaded packages. The reflow soldering process involves applying solder paste to a board. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs. including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 13. however.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs). due to an increased probability of bridging. Soldering of SMD packages This text provides a very brief insight into a complex technology. 02 — 3 August 2009 16 of 22 . packages with solder balls.3 Wave soldering Key characteristics in wave soldering are: • Process issues. it is not suitable for fine pitch SMDs. including the board finish. All rights reserved. Product data sheet Rev. 13. cannot be wave soldered. which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. followed by component placement and exposure to a temperature profile. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. board transport. and the time during which components are exposed to the wave • Solder bath specifications. such as application of adhesive and flux. the solder wave parameters. leaded SMDs with leads having a pitch smaller than ~0.V. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board. Packages with solder balls. 2009. Also. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications.NXP Semiconductors ICM7555 General purpose CMOS timer 13. to form electrical circuits. and some leadless packages which have solder lands underneath the body.

6 1. 02 — 3 August 2009 17 of 22 . and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile.V.NXP Semiconductors ICM7555 General purpose CMOS timer 13.5 > 2. 2009. release.5 ≥ 2. as indicated on the packing. All rights reserved. Studies have shown that small packages reach higher temperatures during reflow soldering. the peak temperature must be low enough that the packages and/or boards are not damaged. thus reducing the process window • Solder paste printing issues including smearing. reflow (in which the board is heated to the peak temperature) and cooling down. see Figure 19. this profile includes preheat. note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 19) than a SnPb process. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 6 and 7 Table 6.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 ≥ 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions. ICM7555_2 © NXP B.5 Table 7. SnPb eutectic process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 2. must be respected at all times. In addition.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 1. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). Product data sheet Rev.6 to 2.

dip and manual soldering. refer to Application Note AN10365 “Surface mount reflow soldering description”. damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 19. The total contact time of successive solder waves must not exceed 5 seconds.NXP Semiconductors ICM7555 General purpose CMOS timer temperature maximum peak temperature = MSL limit. either below the seating plane or not more than 2 mm above it.3 Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package. depending on solder material applied. forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 2009.1 Introduction to soldering through-hole mount packages This text gives a very brief insight into wave. contact may be up to 5 seconds. Product data sheet Rev. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. SnPb or Pb-free respectively. Temperature profiles for large and small components For further information on temperature profiles. The device may be mounted up to the seating plane. 14. 14.V. All rights reserved. If the bit temperature is between 300 °C and 400 °C. Soldering of through-hole mount packages 14.2 Soldering by dipping or by solder wave Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. ICM7555_2 © NXP B. but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). 14. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C or 265 °C. If the printed-circuit board has been pre-heated. 02 — 3 August 2009 18 of 22 .

02 — 3 August 2009 19 of 22 .NXP Semiconductors ICM7555 General purpose CMOS timer 14. All rights reserved.V. DIP. HCPGA DBS. For PMFP packages hot bar soldering or manual soldering is suitable. the longitudinal axis must be parallel to the transport direction of the printed-circuit board. HDIP. Package CPGA.4 Package related soldering information Table 8. SDIP. Product data sheet Rev. 15. SIL PMFP[2] [1] [2] Suitability of through-hole mount IC packages for dipping and wave soldering Soldering method Dipping suitable Wave suitable suitable[1] not suitable For SDIP packages. Acronym CMOS TTL SCR Abbreviations Description Complementary Metal-Oxide Semiconductors Transistor-Transistor Logic Silicon-Controlled Rectifier ICM7555_2 © NXP B. Abbreviations Table 9. RDBS. 2009.

∆f/∆T. VTH. VCV. – Symbol/parameter “TSTG. Added Section 15 “Abbreviations”. – Symbol/parameter “VDIS. – Symbol/parameter “tF. VTH. output fall time”. Product data sheet Rev. 02 — 3 August 2009 20 of 22 . storage temperature”. oscillator frequency”. – Symbol/parameter “PDMAX. maximum power dissipation” replaced with “P. fall time of output” changed to “tf(o). Table 4 “Limiting values”: – Symbols VTRIG. discharge output voltage” changed to “Vo. – Symbols ITRIG. storage temperature range” replaced with “Tstg. – Symbols VTRIG. – Symbol changed from “TSOLD” to “Tsp. power dissipation” (only maximum values given). output voltage” (specific pin name is now noted under Conditions column). Added Table 2 “Pin description”.V. • • • • ICM7555_1 Section 11. respectively). have been added for Astable mode timing. VRST are replaced with VI (specific pin names are now noted under Conditions column). output rise time”. rise time of output” changed to “tr(o). – Symbol/parameter “tR. – Symbol “FMAX” changed to “fosc. VCV. Revision history Release date 20090803 Data sheet status Product data sheet Change notice Supersedes ICM7555_1 Document ID ICM7555_2 Modifications: • • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Revision history Table 10. Legal texts have been adapted to the new company name where appropriate. VRST are replaced with VI (specific pin names are now noted under Conditions column). Added soldering information.4 “Astable operation”: changed symbol for duty cycle from “D” to “δ”. Provided separate pinning diagrams for SO8 and DIP8 packages (Figure 2 and Figure 3. All rights reserved. ITH. IRST are replaced with II (specific pin names are now noted under Conditions column). Added Section 12 “Package outline”. Product specification ECN 853-1192 13721 dated 1994 Aug 31 - 19940831 ICM7555_2 © NXP B. 2009. ∆f/∆V.NXP Semiconductors ICM7555 General purpose CMOS timer 16. solder point temperature” • Table 5 “Characteristics”: – Symbols ∆f/f.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development.com ICM7555_2 © NXP B. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document. which is available on request via the local NXP Semiconductors sales office. This document contains data from the preliminary specification.nxp. 17.V. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. All rights reserved. the latter will prevail.nxp. Exposure to limiting values for extended periods may affect device reliability. In case of any inconsistency or conflict with the short data sheet. This document supersedes and replaces all information supplied prior to the publication hereof. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant. conveyance or implication of any license under any copyrights. nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury. 2009. please send an email to: salesaddresses@nxp. Legal information 17. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.com. which may result in modifications or additions. Product data sheet Rev. space or life support equipment. service names and trademarks are the property of their respective owners.NXP Semiconductors ICM7555 General purpose CMOS timer 17. Suitability for use — NXP Semiconductors products are not designed. intellectual property rights infringement and limitation of liability. as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.4 Trademarks Notice: All referenced brands. patents or other industrial or intellectual property rights. Export might require a prior authorization from national authorities. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. product names. NXP Semiconductors does not give any representations or warranties. The content is still under internal review and subject to formal approval. 02 — 3 August 2009 21 of 22 . military. In case of any inconsistency or conflict between information in this document and such terms and conditions. Please consult the most recently issued document before initiating or completing a design. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. 18. the full data sheet shall prevail.com/profile/terms. expressed or implied. The latest product status information is available on the Internet at URL http://www. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. please visit: http://www. authorized or warranted to be suitable for use in medical. as published at http://www. This document contains the product specification. However. damage.2 Definitions Draft — The document is a draft version only. For detailed and full information see the relevant full data sheet. Export control — This document as well as the item(s) described herein may be subject to export control regulations.com For sales office addresses. Applications — Applications that are described herein for any of these products are for illustrative purposes only. at any time and without notice. unless explicitly otherwise agreed to in writing by NXP Semiconductors. aircraft.nxp. Contact information For more information. including those pertaining to warranty. including without limitation specifications and product descriptions. The term ‘short data sheet’ is explained in section “Definitions”. 17. death or severe property or environmental 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable.

. . . . . . . . . . 18 Package related soldering information . . . . . . . . . 16 Introduction to soldering . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . 4 Typical performance curves . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . .com Date of release: 3 August 2009 Document identifier: ICM7555_2 . . . . . . . 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 6. . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 RESET . . . . . . . . .nxp. . . . 22 Please be aware that important notices concerning this document and the product(s) described herein. . . . . . . . . . 12 Control voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 11. . . . . . . . . . .3 11. . . . 18 Soldering by dipping or by solder wave . . . . .4 11. . . . . . . . . . . . . . . . . 1 Features . . . . . 17 Soldering of through-hole mount packages . 18 Introduction to soldering through-hole mount packages . . . have been included in section ‘Legal information’. . .4 14 14. . . .2 11. . 1 Applications . . . . . . 16 Reflow soldering . . . . . . . 16 Wave soldering . . . 4 Characteristics . . . . . . . . . . For more information. . . . . . . . . 11 Output drive capability . . . . . . . . . . . . . . . . 2 Pinning information . . . . . please send an email to: salesaddresses@nxp. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Soldering of SMD packages . . . . . . 11 Power supply considerations . . . . . . . . . . . . . . . 2 Ordering information . . . .4 15 16 17 17. . . . . © NXP B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 13. . . . . . . . . . . .V. . . . . . . . . . 3 Limiting values. . . . Contents 1 2 3 4 5 6 6. . . . . . . . . . . . . . . . . . . . . . .2 13. . . . . . . . . . . . . . . . . . . .1 14. . . . . . 11 General . . . . . . . . . . . . . . . 21 Trademarks .2 7 7. . . . . . . . . . 11 Astable operation . . . 21 Disclaimers . 16 Wave and reflow soldering . . . . . . 21 Data sheet status . .com For sales office addresses. . . . . . .1 17.2 14. . . . . . . 19 Revision history . . .NXP Semiconductors ICM7555 General purpose CMOS timer 19. . . . . . . . . . . . .5 11. . . . . . . . . . . . . . . 2009.3 17. . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . 19 Abbreviations . . . . . . . . . 6 Application information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 17. . . . . . . . . . . . . . .7 12 13 13. . 12 Monostable operation . . . . . 20 Legal information. . . . . . . . please visit: http://www. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Function selection. . . . . . . . . . . . . .1 8 9 10 11 11. . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . All rights reserved. . .3 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information. . . . . . . . . . . . . . . 21 Definitions . . . . . . . . . . . . . . . . . . . . . . .1 11. . . . . . . . . . 18 Manual soldering . . . . . . . . . . . . . . . . . . . . . .3 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 18 19 General description . . . . .

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