P. 1
Phase detectors

Phase detectors

|Views: 10|Likes:
Published by Kuldeep Gola

More info:

Categories:Types, School Work
Published by: Kuldeep Gola on Oct 01, 2012
Copyright:Attribution Non-commercial

Availability:

Read on Scribd mobile: iPhone, iPad and Android.
download as PPT, PDF, TXT or read online from Scribd
See more
See less

11/30/2012

pdf

text

original

Phase Detector Circuits

Presented by: Ricky Lau

Outline  Why this topic?  Common Phase Detectors (PD) in industry  Novel Phase Detector design  Future design challenges of Phase Detectors .

Why this topic?  Clock and Data Recovery Systems (CDR) are extensively used in telecommunication and digital systems  Phase Detector is critical to the performance of a CDR system .

Linear vs Bang-Bang PD Linear PD Bang-Bang PD Advantages • Small output jitter • Less sensitive to data patterns Disadvantages • Nonlinearity • High output for non-uniform jitter data .

Hogge Phase Detector  Static phase error due to CK->Q delay of FF  Low output jitter and retimes data .

Alexander Phase Detector  High output jitter  Maintain VCO frequency even when no data transition  Retimes Data .

Improved Bang-Bang PD  Large freq steps enhance pull-in range  Small freq steps reduce output jitter  Half-Rate Architecture .

Future Challenges  Jitter performance  Pull-in range  Sensitivity to input data patterns  Reliability  Analog vs Digital PD .

Questions? .

ISCAS. 5. Vol. Raahemifar. M. 94-101. Schweer. M. C. Menoux. “Challenges in the design high-speed clock and data recovery circuits”. Aug. Oberst. Issue 8. pp.36. May 2001 3. “An overview of design techniques for CMOS phase detectors”. IEEE Journal of Solid-State Circuits.26-29. pp. R. . 2001. Vol. 2002. Yuan. pp. Ramezani. Salama. Razavi.T.” IEEE Journal of Solid-State Circuits.40.References 1.715-718. ISCAS. Vol. Soliman.761-768. “A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half Rate Linear Phase Detector. May 2002. Savoj. K. F. "An Improved Bang-Bang Phase Detector for Clock and Data Recovery Applications“. T. Vol. 2. A. B. “Clock/Data Recovery PLL Using Half-Frequency Clock”. Lares. J. IEEE communications Magazine. pp. R. Razavi. 4.1156-1160. S. pp. Rau. 1997. Rothermel.1. N. B.A.5.

You're Reading a Free Preview

Download
scribd
/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->