JK, T, and D Flip-Flops

Dept. of CSIE, Fu Jen Catholic University CAD Laboratory (SF-640) 2010/5

JK Flip-Flop with Synchronous Reset   Input ◦ J. and Reset (Active Low) Output Q and Q J 0 0 J K >clk Q Q’ 2011/5/2  Function Table ◦ positive-edge triggered Reset K 0 1 0 1 Qn Q 0 1 Q’ 2 1 1 . Clock. K.

// behavioral style … always @(posedge Clock) begin // positive-edge triggered if (!Reset) // synchronous reset. endmodule 2011/5/2 3 . else Q <= (J & ~Q)|(~K & Q). active low Q <= 1’b0. // characteristic equation end // always assign Qbar = ~Q.Verilog Code for JK Flip-Flop (Behavioral Modeling)(1/3) module JK-FF-B(…).

else if (J == 1 && K == 0) // Set Q <= 1.Verilog Code for JK Flip-Flop (Behavioral Modeling)(2/3) … always @(posedge Clock) begin // positive-edge triggered if (!Reset) // synchronous reset. else if (J == 0 && K == 0) // No change Q <= Q. … 2011/5/2 4 . active low Q <= 1’b0. else if (J == 0 && K == 1) // Clear Q <= 0. else if (J == 1 && K == 1) // Complement Q <= Qbar. end // always assign Qbar = ~Q.

// No change 2’b01: Q <= 1’b0. // Set 2’b11: Q <= Qbar. K}) 2’b00: Q <= Q. … 2011/5/2 5 . // Complement endcase end // end // always assign Qbar = ~Q.Verilog Code for JK Flip-Flop (Behavioral Modeling)(3/3) … always @(posedge Clock) begin // positive-edge triggered if (!Reset) // synchronous reset. else begin case ({J. // Clear 2’b10: Q <= 1’b1. active low Q <= 1’b0.

Verilog Code for JK Flip-Flop (Dataflow Modeling) module JK-FF-D(…). // characteristic equation of JK FF assign Qbar = ~Q. // dataflow style … wire Qn. // assign the next state end // always assign Qn = J & ~Q | ~K & Q. else Q <= Qn. active low Q <= 1’b0. endmodule 2011/5/2 6 . // the next state Qn always @(posedge Clock) begin if (!Reset) // synchronous reset.

T Flip-Flop with Asynchronous Preset   Input ◦ T. and Preset (Active High) Output Q and Q T 0 1 T >clk Q Q’ 2011/5/2 7  Function Table ◦ negative-edge triggered Preset Qn Q Q’ . Clock.

endmodule 2011/5/2 8 . Q.Verilog Code for T Flip-Flop (Behavioral Modeling)(1/3) module T-FF-B(T. Preset. // behavioral style … always @(negedge Clock or posedge Preset) begin //negative-edge triggered if (Preset) // asynchronous preset. Clock. Qbar). else Q <= ( T & ~Q ) | ( ~T & Q) // characteristic equation // Q <= T ^ Q. end // always assign Qbar = ~Q. active high Q <= 1’b1.

else if ( T == 1) // Complement Q <= Qbar.Verilog Code for T Flip-Flop (Behavioral Modeling)(2/3) … always @(negedge Clock or posedge Preset) begin //negative-edge triggered if (Preset) // asynchronous preset. else if ( T == 0) // No change Q <= Q. active high Q <= 1’b1. … 2011/5/2 9 . end // always assign Qbar = ~Q.

… 2011/5/2 10 . // No change 1’b1: Q <= Qbar.Verilog Code for T Flip-Flop (Behavioral Modeling)(3/3) … always @(negedge Clock or posedge Preset) begin // positive-edge triggered if (Preset) // asynchronous preset. else begin case (T) 1’b0: Q <= Q. active high Q <= 1’b1. // Complement endcase end // else end // always assign Qbar = ~Q.

// characteristic equation of T flip-flop assign Qbar = ~Q. Q. // the next state Qn always @(negedge Clock or posedge Preset) // negative-edge triggered if (Preset) Q <= 1’b1. endmodule // assign the next state // asynchronous preset . Clock. end // always assign Qn = T ∧ Q . else Q <= Qn. … wire Qn. Qbar). Prest.Verilog Code for T Flip-Flop (Dataflow Modeling) module T-FF-D(T. active high // dataflow style 2011/5/2 11 .

Reset and Preset (both Active Low) Output Q and Q Reset Preset D 0 1 D >clk Reset Q Q’ 1 1 X 0 1 1 X X 0 1 Qn Qn’ 0 1 0 1 1 0 1 0  Function Table ◦ positive-edge triggered Preset 2011/5/2 12 .D Flip-Flop with Synchronous Reset and Preset   Input ◦ D. Clock.

Verilog Code for D Flip-Flop (Behavioral Modeling)  Exercised by students 2011/5/2 13 .

Verilog Code for D Flip-Flop (Dataflow Modeling)  Exercised by students 2011/5/2 14 .

 Compare the simulation results for each type of flip-flops modeled by behavioral and dataflow modeling.x. T-FF-B and T-FF-D). 2011/5/2 15 . (See Next Slide)  It should be 0 for all input values of T and Preset.Functional Simulation of Flip-Flops Exercised by students.  ◦ Add a XOR gate which connects the outputs of two flip-flops (e.

Checking the Output Difference of Two Flip-Flops  Logic schematic for checking the equivalence of two T flip-flops. The other types of flip-flops can be checked in the same way. Preset T Q Behavioral >clk Q’ T F Clock Q Dataflow >clk Q’ 2011/5/2 16 T .