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Program1 --- VHDL Architecture shreya_lib.gates2.and1 --- Created: -by - Lab.

UNKNOWN (E3LAB1-08-6843) -at - 09:22:40 07/24/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY gates2 IS port(a,b:in std_logic;c:out std_logic); END ENTITY gates2; -ARCHITECTURE and1 OF gates2 IS BEGIN c<=a and b; END ARCHITECTURE and1;

Or--- VHDL Architecture shreya_lib.gates2or.or1 --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 09:51:42 07/24/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY gates2or IS port(a,b:in std_logic;c:out std_logic); END ENTITY gates2or; -ARCHITECTURE or1 OF gates2or IS BEGIN c<=a or b;

END ARCHITECTURE or1; Xor-

--- VHDL Architecture shreya_lib.gates2xor.xor1 --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 10:07:34 07/24/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY gates2xor IS port(a,b:in std_logic;c:out std_logic); END ENTITY gates2xor; -ARCHITECTURE xor1 OF gates2xor IS BEGIN

c<=a xor b; END ARCHITECTURE xor1; Xnor-

--- VHDL Architecture shreya_lib.gates2xnor.xnor1 --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 10:14:08 07/24/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY gates2xnor IS port(a,b:in std_logic;c:out std_logic); END ENTITY gates2xnor; -ARCHITECTURE xnor1 OF gates2xnor IS BEGIN c<= a xnor b;

END ARCHITECTURE xnor1; 3 inputsAnd-

--- VHDL Architecture shreya_lib.gates3and.and3 --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 10:17:49 07/24/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY gates3and IS port(a,b,c:in std_logic;d:out std_logic); END ENTITY gates3and; -ARCHITECTURE and3 OF gates3and IS BEGIN d<=a and b and c; END ARCHITECTURE and3;

Or-

--- VHDL Architecture shreya_lib.gates3or.or3 --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 10:20:53 07/24/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY gates3or IS port(a,b,c:in std_logic;d:out std_logic); END ENTITY gates3or; -ARCHITECTURE or3 OF gates3or IS BEGIN d<=a or b or c; END ARCHITECTURE or3; Xor-

--- VHDL Architecture shreya_lib.gates3xor.xor3 --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 10:23:19 07/24/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY gates3xor IS port(a,b,c:in std_logic;d:out std_logic); END ENTITY gates3xor; -ARCHITECTURE xor3 OF gates3xor IS BEGIN d<=a xor b xor c; END ARCHITECTURE xor3; Xnor-

--- VHDL Architecture shreya_lib.gates3xnor.xnor3 --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 10:25:33 07/24/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY gates3xnor IS port(a,b,c:in std_logic;d:out std_logic); END ENTITY gates3xnor; -ARCHITECTURE xnor3 OF gates3xnor IS BEGIN d<= not (a xor b xor c); END ARCHITECTURE xnor3; 4 inputsAnd-

--- VHDL Architecture shreya_lib.gates4and.and4 --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 10:28:54 07/24/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY gates4and IS port(a,b,c,d:in std_logic;e:out std_logic); END ENTITY gates4and; -ARCHITECTURE and4 OF gates4and IS BEGIN e<=a and b and c and d; END ARCHITECTURE and4; Or-

--- VHDL Architecture shreya_lib.gates4or.or4 --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 10:32:12 07/24/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY gates4or IS port(a,b,c,d:in std_logic;e:out std_logic); END ENTITY gates4or; -ARCHITECTURE or4 OF gates4or IS BEGIN e<=a or b or c or d; END ARCHITECTURE or4; Xor-

--- VHDL Architecture shreya_lib.gates4xor.xor4 --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 10:36:58 07/24/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY gates4xor IS port(a,b,c,d:in std_logic;e:out std_logic); END ENTITY gates4xor; -ARCHITECTURE xor4 OF gates4xor IS BEGIN e<= a xor b xor c xor d; END ARCHITECTURE xor4; Xnor-

--- VHDL Architecture shreya_lib.gates4xnor.xnor4 --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 10:39:13 07/24/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY gates4xnor IS port(a,b,c,d:in std_logic;e:out std_logic); END ENTITY gates4xnor; -ARCHITECTURE xnor4 OF gates4xnor IS BEGIN e<= not(a xor b xor c xor d); END ARCHITECTURE xnor4; Not-

--- VHDL Architecture shreya_lib.not1.not2 --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 10:47:09 07/24/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY not1 IS port(a:in std_logic;b:out std_logic); END ENTITY not1; -ARCHITECTURE not2 OF not1 IS BEGIN b<=not a; END ARCHITECTURE not2;

Experiment-2 Aoi_struct

--- VHDL Architecture shreya_lib.ent_struct_aoi.aoi_struct --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 10:45:20 07/24/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY ent_struct_aoi IS port(a,b,c,d:in std_logic;e:out std_logic); END ENTITY ent_struct_aoi; -ARCHITECTURE aoi_struct OF ent_struct_aoi IS signal a1,a2,a3:std_logic; component gates2 IS port(a,b:in std_logic;c:out std_logic); END component gates2; component gates2or IS port(a,b:in std_logic;c:out std_logic); END component gates2or; component not1 IS

port(a:in std_logic;b:out std_logic); END component not1; BEGIN x1:gates2 port map(a,b,a1); x2:gates2 port map(c,d,a2); x3:gates2or port map(a1,a2,a3); x4:not1 port map(a3,e); END ARCHITECTURE aoi_struct; Oai struct--- VHDL Architecture shreya_lib.struct_oai.oai --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 11:01:31 07/24/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY struct_oai IS port(a,b,c,d:in std_logic;e:out std_logic); END ENTITY struct_oai; -ARCHITECTURE oai OF struct_oai IS signal a1,a2,a3:std_logic; component not1 IS port(a:in std_logic;b:out std_logic); END component not1; component gates2or IS port(a,b:in std_logic;c:out std_logic); END component gates2or; component gates2 IS port(a,b:in std_logic;c:out std_logic); END component gates2; BEGIN x1:gates2or port map(a,b,a1); x2:gates2or port map(c,d,a2); x3:gates2 port map(a1,a2,a3); x4:not1 port map(a3,e); END ARCHITECTURE oai;

Ioa--- VHDL Architecture shreya_lib.ioa_struct.ioa --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 11:08:22 07/24/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY ioa_struct IS port(a,b,c,d:in std_logic;e:out std_logic); END ENTITY ioa_struct; -ARCHITECTURE ioa OF ioa_struct IS signal a1,a2,a3,a4,a5,a6:std_logic; component not1 IS

port(a:in std_logic;b:out std_logic); END component not1; component gates2or IS port(a,b:in std_logic;c:out std_logic); END component gates2or; component gates2 IS port(a,b:in std_logic;c:out std_logic); END component gates2; BEGIN x1:not1 port map(a,a1); x2:not1 port map(b,a2); x3:not1 port map(c,a3); x4:not1 port map(d,a4); x5:gates2or port map(a1,a2,a5); x6:gates2or port map(a3,a4,a6); x7:gate2 port map(a5,a6,e); END ARCHITECTURE ioa;

DataflowAoi-

--- VHDL Architecture shreya_lib.ent.aoidf --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 09:22:11 07/31/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY ent IS port(a,b,c,d:in std_logic;e:out std_logic);

END ENTITY ent; -ARCHITECTURE aoidf OF ent IS signal a1,a2,a3:std_logic; BEGIN a1<=a and b; a2<=c and d; a3<=a1 or a2; e<=not a3; END ARCHITECTURE aoidf; Oai-

--- VHDL Architecture shreya_lib.ent_oai.oaidf --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 09:31:10 07/31/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;

ENTITY ent_oai IS port(a,b,c,d:in std_logic;e:out std_logic); END ENTITY ent_oai; -ARCHITECTURE oaidf OF ent_oai IS signal a1,a2,a3:std_logic; BEGIN a1<=a or b; a2<=c or d; a3<=a1 and a2; e<=not a3; END ARCHITECTURE oaidf; Ioa--- VHDL Architecture shreya_lib.ioa_df.ioadf --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 09:35:58 07/31/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY ioa_df IS port(a,b,c,d:in std_logic;e:out std_logic); END ENTITY ioa_df; -ARCHITECTURE ioadf OF ioa_df IS signal a1,a2,a3,a4,a5,a6:std_logic; BEGIN a1<=not a; a2<=not b; a3<=not c; a4<=not d; a5<=a1 or a2; a6<=a3 or a4; e<=a5 and a6;

END ARCHITECTURE ioadf;

Lab-3 3 input nand-

--- VHDL Architecture shreya_lib.gates3nand.nand3 --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 09:54:27 07/31/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY gates3nand IS port(a,b,c:in std_logic;d:out std_logic); END ENTITY gates3nand; -ARCHITECTURE nand3 OF gates3nand IS BEGIN d<=(a nand b) nand c; END ARCHITECTURE nand3;

2 i/p nand-

D flipflop-behavioral

--

-- VHDL Architecture shreya_lib.d_behav.d_b --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 10:08:43 07/31/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY d_behav IS port (d,clk: in STD_LOGIC;q,qbar : out STD_LOGIC); end d_behav; architecture d_b of d_behav is begin process(clk) begin if clk'event and clk=1then q <= d; qbar<=not d; end if; end process; end d_b;

d-struct--- VHDL Architecture shreya_lib.d_struct.dstruct --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 10:45:26 07/31/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;

ENTITY d_struct IS port (d,clk: in STD_LOGIC;q,qbar : out STD_LOGIC); END ENTITY d_struct; -ARCHITECTURE dstruct OF d_struct IS signal a1,a2,a3:std_logic; signal q1:std_logic:=0; signal q2:std_logic:=1; component gates2nand port(a,b:in std_logic;c:out std_logic); end component; component not1 port(a:in std_logic;b:out std_logic); end component; BEGIN x1:gates2nand port map(d,clk,a2); x2:not1 port map(d,a1); x3:gates2nand port map(a1,clk,a3); x4:gates2nand port map(a2,q2,q); x5:gates2nand port map(a3,q1,qbar); q<=q1; qbar<=q2; END ARCHITECTURE dstruct; d- dataflow--- VHDL Architecture shreya_lib.d_df.ddf --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 09:28:46 08/ 7/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY d_df IS port(d,clk:in std_logic;q,qbar:inout std_logic); END ENTITY d_df; --

ARCHITECTURE ddf OF d_df IS signal a1,a2,a3:std_logic; BEGIN a2<=d nand clk; a1<=not d; a3<=a1 nand clk; q<=a2 nand qbar; qbar<=a3 nand q; END ARCHITECTURE ddf;

Sr-dataflow--- VHDL Architecture shreya_lib.sr_df.srdf --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 09:35:55 08/ 7/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all; ENTITY sr_df IS port(s,r,clk:in std_logic;q,qbar:out std_logic); END ENTITY sr_df; -ARCHITECTURE srdf OF sr_df IS signal q1:std_logic:='0'; signal q2:std_logic:='1'; BEGIN q1<= s or(q1 and(not r)); q2<=(not s) and(q2 or r); q<=q1; qbar<=q2; END ARCHITECTURE srdf;

Sr struct-

--- VHDL Architecture shreya_lib.sr_struct.srstruct --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 10:18:53 08/ 7/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY sr_struct IS port(s,r,clk:in std_logic;q,qbar:out std_logic); END ENTITY sr_struct; -ARCHITECTURE srstruct OF sr_struct IS component gates2nand port(a,b:in std_logic;c:out std_logic); end component; signal a1,a2:std_logic; signal q1:std_logic:='0'; signal q2:std_logic:='1'; BEGIN

x1:gates2nand port map(s,clk,a1); x2:gates2nand port map(r,clk,a2); x3:gates2nand port map(q2,a1,q1); x4:gates2nand port map(q1,a2,q2); q<=q1; qbar<=q2; END ARCHITECTURE srstruct; Sr-behavioral --- VHDL Architecture shreya_lib.sr_behav.srbehav --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 10:39:43 08/ 7/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY sr_behav IS port(s,r,clk:in std_logic;q,qbar:out std_logic); END ENTITY sr_behav; -ARCHITECTURE srbehav OF sr_behav IS signal x:std_logic:='0'; signal y:std_logic:='1'; BEGIN process(clk) begin if clk'event and clk='1' then if s='0' and r='0' then x<=x; y<=y; elsif s='1' and r='0' then x<='1'; y<='0'; elsif s='0' and r='1' then x<='0'; y<='1'; elsif s='1' and r='1' then x<='Z';

y<='Z'; end if; q<=x; qbar<=y; end if; end process; END ARCHITECTURE srbehav;

Jk dataflow--- VHDL Architecture shreya_lib.jk_df.jkdf --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 11:04:02 08/ 7/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all; ENTITY jk_df IS port(j,k,clk:in std_logic;q,qbar:out std_logic); END ENTITY jk_df; -ARCHITECTURE jkdf OF jk_df IS signal q1:std_logic:='1'; signal q2:std_logic:='0'; BEGIN q1<=(j and q2) or((not k) and q1); q2<=not q1; q<=q1; qbar<=q2; END ARCHITECTURE jkdf;

t-df-\ --- VHDL Architecture shreya_lib.t_df.tdf --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 09:28:06 08/14/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY t_df IS port(t:in std_logic;q,qbar:out std_logic); END ENTITY t_df;

-ARCHITECTURE tdf OF t_df IS signal q1:std_logic:='0'; signal q2:std_logic:='1'; BEGIN q1<=not t; q2<=not q1; q<=q1; qbar<=q2; END ARCHITECTURE tdf;

t-behav--- VHDL Architecture shreya_lib.t_behav.tbehav --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 09:37:58 08/14/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY t_behav IS

port(t,clk:in std_logic;q,qbar:out std_logic); END ENTITY t_behav; -ARCHITECTURE tbehav OF t_behav IS signal q1:std_logic:='1'; signal q2:std_logic:='0'; BEGIN process(clk) begin if clk'event and clk='1' then if t='0' then q1<='1'; q2<='0'; else q1<='0'; q2<='1'; end if; q<=q1; qbar<=q2; end if; end process; END ARCHITECTURE tbehav;

t-struct-

lab-3 bcd-7 segment dataflow-

--- VHDL Architecture shreya_lib.bcdto7.bcdto7_df --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 09:32:16 08/21/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY bcdto7 IS port(a,b,c,d:in std_logic;t,u,v,w,x,y,z:out std_logic); END ENTITY bcdto7; -ARCHITECTURE bcdto7_df OF bcdto7 IS BEGIN t<=a or c or(b xnor d); u<=(not b)or (c xnor d); v<=b or (not c)or d; w<=a or(c and(not d))or (b xor(c or (not d))); x<=(not d)and((not b)or c); y<=a or ((not c)and (not d))or(b and((not c)or(not d))); z<=a or(c and(not d))or(b xor c); END ARCHITECTURE bcdto7_df;

Behavioral--- VHDL Architecture shreya_lib.bcdto7.bcdto7_b --- Created: -by - Lab.UNKNOWN (E3LAB1-08-6843) -at - 09:50:35 08/21/2012 --- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19) -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY bcdto7 IS port(i:in std_logic_vector(3 downto 0);o:out std_logic_vector(6 downto 0)); END ENTITY bcdto7; -ARCHITECTURE bcdto7_b OF bcdto7 IS BEGIN process(i) begin if i= "0000" then o<="1111110"; elsif i="0001" then o<="0110000"; elsif i="0010" then o<="1101101"; elsif i="0011" then o<="1111001"; elsif i="0100" then o<="0110011"; elsif i="0101" then o<="1011011"; elsif i="0110" then o<="1011111"; elsif i="0111" then o<="1110000"; elsif i="1000" then o<="1111111"; else o<="1111011"; end if; end process; END ARCHITECTURE bcdto7_b;

Struct-