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MC LC MC LC 1 Chng 1: I CNG V K THUT GHP NI MY TNH......................

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1.1. Yu cu trao i tin ca my vi tnh i vi mi trng bn ngoi........................................3 1.1.1. Yu cu trao i tin vi ngi iu hnh...........................................................................3 1.1.2. Yu cu trao i tin vi thit b ngoi thng dng.............................................................3 1.1.3. Yu cu trao i tin trong mng my tnh..........................................................................3 1.2. Dng v cc loi tin trao i gia my vi tnh v thit b ngoi (TBN)..................................3 1.2.1. Dng tin (s)........................................................................................................................3 1.2.1. Cc loi tin..........................................................................................................................3 1.3. Vai tr nhim v v chc nng ca khi ghp ni (KGN)......................................................5 1.3.1. Vai tr..................................................................................................................................5 1.3.2. Nhim v.............................................................................................................................5 1.3.3. Chc nng............................................................................................................................6 1.4. Cu trc chung ca mt khi ghp ni.....................................................................................7 1.5. Chng trnh phc v trao i tin cho khi ghp ni..............................................................8

Chng 2: GIAO TIP VI TN HIU TNG T.............................................9


2.1. Khi nim tn hiu analog v h o lng iu khin s.........................................................9 2.2. Chuyn i tn hiu s sang tng t DACs............................................................................9 2.2.1. Cc tham s chnh ca mt DAC.....................................................................................10 2.2.2. DAC chia in tr (Resistive Divider DACs)..................................................................11 2.2.3. DAC iu bin rng xung (PWM DACs)...................................................................11 2.3. Chuyn i tn hiu tng t - s ADCs: ..............................................................................12

Chng 3: TH TC TRAO I TIN CA MY TNH....................................14


3.1. Cc ch trao i tin ca my vi tnh..................................................................................14 3.2. Trao i tin ngt vi x l........................................................................................................16 3.2.1. Cc loi ngt ca my vi tnh PC......................................................................................16 3.2.2. X l ngt cng trong IBM - PC:.....................................................................................18 3.2.3. Lp trnh x l ngt cng: ...............................................................................................21 3.3. Trao i tin trc tip khi nh................................................................................................23 3.3.1. C ch hot ng:.............................................................................................................23 3.3.2. Hot ng ca DMAC:.....................................................................................................23 3.3.3. Chip iu khin truy nhp b nh trc tip DMAC 8237 (Direct Memory Access Controller)...................................................................................................................................24

Chng 4: KHE CM M RNG.........................................................................30


4.1. t vn ................................................................................................................................30 4.2. Bus PC.....................................................................................................................................31 4.3. Bus ISA (16 bit)......................................................................................................................31 4.4. Bus PCI....................................................................................................................................32 4.5. Ghp ni qua khe cm m rng..............................................................................................32 4.5.1. Mt s c im ca Card ISA.........................................................................................32 4.5.2. Gii m a ch v kt ni Bus d liu.............................................................................32

Chng 5: GHP NI TRAO I TIN SONG SONG.........................................34


5.1. Khi ghp ni song song n gin.........................................................................................34 5.2. Cc vi mch m, cht (74LS245, 74LS373)........................................................................35

5.2.1. Vi mch m 74LS245:....................................................................................................35 5.2.2. Vi mch cht 74LS373:....................................................................................................35 5.3. Vi mch PPI 8255A.................................................................................................................36 5.3.1. Gii thiu chung................................................................................................................36 5.3.2. Cc lnh ghi v c cc cng v cc thanh ghi iu khin..............................................37 5.3.3. Cc t iu khin..............................................................................................................37 5.3.4. Ghp ni 8255A vi MVT v TBN..................................................................................41 5.4. Ghp ni song song qua cng my in.....................................................................................44 5.4.1. Gii thiu chung................................................................................................................44 5.4.2. Cu trc cng my in........................................................................................................45 5.4.3. Cc thanh ghi ca cng my in:........................................................................................46 5.4.4. EPP - Enhanced Parallel Port............................................................................................49

Chng 6: GHP NI TRAO I TIN NI TIP...............................................54


6.1. t vn ................................................................................................................................54 6.2. Yu cu v th tc trao i tin ni tip:.................................................................................54 6.2.1. Yu cu: ............................................................................................................................54 6.2.2. Trao i tin ng b: Synchronous..................................................................................55 6.2.3. Trao i tin khng ng b - Asynchronous:...................................................................55 6.3. Truyn thng ni tip s dung giao din RS-232:..................................................................56 6.3.1. Qua trinh truyn mt byte d liu:....................................................................................56 6.3.2. Cng ni tip RS 232........................................................................................................56

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Chng 1: I CNG V K THUT GHP NI MY TNH


1.1. Yu cu trao i tin ca my vi tnh i vi mi trng bn ngoi 1.1.1. Yu cu trao i tin vi ngi iu hnh Ngi iu hnh (ngi s dng) my vi tnh (MVT) cn a lnh (di dng ch) v s liu thng qua bn phm. Khi ngi iu hnh bm vo cc phm ca bn phm nhng m c to ra v c truyn vo b nh ca MVT v ng thi hin th ln mn hnh cc ch v con s bm. 1.1.2. Yu cu trao i tin vi thit b ngoi thng dng Cc thit b a tin vo Cc thit b a tin ra Cc b nh ngoi Yu cu trao i tin vi thit b ngoi khc Trong h o vt l, MVT cn nhn cc tin vt l (nhit , p xut, lc, dng in,...) di dng tn hiu in thng qua du d b pht hin (detector), cm bin (sensor), b chuyn i (tranducer). Hn na MVT cn nhn cc tin v trng thi sn sng hay bn ca cc thit b o. Trong h o - iu khin, MVT cn: Nhn tin v s liu o, v trng thi thit b o chp hnh (Cc ng c servo, cc van ng m, cc thit b ng ngt mch in,...) v cc thng s k thut cho thit b. Trong cc h lu tr v biu din tin, MVT cn a tin ra : Lu tr trn bng t, a t, bng giy v a compac Biu din kt qu o di dng bng s liu, dng th trn giy ca my v hay trn mn hnh ca thit b u cui. 1.1.3. Yu cu trao i tin trong mng my tnh Mt my tnh trong mng cn trao i tin vi nhiu ngi s dng mng, vi nhiu my vi tnh khc, vi nhiu thit b ngoi nh: cc thit b u cui, cc thit b nh ngoi, cc thit b lu tr v biu din tin. 1.2. Dng v cc loi tin trao i gia my vi tnh v thit b ngoi (TBN) 1.2.1. Dng tin (s) MVT ch trao i tin di dng s vi cc mc logic 0 v 1 Thit b ngoi li trao i tin vi nhiu dng khc nhau nh dng s, dng k t, dng tng t, dng m tn hnh sin tun hon 1.2.1. Cc loi tin MVT a ra thit b ngoi mt trong 3 loi tin: Tin v a ch: l cc tin ca a ch TBN hay chnh xc hn, l a ch thanh ghi m ca khi ghp ni i din cho TBN

a tin v s chp nhn trao i tin vi thit b ngoi, v lnh iu khin cc c cu

ng m thit b, c hoc ghi mt thanh ghi, cho php hay tr li yu cu hnh ng,... Tin v s liu: l cc s liu cn a ra cho thit b ngoi My tnh nhn tin vo t TBN v mt trong hai loi tin: Tin v trng thi ca TBN: l tin v s sn sng hay yu cu trao i tin, v trng thi sai li ca TBN Tin v s liu: l cc s liu cn a vo MVT

Tin v lnh iu khin: l cc tn hiu iu khin khi ghp ni hay TBN nh

1.3. Vai tr nhim v v chc nng ca khi ghp ni (KGN) 1.3.1. Vai tr Ngun pht

Ngun nhn

Ngun pht

Ngun nhn

MVT
Ngun nhn Ngun pht Ngun nhn

TBN
Ngun pht

Ghp ni ng Ghp ni ng dy TBN dy MVT V tr v vai tr ca khi ghp ni

Khi ghp ni nm gia MVT v TBN ng vai tr bin i v trung chuyn tin gia chng 1.3.2. Nhim v Phi hp v mc v cng sut tn hiu o Mc tn hiu ca MVT thng l mc TTL (0V 5V) trong khi TBN c nhiu mc khc nhau, thng thng cao hn ( 15V, 48V) o Cng sut ng dy MVT nh, TBN ln o Thng dng cc vi mch 3 trng thi Phi hp v dng tin: Trao i tin ca MVT thng l song song, cua TBN i khi l ni tip Phi hp v tc trao i tin Phi hp v phng thc trao i tin m bo trao i tin mt cch tin cy gia MVT v TBN, cn c KGN v cch trao i tin din ra theo trnh t nht nh. Vic trao i tin do my tnh khi xng

MVT a lnh d khi ng TBN hay khi ng KGN MVT c tr li sn sng trao i hay trng thi sn sng ca TBN. Nu c trng thi sn sng mi trao i tin, nu khng, ch v c li trng thi MVT trao i khi c thy trng thi sn sng Vic trao i tin do TBN khi xng: gim thi gian ch i trng thi sn sng ca TBN, MVT c th khi ng TBN ri thc hin nhim v khc. Vic trao i tin din ra khi: TBN a yu cu trao i tin vo b phn x l ngt ca KGN, a yu cu ngt chng trnh cho MVT Nu c nhiu TBN a yu cu ng thi, KGN sp xp theo u tin nh sn, ri a yu cu trao i tin cho MVT MVT nhn yu cu , sa son trao i v a tn hiu xc nhn sn sng trao i KGN nhn v truyn tn hiu xc nhn cho TBN TBN trao i tin vi KGN v KGN trao i tin vi MVT (nu a tin vo) MVT trao i tin vi TBN qua KGN (nu a tin ra) 1.3.3. Chc nng Chc nng nhn tn hiu (listener) Nhn thng bo a ch t MVT Nhn thng bo trng thi t TBN Nhn lnh iu khin t MVT Nhn s liu t MVT Chc nng ngun tn hiu (talker) Pht a ch cho khi chc nng ca TBn Pht lnh cho TBN Pht yu cu hay trng thi ca TBN cho MVT Pht s liu cho TBN hay cho MVT Chc nng iu khin (Controler) Ni chung KGN thng c ng thi hai chc nng trn, c bit khi ghp ni vi nhiu TBN Cu trc chung ca mt h ghp ni my tnh Cu trc ng dy ca KGN vi MVT Bt c KGN no cng ni vi MVT v TBN theo cc nhm sau Nhm ng dy a ch A0 - An o Cc tn hiu ny c gii m trong cc KGN chn cc TBN cn lin lc vi MVT o Tp hp cc tn hiu ny to thnh bus a ch (address bus) Nhm ng dy lnh o ng dy c, ng dy vit truyn lnh c (RD) hay vit cho KGN. o ng dy hi thoi t chc phi h hnh ng gia MVT v KGN, m bo s hot ng nhp nhng, tin cy gia chng nh:

o Hi - tr li o Yu cu (t KGN vo MVT) v chp nhn (t MVT ra KGN) : yu cu ngt INTR v chp nhn ngt INTA ng dy lnh iu khin KGN hay TBN o Nhm ng dy nhp thi gian o Nhm ng dy in p ngun

1.4. Cu trc chung ca mt khi ghp ni


Lnh
A0 - An n

W R W R
ng dy my tnh (System bus)

Gii m a ch lnh

c Lnh vit

Cc lnh chn chp

Phi hp ng dy thit b ngoi

Phi hp ng dy my tnh

ng dy thit b ngoi

Yu cu (INTR) Xc nhn (INTA) Lnh c

X l ngt

Thanh ghi trng thi Lnh vit


Thanh ghi iu khin

Yu cu A Yu cu B iu khin A iu khin B

cm n ngt

DO0 - DOn

Thanh ghi m vit


Lnh vit

DO0 - DOn

DI0 - DIn Lnh c

Thanh ghi m c

DI0 - DIn

Khi phi hp ng dy MVT o Phi hp mc v cng sut tn hiu vi bus MVT. Thng dng vi mch chuyn mc, vi mch cng sut o C lp ng dy khi khng c trao i tin Khi gii m a ch - lnh: Nhn cc tn hiu t bus a ch, cc tn hiu c, ghi, cht a ch (ALE), t hp thnh cc tn hiu c, ghi v chn chp cho tng thit b ca KGN v TBN. Cc thanh ghi m: o Thanh ghi iu khin ch o Thanh ghi trng thi hay yu cu trao i cuatr TBN

o Thanh ghi m s liu ghi o Thanh ghi m s liu c Khi x l ngt: Ghi nhn, che chn yu cu trao i tin ca TBN. X l u tin v a yu cu vo MVT Khi pht nhp thi gian: Pht nhp thi gian cho hnh ng bn trong KGN hay cho TBN. i khi ng b, khi cn nhn tn hiu nhp ng h (clock) t bus my tnh Khi m thit b ngoi: Bin i mc tn hiu, cng sut v bin i dng tin Khi iu khin : iu khin hot ng ca khi nh pht nhp thi gian, ch hot ng

1.5. Chng trnh phc v trao i tin cho khi ghp ni Mi khi ghp ni cn c mt chng trnh phc v trao i tin (thng thng vit bng Assembly) v khi s dng, ngi dng cn vit chng trnh ng dng. Vi chng trnh phc v trao i tin, cn c cc thao tc sau: Khi ng KGN Ghi che chn v cho php ngt c trng thi TBN Ghi s liu ra c tin s liu n tp : Cu 1 : nh gi kh nng giao tip ca my tnh IBM PC vi mi trng bn ngoi qua cc giao din kt ni c cung cp sn. Cu 2 : M t li cu trc khi ghp ni giao tip cng LPT trong my tnh IBM PC.

Chng 2: GIAO TIP VI TN HIU TNG T


2.1. Khi nim tn hiu analog v h o lng iu khin s

Vic s dng phng php s trong x l thng tin v iu khin ang ngy cng hiu qu v thun li. Tuy nhin hu ht cc tn hiu trong th gii thc li l tn hiu dng tng t (analog). Do bt k h thng no mun x l cc tn hiu thc t bng phng php s th n phi c kh nng chuyn i cc thng tin tng t thnh dng s v ngc li. Thao tc thng c thc hin bng cc thit b ADC (Analog to Digital Converter) v DAC (Digital to Analog Converter). H thng x l tn hiu tng t bng phng php s ni chung l mt h lai, trong s liu tng t s c truyn, lu tr , hay x l bng phng php s nh cc b vi x l s. Trc khi s l, tn hiu tng t phi c chuyn thnh tn hiu s nh b chuyn i tn hiu tng t sang s (ADC). Kt qu ca php x l s c chuyn ngc li thnh dng tng t nh b chuyn i tn hiu s thnh tng t (DAC). 2.2. Chuyn i tn hiu s sang tng t DACs Mt b chuyn i tn hiu s thnh tng t DAC l mt dng c bit ca mt b gii m. N gii m tn hiu s u vo v chuyn thnh tn hiu tng t u ra. Bng chn l:

2.2.1. Cc tham s chnh ca mt DAC n Tham s Gii thch v y l s bit m DAC x l. Nu DAC c n bit th gi tr in phn gii p u ra c th phn thnh n trng thi c gi tr cch u Bit (revolution) nhau. Mi gi tr tng ng vi mt m s u vo. S bit n cng cao th DAC c phn gii cng ln Gii in p tham Ch ra mc in p ln nht v nh nht c th c s dng V chiu (Vref) FSR nh in p tham chiu t bn ngoi L lch gia in p tng t u ra thc t vi u ra l Sai s phn cc im mV tng 0V khi u m b hai vo l 0 c a vo thanh ghi khng u vo L chnh lch gia thay i gi tr ip p ra thc t vi thay i in p ra l tng trong trng hp u vo s phi tuyn vi phn LSB thay i mt bit LSB , hay d thay i gia hai gi tr s k (Non-Linearity, hay Differential - DNL) %Vref nhau VD: +/- 1 LSB; +/- 0.001% FSR phi tuyn tch phn L sai s ln nht gia u ra vi ng thng ni gia im 0 (Non-Linearity, v im ton thang (gi tr ln nht ca thang o) ngoi tr sai Integral - INL) hay LSB s im khng v sai s ton thang chnh xc tng i VD: +/-1 LSB typ.; +/- 4 LSB's max. (Relative Accuracy) Gii u ra tng t L chnh lch gia gi tr tng t ln nht v nh nht m hay gii ton thang DAC c th cung cp V Analog Output Range VD: -3V to +3V, Bipolar Mode or Full-Scale Range Mc in p logic cao L in p nh nht ca tn hiu s u vo DAC m bo u vo - Logic Input c nhn l mc logic 1 V Voltage, Vih (Logic VD: 2.4 V min. "1") L in p ln nht ca tn hiu s u vo DAC m c Logic Input Voltage, nhn l mc logic 0" V Vil (Logic "0") VD: : 0.8 V max L di in p c th dng lm ngun cung cp dng cho in p ngun dng DAC Analog Positive Power V Supply (+Vs) VD: +4.75V min.; +5.0V typ.; +13.2V max. L di in p c th s dng lm ngun cung cp m cho in p ngun m DAC Analog Negative V Power Supply (-Vs) VD: -13.2V min.; -5V typ.; -4.75V max. in p mc logic L di in p c th s dng cho mc logic dng ca DAC: dng - Logic Positive V VD: +4.75V min.; +5.0V typ.; +13.2V max. Power Supply (+VL) in p mc logic m L di in p c th s dng cho mc logic dng ca DAC Logic Negative Power V VD: -13.2V min.; -5V typ.; -4.75V max. Supply (-VL)

2.2.2. DAC chia in tr (Resistive Divider DACs) DAC theo phng php chia in tr c l l kiu DAC n gin nht. DAC kiu ny s dng mt chui in tr mc ni tip vi nhau to ra mt tp cc gi tr in p cch u nhau gia +Vref v Vref. Tn hiu s u vo xc nh tn hiu in p no c ni vi b khuch i thng qua cc cc b chuyn mch. Mc d phng php chia in tr c th d hiu, nhng n tr nn km hiu qu vi cc b DAC c phn gii cao. Mi bit thm vo cho phn gii ca DAC i hi tng gp i s in tr v cng tc. V d nh vi DAC 12 bit th phi cn ti 4095 in tr v 4096 cng tc.

DAC trng s nh phn (Binary Weighted DACs) Khi phn gii ca DAC t ti 6 hay 7 bit, kin trc thang in tr thng cho mt phng php hiu qu hn Phng php ny cho ta li ch chnh l chng tit kim din tch vi mch. Chng hn nh mt DAC 9 bit ch cn 1 in tr v 1 cng tc thm vo so vi DAC 8 bit

2.2.3. DAC iu bin rng xung (PWM DACs) Phng php DAC iu bin rng xung (Pulse width modulation PWM) l phng php rt n gin v hu nh hon ton s dng phng php s, s dng rt t mch tng t PWM iu chnh in p u ra s dng chui xung tn s cao vi rng xung c th thay i c thay i cng sut u ra di xung cng ln th in p u ra cng gn vi in p ti a (VOH) ca DAC, v ngc li di xung ngn nht tng ng vi in p ti thiu (VOL) Tn hiu u ra s c a qua mt b lc thng thp to tn hiu analog.

DAC dng PWM cng kh thu c DAC vi phn gii cao, bi v c phn gii cao, DAC phi iu chnh chui xung theo cc khong thi gian rt nh. iu yu cu phi c mt xung clock (master clock) vi tn s rt cao iu khin rng xung V d vi DAC 16 bit, cn c phn gii theo thi gian bng 1/65536 ln chu k chui xung. V xung tn hiu cn phi a qua b lc thng thp to ra tn hiu tng t, tn s xung i hi phi gp nhiu ln (thng thng l gp 100 ln) tn s cao nht ca tn hiu tng t u ra. Do mt b DAC 16 bit cho cc ng dng x l m thanh c bng thng 20kHz cn c mt b to xung clock c tn s l 65536 x 100 x 20000 = 131 GHz. R rng rng tn s ny l khng th t c vi cng ngh hin nay 2.3. Chuyn i tn hiu tng t - s ADCs: Gii php thng dng a tn hiu tng t vo x l bng cc b x l s l dng b chuyn i tn hiu tng t sang s (analog-to-digital converter - ADC). Hnh di l mt v d cho mt b ADC n gin. u vo cho b ny l hai tn hiu: mt tn hiu tham chiu (reference) v tn hiu cn chuyn i. N c mt u ra biu din mt t m dng s 8 bit. T m ny vi x l c th c v hiu c

Cc tham s chnh ca mt ADC Tham s n v Gii thch Nu mt ADC c n bit, th phn gii ca n l 2n , c ngha phn gii l s trng thi hay s m c th s dng chia u vo Bits Resolution analog. S bit cng cao th phn gii cng ln v cng phn bit c nhiu trng thi

Tham s Sai s tuyn tnh vi phn Non-Linearity, Differential (DNL) Sai s tuyn tnh tch phn Non-Linearity, Integral (INL) Di in p tng t u vo hay di ton thang (Analog Input Range or Full-Scale Range) Thi gian chuyn i (Conversion Time) Ngun nui dng (+ Power Supply - V+) Ngun nui m - Power Supply (V-)

n v Bits (with no missing codes) LSB

Gii thch Vi mi ADC, tn hiu s bin i theo tng bit LSB. chnh lch gia cc gi tr l tng c gi l phi tuyn vi phn. Example of an Actual Spec: 10 Bits min Hm truyn ca mt ADC l mt ng thng ni t im 0 ti im ton thang. Sai s ln nht ca mt m s vi ng thng ny c gi l sai s tch phn ca ADC Example of an Actual Spec: +/- 2 LSB's max L chnh lch gia gi tr tng t ln nht v nh nht ng vi ADC c th VD:0V to +10 V, Unipolar Mode; -5V to +5V, Bipolar Mode Thi gian cn thit ADC hon thnh mt ln chuyn i VD: 15 sec min.; 25 sec typ.; 40 sec max. Di in p c th s dng lm ngun nui dng cho ADC VD: +4.5V min.; +5.0V typ.; +7.0V max. Di in p c th s dng lm ngun nui m cho ADC VD: -12.0V min.; -15V typ.; -16.5V max.

sec V V

n tp : Cu 1 : Phn tc cc thng s ca DAC, xc nh thng s no l thng s quan trng nht. Cu 2 : So snh 2 phng php DAC chia in tr v trng s nh phn. Cu 3 : Phn tc cc thng s ca ADC, xc nh thng s no l thng s quan trng nht.

Chng 3: TH TC TRAO I TIN CA MY TNH


3.1. Cc ch trao i tin ca my vi tnh Ch trao i tin ca MVT vi thit b ngoi Trao i tin theo ch chng trnh S trao i tin c VXL iu khin theo mt trong hai loi lnh sau Cc lnh vo (IN) hay ra (OUT). Cc lnh chuyn(MOV) gia thanh ghi A v thanh ghi m s liu ca KGN c a ch nh xc nh. Chng trnh Trao i tin

Trao i tin trc tip khi nh Sau khi VXL c khi ng, s trao i tin hon ton do KGN iu khin thay cho VXL v cc ca vo ra ca VXL trng thi in tr cao (VXL b c lp). Lc ny, KGN iu khin mi hot ng ca khi nh M v KGN, c th l: Pht a ch cho khi nh hoc TBN. Pht lnh c (RD) hay ghi (WR) s liu. Cc s liu c, ghi c trao i gia khi nh M va TBN thng qua cc thanh ghi m ca KGN. ch trao i tin theo chng trnh, c th trao i tin theo mt trong ba phng php sau: Trao i ng b Trao i khng ng b hay hi trng thi (Polling) Trao i theo ngt chng trnh * Trao i ng b Sau khi khi ng TBN, MVT khng cn quan tm ti TBN c sn sng trao i tin hay khng m a lun cc lnh trao i tin (c vo, ghi ra hay truyn s liu). Phng php trao i tin ny ch c thc hin khi: TBN lun sn sng trao i tin. Tc trao i tin ca MVT v TBN lun ph hp nhau hoc TBN trao i tin nhanh. nh gi: u im: Nhanh, khng tn thi gian ch i Nhc im: Thiu tin cy, b mt tin v c th c s c lm TBN cha sn sng trao i. * Trao i khng ng b hay hi trng thi (Polling)

Trnh t trao i din ra nh sau: MVT a tin iu khin TBN. S

Chng trnh

TBN sn sng ? Trao i tin

MVT ch v kim tra trng thi sn sng trao i tin ca TBN bng cch: o c tin v trng thi sn sng ca TBN. o Kim tra trng thi sn sng. Nu cha, MVT li c v kim tra trng thi sn sng. MVT trao i tin vi TBN. Phng php trao i ny thc hin khi tc trao i tin ca TBN chm so vi MVT nh gi: u im: Tin cy, ch trao i khi bit chc TBN sn sng. Nhc im: Tn thi gian s dng MVT. V d: Gi s c mt thit b o lng c ghp ni vi my tnh. N c nhim v thu nhit t mt im o v chuyn thnh tn hiu s a vo my tnh. Thit b ny c mt thanh ghi trng thi StatusReg 8 bit cho bit trng thi hot ng ca n, khi no d liu sn sng my tnh c th c vo th bit S5 ca thanh ghi ny s c t ln 1. Chng trnh iu khin s c nhim v lin tc c d liu nhit t thit b ny. Ta c on chng trnh nh sau:
Begin While ((StatusReg and 20H) = 20H) do Begin c d liu v thc hin cc tc v lin quan End; End.

3.2. Trao i tin ngt vi x l Chng trnh

Chng trnh con phc v ngt

Ngt

Phng php trao i tin ny khc phc nhc im ca cc phng php trn. Trnh t nh sau: (1) MVT ang thc hin chui lnh ca mt chng trnh no . (2)TBN c yu cu trao i tin, s gi tn hiu yu cu trao i tin (yu cu ngt INTR) (3)MVT (c th l VXL) a tn hiu chp nhn (xc nhn ngt INTA) (4) Chng trnh chnh b ngt, MVT chuyn sang chng trnh con phc v ngt tc l chng trnh con trao i tin cho TBN yu cu. (5) Chng trnh chnh lai tip tc thc hin ch b ngt. 3.2.1. Cc loi ngt ca my vi tnh PC 3.2.1.1. Cc loi ngt Ngi ta chia ngt thnh hai loi: ngt cng v ngt mm Ngt cng: cn gi l ngt ngoi v do nguyn nhn bn ngoi. VXL c cc li vo dnh cho ngt ngoi. Khi c tn hiu vo li vo ny, chng trnh VXL ang thc hin s b dng. Ngt NMI (Non maskable Interrupt) - Ngt khng che c : Khi c ngt ny, VXL dng chng trnh sau lnh ang thc hin, thanh ghi a ch lnh (IP) v thanh ghi ch th flag c lu gi, 2 bit IF (Interrupt Flag) va TF (Trap Flag) b xo v 0 cm ngt ngoi tip theo v khng c by. Mun cho php hay khng cho php ngt ny sy ra, chng ta dng mt triger (flip flop) mc li vo ngt trc khi a vo li vo ngt NMI. Ngt INTR: o Ngt ny c cho php hay cm ngt bng cch lp hay xo bit IF ca thanh ghi flag. Lp bi lnh STI (Set Interrupt), xo bi lnh CLI (Clear Interup) o Thng c ni vi li ra yu cu ngt ca vi mch x l u tin ngt (8214, 8259). Ngt reset Ngt mm: (hay ngt bn trong do lnh ca chng trnh) do VXL gp cc lnh gy ra ngt hoc tnh hung c bit khi thc hin lnh (ngt logic) v ngt ca h iu hnh. Ngt do lnh: l ngt khi thc hin cc lnh CALL, HLT, INT Ngt logic hay cc ngoi tr: xy ra khi gp cc tnh hung c bit sau: o Chia mt s cho 0

o Trn ni dung thanh ghi hay b nh o Thc hin tng bc (vector 1) o im dng (Break point) chng trnh do ngi dung chng trnh s dng nh trc (Vect 3) Ngt ca h iu hnh: l cc ngt do h iu hnh quy nh phc v trao i tin ca cc TBN (bn phm, my in,...) nh INT 10, INT 16, INT 21, .v.v..) Ngt ca MVT PC (8086, 80286) Cc ngt khng hon ton c lin kt vi cc thit b ngoi. H VXL 8086 cung cp 256 ngt, a phn trong s chng l ch phc v nh ngt phn mm. H 8086 c mt bng vecter ngt gi a ch ca cc chng trnh phc v ngt. Mi a ch l 4 byte. Trong cc my PC, ch c 15 ngt dnh cho phn cng v 1 ngt khng che c. Phn cn li c s dng cho cc ngt phn mm v cc b x l ngoi l. B x l ngoi l l cc chng trnh tng t nh ISR nhng x l cc ngt khi xut hin li. V d nh vector ngt u tin gi a ch ca ngoi l Divide by Zero (li chia cho 0). Khi xut hin li ny VXL nhy sang a ch 0000:0000 v thc hin chng trnh c a ch lu y. INT (Hex) 00 - 01 02 03 - 07 08 09 0A 0B 0C 0D 0E 0F 10 - 6F 70 71 72 73 74 75 76 77 78 - FF IRQ Exception Handlers Non-Maskable IRQ Exception Handlers Hardware IRQ0 Hardware IRQ1 Hardware IRQ2 Hardware IRQ3 Hardware IRQ4 Hardware IRQ5 Hardware IRQ6 Hardware IRQ7 Software Interrupts Hardware IRQ8 Hardware IRQ9 Hardware IRQ10 Hardware IRQ11 Hardware IRQ12 Hardware IRQ13 Hardware IRQ14 Hardware IRQ15 Software Interrupts Common Uses Non-Maskable IRQ (Parity Errors) System Timer Keyboard Redirected Serial Comms. COM2/COM4 Serial Comms. COM1/COM3 Reserved/Sound Card Floppy Disk Controller Parallel Comms. Real Time Clock Redirected IRQ2 Reserved Reserved PS/2 Mouse Math's Co-Processor Hard Disk Drive Reserved -

3.2.1.2. Th tc x l (p ng) ngt chng trnh

Khi c mt tin hiu yu cu ngt chng chnh a vo chn yu cu ngt (INTR), qu trnh ngt chng trnh c din ra theo cc bc sau: Lu gi tin v trng thi ca VXL lc c tn hiu yu cu ngt v ni chng trnh b gin on. VXL gi tn hiu xc nhn hay cho php ngt INTA v c vector ngt. Chuyn sang chng trnh phc v ngt. Tr v ch chng trnh chnh b ngt v tip tc thc hin chng trnh . Lu gi tin v ch b ngt chng trnh: cui mi chu trnh lnh, VXL 8086 (cng nh 80286) kim tra xem c yu cu ngt no gi ti khng. Nu c yu cu, VXL tin hnh lu tr tin v ni b ngt chng trnh (dng lnh PUSH vo vng nh ngn xp m a ch ch th bi thanh ghi SP). Cc tin l: Thanh ghi c Flag FR (Flag Register) Con tr lnh IP(Instruction Pointer) Thanh ghi on lnh CS (Code Segment register) Gi tn hiu cho php (xc nhn) ngt v c vector ngt: Sau khi lu tr tin v v tr b ngt ca chng trnh chnh, VXL gi tn hiu xc nhn ngt INTA (Interrupt Acknowledge) cho KGN ca TBN. Tu cch t chc ngt v to vector ngt, VXL s dng tn hiu ny c vector ngt tng ng ca KGN vo thanh ghi cha A. VXL c ni dung ca nh c a ch l vector ngt bit c a ch u tin ca chng trnh con phc v ngt (chng trnh trao i tin). Thc hin chng trnh con phc v ngt l chng trnh m a ch lnh u tin nm trong nh c a ch l vector ngt. Kt thc chng trnh con ny, c lnh tr v (RET - return) VXL tip tc thc hin chng trnh chnh. Tip tc thc hin chng trnh chnh: Sau khi gp lnh tr v (RET), VXL tin hnh c v hi phc cc tin ca VXL lc b ngt chng trnh ghi nh ch ngt chng trnh (bng lnh POP cc nh ngn xp). Qua trnh c ra ny xy ra ngc li vi qu trnh ghi vo (theo quy lut LIFO Last In First Out) v ni dung ca: Thanh ghi con tr lnh (IP) tr v lch (offset) ca a ch lnh tip theo ca chng trnh chnh b ngt trong mng nh lnh (CS). Thanh ghi mng lnh (CS) v a ch on u tin ca vng nh dnh cho chng trnh chnh b ngt. Thanh ghi flag lc b ngt chng trnh. 3.2.2. X l ngt cng trong IBM - PC: VXL 80x86 c 3 chn dng cho ngt cng l: INTR: Interrupt Request NMI: NonMaskable Interrupt /INTA: Interupt Acknowledge /

INTR l tn hiu u vo yu cu ngt ca VXL v n c th che hay cho php thng qua lnh CLI (Clear Interrupt) v STI (Set Interrupt) NMI tng t INTR nhng khng che c bng lnh INTR v NMI c th c kch hot t bn ngoi bng cch ni vo in p 5V vo chn tng ng ca VXL. Nh vy VXL ch c kh nng phc v mt yu cu ngt cng t TBN. m rng kh nng phc v ngt ngoi IBM - PC s dng thm vi mch x l ngt cng lp trnh c PIC (Programmable Interrupt Controller) 8259. S dng PIC 8259 ni vo chn INTR c th m rng s lng ngt cng ln n 64 RAM

ROM

System bus

INT R VXL

INT /INTA Interrupt Controller IR7 . . . IR0 KGN1 ... KGN8

Reset NMI 3.2.2.1 Vi mch x l ngt 8259 S khi:

A0 D0 D7 B m d liu Logic iu khin

INT

A0 0 A0 0 A0 0 A0 0 CAS0 CAS1 CAS2 A0 0

Logic c/ghi

Thanh ghi phc v (ISR)

Gii quyt u tin (PR)

Thanh ghi yu cu ngt

IR0 . . . . IRn

ng dy ni

B so snh v ni tng

Thanh ghi che ngt (IMR)

Cc chn: IR0 IR7 (Chn 18 25) D0 D7 (Chn 11 4) A0 (chn 27) CS (Chn 11) WR (chn 2) RD (chn 3) CAS0 2 (Chn 12,13,15) SP (chn 16)

INTA (chn 26) INT (chn 17) Cu trc PIC 8259 Thanh ghi yu cu ngt IRR (Interrupt Request Register): ghi tm mc ngt(IR0 IR7) t TBN. Thanh ghi Ngt ang phc v ISR (In Service Register): ghi mc ngt ang s dng. Thanh ghi mt n ngt IMR (Interrupt Mask Register). Mch logic gii quyt u tin PR (Priority Resolver) Khi logic iu khin: x l ngt, a yu cu (INT) v xc nhn ngt (INTA)

: Cc li vo yu cu ngt : Cc bit s liu (2 chiu) : a ch chn thanh ghi lnh : Chn vi mch (chip select) : Li vo lnh ghi : Li vo lnh c : Li vo mc ni tng : Trong ch khng m, nu SP = 1 th 8259 l ch (Master). SP = 0 th 8259 l t (Slave) : Li vo xc nhn ngt : Li ra yu cu ngt chng trnh

B m ng dy s liu: m ghi vo cc thanh ghi v m c cc s liu t cc thanh ghi. Logic iu khin c/ghi: to cc tn hiu ghi v c cc thanh ghi m. B m ni tng/so snh: chn cc vi mch 8259 t trong mt vi mch 8259 ch. i vi IBM - PC, 2 PIC c s dng m rng ra 15 ngt cng. PIC1 qun l u vo ngt IRQ0 - 7, PIC2 dnh cho IRQ8 - 15. PIC2 c ni tng ?ln PIC1 qua ng IRQ2 (Do nu ta chn ngt IRQ2 th ton b IRQ 8 - 15 cng b che. 3.2.3. Lp trnh x l ngt cng:
Port 20H

INT R

INT Pri PIC / INTA

MPU
/ INTA

IR0 IR1 IR2 IR3 : IR7 :

IRQ0 IRQ1 IRQ3 : IRQ7 Port A0H INT Sec PIC CAS0-2 / INTA IR0 IR1 IR2 : IR7 IRQ8 IRQ9 IRQ10 : IRQ15

CAS0-2

Trong my IBM - PC c 2 PIC c nh v ti cc a ch l PIC1 - 20H, PIC2 - A0H. Cc PIC c khi to bi BIOS, do ta ch cn quan tm ti 2 lnh khi lm vic vi chng. Lnh th nht tc ng vo t iu khin OCW1 thit lp vic che ngt Nu mun che ngt no th ta xo bit tng ng vi ngt v 0. T iu khin OCW1 c gi ti a ch base + 1. Lnh th 2 l lnh End of Interrupt (EOI). Lnh ny c gi ti PIC khi kt thc chng trnh con x l ngt reset PIC. Lnh EOI c gi ti PIC bng cch ghi gi tr 20H vo thanh ghi c a ch base. Thc hin chng trnh x l ngt; Trong ngn ng C ta c th thc hin mt chng trnh x l ngt bng khai bo:
void interrupt myISR()

Trong yourISR l con tr tr n a ch m chng trnh ISR ca ta nm trong b nh. a ch ny sau s c t vo bng vector ngt, v c gi khi c ngt. Khung ca mt chng trnh ISR vit bng C nh sau:
void interrupt myISR() { disable(); /* Interrupt Service Routine (ISR) */

/* Body of ISR goes here */ oldhandler(); outportb(0x20,0x20); /* Send EOI to PIC1 */ enable(); }

nh ngha mt hm l mt chng trnh con x l ngt.


void interrupt yourisr()

disable(); xo c ngt lm cho cc ngt cng khc (ngoi tr ngt NMI) khng thc hin c. V trnh trng hp cc ngt khc c u tin cao hn s ngt chng trnh x l ngt ca chng ta. Tuy vy vic ny c th khng cn thc hin. Phn thn ca chng trnh ISR gm cc lnh m ta mun thc hin khi yu cu ngt c kch hot. Cc cng hoc cc thit b ngoi c th ngt VXL bi rt nhiu l do, vd nh nhn c mt byte, time-out, trn b m,.... Khi chng trnh ISR phi c thanh ghi trng thi ca KGN bit nguyn nhn gy ra ngt ca thit b, v c nhng thao tc tng ng. i khi ngoi chng trnh x l ngt ca ta, h thng cn mt s chng trnh thng tr khc cng c kch hot khi c ngt . V vy sau khi thc hin xong cc thao tc ca mnh, chng trnh ISR ca chng ta phi c li gi ti chng trnh ISR c (nu c). Thc hin bng lnh gi con tr tr ti a ch ca chng trnh ISR c. Trong trng hp ny l oldhandle() Trc khi thoat khi chng trnh con ISR, ta phi bo cho PIC bit l ta kt thc chng trnh ISR bng cch gi lnh EOI ti PIC tng ng. Chng trnh con ISR mun c thc thi phi c mt chng trnh khi to v qun l n. on chng trnh sau s khi to v qun l chng trnh con myISR m ta va to. Gi thit chng ta s dng ngt IRQ3
#include <dos.h> #define INTNO 0x0B /* Interupt Number - See Table 1 */ void main(void) { oldhandler = getvect(INTNO); /* Save Old Interrupt Vector */ setvect(INTNO, myISR); /* Set New Interrupt Vector Entry */ outportb(0x21,(inportb(0x21) & 0xF7)); /* Un-Mask (Enable) IRQ3 */ /* Set Card - Port to Generate Interrupts */ /* Body of Program Goes Here */ /* Reset Card - Port as to Stop Generating Interrupts */ outportb(0x21,(inportb(0x21) | 0x08)); /* Mask (Disable) IRQ3 */ setvect(INTNO, oldhandler); /*Restore old Interrupt Vector before exit*/ }

Trc khi thay th a ch ca chng trnh ISR mi vo bng vector ngt , ta phi lu vector ngt c, ta c th phc hi li sau khi thot khi chng trnh. Thc hin bng lnh
oldhandler = getvect(INTNO); /* Save Old Interrupt Vector */

Trong INTNO l s hiu ca vector ngt ta mun lu. Sau ta ci chng trnh ISR mi ca ta vo bng lnh
setvect(INTNO, myISR); /* Set New Interrupt Vector Entry */

Ngt cng ta mun s dng phi c cho php bng lnh


outportb(0x21,(inportb(0x21) & 0xF7)); /* Un-Mask (Enable) IRQ3 */

Phn thn chng trnh chnh tip tc thc hin bnh thng tu theo tng ng dng, vd nh x l ho, giao tip vi ngi s dng, v.v. Khi c bt k s kin lin quan n thit b u c x l t ng bi chng trnh con ISR. Trc khi thot khi chng trnh chnh ta lun phi khi phc li vector ngt c.
setvect(INTNO,oldhandler); /*Restore old Interrupt vector before Exit*/

3.3. Trao i tin trc tip khi nh Data Bus

HOLD

DREQ DMAC MEMORY Disk Controller

VXL

HLDA

DACK

Address Bus Control Bus (IOR, IOW, MEMR, MEMW) 3.3.1. C ch hot ng: VXL khi to TBN TBN khi xng vic truyn s liu bng cch s dng cc thng tin cung cp bi VXL thng qua qu trnh khi to TBN thc hin vic truyn s liu bng cch truyn trc tip gia TBN v b nh thng qua s iu khin ca b iu khin DMA (DMAC) 3.3.2. Hot ng ca DMAC: Khi to: Trc khi a DMAC vo hot ng, Phi c chng trnh khi to cho n. Qu trnh khi to s cung cp cho DMAC thng tin cn thit hot ng. l cc thng tin nh: a ch bt u ca khi d liu, kch thc khi d liu, chiu c/ghi d liu, s hiu cng ca TBN. Hot ng: Xt trng hp truyn mt khi d liu t b nh ra TBN. (1) Bc 1: TBN yu cu DMA bng cch t tn hiu DREQ ln mc cao (2) Bc 2: DMAC t tn hiu mc cao vo chn HRQ (Hold Request) gi tn hiu yu cu treo bus cho VXL, bo cho VXL bit DMAC cn s dng bus. (3)Bc 3: VXL kt thc chu k bus hin ti, chuyn cc cng ghp ni vi bus sang mc tr khng cao v tr li yu cu DMA bng tn hiu mc cao chn HDLA (Hold Acknoledge) bo cho DMAC c quyn s dng bus (4) Bc 4: DMAC kch hot tn hiu DACK bo cho TBN bit n s bt u iu khin vic truyn d liu.

(5)Bc 5: DMAC bt u truyn d liu t b nh ti TBN nh sau:


o DMAC t a ch ca byte u tin ca khi d liu ln bus a ch o Kch hot tn hiu /MEMR c byte d liu t b nh ln bus d liu o t a ch ca cng TBN ln bus a ch o Kch hot tn hiu IOW ghi byte d liu ang c trn bus d liu ra TBN o Gim gi tr m v tng gi tr i ch o Lp li qu trnh trn cho ti khi gi tr m bng 0. (6) Sau khi qu trnh DMA kt thc, DMAC xo gi tr HRQ xung mc thp, tr quyn iu khin bus cho VXL. 3.3.3. Chip iu khin truy nhp b nh trc tip DMAC 8237 (Direct Memory Access Controller) DMAC 8237 c th thc hin truyn d liu theo 3 kiu: kiu c (t b nh ra thit b ngoi vi), kiu ghi (t thit b ngoi vi n b nh) v kiu kim tra.

Khi Timing and Control (nh thi v iu khin): To cc tn hiu nh thi v iu khin cho bus ngoi (external bus). Cc tn hiu ny c ng b vi xung clock a vo DMAC (tn s xung clock ti a l 5 MHz). Khi Priority encoder and rotating priority logic (m ho u tin v quay mc u tin): DMAC 8237A c 2 m hnh u tin: m hnh u tin c nh (fixed priority) v m hnh u tin quay (rotating priority). Trong m hnh u tin c nh, knh 0 s c mc u tin cao nht cn knh 3 c mc u tin thp nht. Cn i vi m hnh uu tin quay th mc uu tin khi khi dng ging nh m hnh u tin c nh nhng khi yu cu DMA ti mt knh no d c phc v th s c t xung mc u tin thp nht. Khi Command Control (iu khin lnh): Gii m cc thanh ghi lnh (xc nh thanh ghi s c truy xut v loi hot ng cn thc hin).

Cc thanh ghi:

DMAC 8237A c tt c 12 loi thanh ghi ni khc nhau:

Chc nng cc chn ca 8237A: CLK (Input): tn hiu xung clock ca mch. Tn hiu ny thng c ly t 8284 sau khi qua cng o. CS (Input): thng c ni vi b gii m a ch. RESET (Input): khi dng 8237A, c ni vi ng RESET ca 8284. Khi Reset th thanh ghi mt n c lp cn cc phn sau b xo: Thanh ghi lnh Thanh ghi trng thi Thanh ghi yu cu Thanh ghi tm Flip-flop du/cui (First/Last flip-flop) READY (Input): ni vi READY ca CPU to chu k i khi truy xut cc thit b ngoi vi hay b nh chm. HLDA (Hold Acknowledge)(Input): tn hiu chp nhn yu cu treo t CPU DRQ0 DRQ3 (DMA Request)(Input): cc tn hiu yu cu treo t thit b ngoi vi DB0 DB7 (Input, Output): ni n bus a ch v d liu ca CPU IOR , IOW (Input, Output): s dng trong cc chu k dc v ghi EOP (End Of Process)(Input,Output): bt buc DMAC kt thc qu trnh DMA nu l ng vo hay dng bo cho mt knh bit l d liu chuyn xong

(Terminal count TC), thng dng nh yu cu ngt CPU kt thc qu trnh DMA.

A0 A3 (Input, Output): chn cc thanh ghi trong 8237A khi lp trnh hay dng cha 4 bit a ch thp. A4 A7 (Output): cha 4 bit a ch HRQ (Hold Request)(Output): tn hiu yu cu treo n CPU DACK0 DACK3 (DMA Acknowledge)(Output): tn hiu tr li yu cu DMA cho cc knh. AEN (Output): cho php ly a ch vng nh cn trao i ADSTB (Address Strobe)(Output): cht cc bit a ch cao A8 A15 cha trong cc chn DB0 DB7 MEMR , MEMW (Output): dng dc / ghi b nh. Cc thanh ghi ni: Cc thanh ghi ni trong DMAC 8237A c truy xut nh cc bit a ch thp A0 A3 Bit a ch A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 a ch X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 XA XB XC XD XE XF

Chn chc nng Thanh ghi a ch b nh knh 0 Thanh ghi m t knh 0 Thanh ghi a ch b nh knh 1 Thanh ghi m t knh 1 Thanh ghi a ch b nh knh 2 Thanh ghi m t knh 2 Thanh ghi a ch b nh knh 3 Thanh ghi m t knh 3 Thanh ghi trng thi / lnh Thanh ghi yu cu Thanh ghi mt n cho mt knh Thanh ghi ch Xo flip-flop u/cui Xo ton b cc thanh ghi / c thanh ghi tm Xo thanh ghi mt n Thanh ghi mt n

R/W? R/W R/W R/W R/W R/W R/W R/W R/W R/W W W W W W/R W W

a ch cc thanh ghi ni dng ghi / c a ch:

Knh 0

/IOR 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

/IOW 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

A3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

A2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

A1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

A0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

Thanh ghi a ch c s v a ch hin hnh a ch hin hnh B m c s v b m hin hnh B m hin hnh a ch c s v a ch hin hnh a ch hin hnh B m c s v b m hin hnh B m hin hnh a ch c s v a ch hin hnh a ch hin hnh B m c s v b m hin hnh B m hin hnh a ch c s v a ch hin hnh a ch hin hnh B m c s v b m hin hnh B m hin hnh

R/W? W R W R W R W R W R W R WR WR

a ch cc thanh ghi trng thi v iu khin: /IOR 1 0 1 1 1 1 1 0 1 0 1 0 /IOW 0 1 0 0 0 0 0 1 0 1 0 1 A3 1 1 1 1 1 1 1 1 1 1 1 1 A2 0 0 0 0 0 1 1 1 1 1 1 1 A1 0 0 0 1 1 0 0 0 1 1 1 1 A0 0 0 1 0 1 0 1 1 0 0 1 1 a ch c s v a ch hin hnh a ch hin hnh B m c s v b m hin hnh B m hin hnh Thanh ghi Ghi thanh ghi lnh c thanh ghi trng thi Ghi thanh ghi yu cu Ghi thanh ghi mt n Ghi thanh ghi ch Xo flip-flop u/cui Xo tt c cc thanh ghi ni

Mch 8237A-5 cha 4 knh trao i d liu DMA vi mc u tin lp trnh c. 8237A-5 c tc truyn 1 MBps cho mi knh v 1 knh c th truyn 1 mng c di 64 KB. c th s dng mch DMAC 8237A, ta cn to tn hiu iu khin nh sau: Tn hiu iu khin cho h thng lm vic vi DMAC 8237A

Tn hiu AEN t 8237A dng cm cc tn hiu iu khin t CPU khi DMAC nm quyn iu khin bus. n tp : Cu 1 : M t li cc ch trao i tin gia my tnh v mi trng bn ngoi bng s khi. Cu 2 : Phn tch xc nh phng php trao i bng ngt c s dng trong trng hp no. Cu 3 : M t c ch hot ng ca mch x l ngt 8259A. Cu 4 : M t c ch hot ng ca mch DMA 8237A.

Chng 4: Rnh cm m rng

Chng 4: KHE CM M RNG


4.1. t vn Khi bn lun v cu trc my tnh ta thng cp n cc cu trc bus, cc ng dn bus nh bus d liu, bus iu khin , v.v. Cc rnh cm m rng l mt dng th hin bng phn cng ca bus trn bn mch chnh, trn c th cm thm cc card m rng thay i hoc nng cp cu hnh ca my tnh. S ra i ca cc loi rnh cm m rng gn lin vi s pht trin ca k thut my tnh. T trc n nay c n 8 kiu bus m rng c s dng cho my tnh c nhn. Vic phn loi cc bus m rng da trn s cc bit d liu m chng x l ng thi. l cc bus: Bus PC (Cn gi l ISA 8 bit) Bus ISA (16 bit) Bus PC/MCIA (16 bit) Bus VESA local (32bit) Bus SCSI (16/ 32 bit) Bus EISA (32 bit) Bus MCA (32 bit) Bus PCI (32/ 64 bit) Bus AGP (32/ 64 bit) S chn khe cm ISA 8 bit Pha mch in GND B01 Reset B02 + 5V B03 IRQ2 B04 - 5V B05 DREQ2 B06 - 12V B07 D tr B08 + 12V B09 GND B10 /MEMW B11 /MEMR B12 /IOW B13 /IOR B14 /DACK3 B15 DERQ3 B16 Pha linh kin A01 /IOCHCK A02 D7 A03 D6 A04 D5 A05 D4 A06 D3 A07 D2 A08 D1 A09 D0 A10 /IOCHRDY A11 AEN A12 A19 A13 A18 A14 A17 A15 A16 A16 A15 Pha mch in /DACK1 B17 DREQ1 B18 /DACK0 B19 CLK B20 IRQ7 B21 IRQ6 B22 IRQ5 B23 IRQ4 B24 IRQ3 B25 /DACK2 B26 TC B27 ALE B28 + 5V B29 OSC B30 GND B31 Pha linh kin A17 A14 A18 A13 A19 A12 A20 A11 A21 A10 A22 A9 A23 A8 A24 A7 A25 A6 A26 A5 A27 A4 A28 A3 A29 A2 A30 A1 A31 A0

Chng 4: Rnh cm m rng

4.2. Bus PC Bus PC l loi bus xut hin trn my tnh PC/XT u tin nn c gi lun l bus PC. Loi bus ny tn dng kin trc ca b VXL Intel 8088, nn c mt bus d liu 8 bit v ngoi v bus a ch 20 bit. Rnh cm ni vi bus PC c 62 chn cho php cm vo mt card m rng lm t mch in 2 mt. V trn bus ny c 8 bit d liu c truyn ng thi nn bus PC cn c gi l bus PCI 8 bit Tc truyn ca bus PC c c nh 4.77 MHz i vi bus ISA 8 bit ta cn quan tm n mt s ng tn hiu chnh sau: Tn hiu Hng M t A0 - A19 I/O 20 ng tn hiu a ch dng nh a ch cho b nh v cc thit b ngoi vi D0 - D7 I/O 8 ng tn hiu to thnh BUS d liu cho vi x l, b nh v cc thit b ngoi vi Reset Out Sau khi bt my tnh hoc sau khi khi ng li, ng dn Reset s kch hot trong thi gian ngn a card c cm vo n mt trng thi ban u xc nh. /IOW Out Input/Output/Write: Tn hiu ny s kch hot khi truy nhp ghi ln mt card m rng. Mc thp ch ra rng cc d liu c gi tr ang ch a ra bus d liu. Cc d liu c n nhn bng sn trc /IOR Out Input/Output/Read: Mc thp ca ng dn a ch ny bo hiu s truy nhp c trn mt card m rng. Trong thi gian ny cc d liu c gi tr cn phi sp xp sau c n nhn bng sn trc AEN Out Address Enable: ng dn iu khin AEN dng phn bit chu trnh truy nhp DMA v chu trnh truy nhp b vi x l. mc cao DMA gim st qua bus a ch v bus d liu. ng dn c hiu lc mc thp. ng dn ny cn phi c s dng cho qu trnh gii m a ch bi card m rng. 4.3. Bus ISA (16 bit) Cng ty my tnh IBM pht trin bus ISA dng trong my tnh AT da trn b VXL 80286. im mnh ca bus ny l c th cho php cng mt lc x l hoc trao i vi 16 bit d liu. m bo tnh tng thch vi bus PC, cc nh thit k b xung rnh cm th 2 thng hng vi rnh cm PC 8 bit, trn c cha 8 bit d liu v 4 bit a ch. Nh vy bus ISA c mt bus d liu 16 bit v mt b a ch 24 bit. Ging nh bus PC, n s dng tc ng h c nh 8.33 MHz Do cch t chc rnh cm nh vy nn mt card PC vn c th cm vo mt khe cm ca bus ISA. Card ISA rt ph bin bi v chng th hin tnh nng u vit i vi hu ht cc ng dng ghp ni. Cc linh kin c s dng trn card u rt r, cho nn trn thc t vic ghp ni bng cc card m rng ISA t ra l cng ngh qua th thchs v ng tin cy.

Chng 4: Rnh cm m rng 4.4. Bus PCI Cng ty Intel xy dng nn mt tiu chun ghp ni mi c tn l bus cc b PCI (Peripheral Componel Interconnection - Kt ni cc thnh phn ngoi vi) hay thng gi tt l bus PCI, dng cho b x l Pentium. Bus ny cho php truy nhp rt nhanh ti b nh, b iu khin a, card m thanh, card ho. Vi mch ghp ni dng cho bus ny l chip PCI 82430 cho php ghp ni trc tip vi bus. Mt s c im chnh: Bus PCI truyn d liu bng tc ca ng h h thng cho php truyn d liu vi tc cao hn nhiu so vi bus ISA. C th hot ng vi 64 bit - Tc ti a t c l 264 Mbyte/s Rnh cm PCI c mt chn cao hn do vy khong tng thch vi cc card ISA. 4.5. Ghp ni qua khe cm m rng 4.5.1. Mt s c im ca Card ISA Kch thc ln nht ca cc card ISA 8 bit l: Chiu cao: 106,7 mm (hay 4.2 inch) Chiu di 333.5 mm (hay 13.13 inch) Chiu dy - k c linh kin - 12.7 mm (hay 0.5 inch) Cc ng tn hiu ca khe cm b tr c 2 pha, v vy card m rng bao gi cng phi l bn mch in 2 mt. 4.5.2. Gii m a ch v kt ni Bus d liu i vi my PC vng a ch 300 - 31FH c d tnh dnh ring cho card m rng cm thm vo. Cc ng a ch s dng i vi vng ny l A0 - A9. Trn mt card m rng thng c nhiu khi chc nng nh b bin i tng t /s ADC, b bin i s - tng t DAC, khi xut nhp d liu s, iu khin hin th, .v.v. . Cc khi ny c trao i di nhng a ch khc nhau t my tnh. Do , trn card m rng phi c thm mt b gii m a ch. B gii m a ch c nhim v so snh i ch trn bus a ch ca my tnh vi cc a ch c thit lp trc cho cc khi chc nng ca card m rng. Khi a ch c s thng nht vi khi no th khi tng ng s c kch hot thng qua mt ng tn hiu logic t u ra ca b gii m. Khi c kch hot, khi mi c th tin hnh s trao i thng tin vi my tnh. B gii m a ch 74HC688 so snh cc ng dn a ch A2 - A9 xem c thng nht vi a ch thit lp trc ca card m rng bng chuyn mch DIP. 74HC688 so snh cc cp bit xem c ging nhau khng. Khi cc cp ng nht thi s to ra mt tn hiu mc thp u ra. Ngoi ra khi gii m cn phi quan tm n ng tn hiu AEN (Address ENable). ng ny cho bit CPU hay DMAC ang chim quyn s dng bus. Khi tn hiu ny mc thp th card m rng mi c s dng cc bus. Tn hiu AEN c a ti u vo /G ca 74HC688 cho php b gii m hot ng. Cc ng tn hiu A0, A1, IOR, IOW cng c s dng trong b gii m bng cch kt hp vi cc IC cng logic AND, OR v vi mch gii m 74HC138 to thnh cc ng iu khin c ghi cho tng khi chc nng trn card B gii m logic ng thi m nhn vai tr iu khin b m bus 2 chiu 74HC245. B ny ni cc ng dn d liu ca rnh cm PC vi cc ng dn ca card m rng. Cch ghp

Chng 4: Rnh cm m rng ni ny rtquan trng, nh vy m cc mc tn hiu trn ng dn d liu khng b nh hng. N c cha 8 vi mch m vi cc li ra 3 trng thi trao i thng tin gia cc ng dn bus d liu theo 2 hng. Hng truyn d liu c xc nh bng chn DIR: DIR = 0, d liu c chuyn t B sang A. Vic chuyn hng d liu cho php qun l n gin bng tn hiu /IOR. Ta c th ni trc tip ra chn DIR. Qua m bo b m ch cho php d liu a vo t bn ngoi a ln bus d liu ca my tnh khi PC thc hin mt qu trnh truy nhp c (/IOR = 0)
19 1 A09 A08 A07 A06 A05 A04 A03 A02 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 Q? 742 45 G DIR A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 18 17 16 15 14 13 12 11 Q? 1 2 3 6 4 5 U? NAND /IOR /IOW RESET NAND U? VCC A B C G1 G2A G2B Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 15 14 13 12 11 10 9 7 D0 D1 D2 D3 D4 D5 D6 D7

MC74 F2 45 A0 A31 A1 A30

SN74L S138

B14 B13 B02

U? NAND

Q? A11 A29 A28 A27 A26 A25 A24 A23 A22 AEN A2 A3 A4 A5 A6 A7 A8 A9 1 2 4 6 8 11 13 15 17 /G P0 P1 P2 P3 P4 P5 P6 P7 74HC688 R? RE S2 /(P=Q) Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 3 5 7 9 12 14 16 18 1 2 3 4 5 6 7 8 SW DIP-8 Q? 16 15 14 13 12 11 10 9

VCC

n tp

Chng 5: GHP NI TRAO I TIN SONG SONG 5.1. Khi ghp ni song song n gin Ca vo n gin: Gm mt b gii m a ch - lnh v cc ca vo 3 trng thi a trc tip s liu song song t thanh ghi m s liu t TBN vo ng dy s liu (D0 - Dn) ca MVT A0 - An RD D0 D1 D2 D3 DI0 DI1 DI2 DI3 Gii m a ch

Ca ra n gin: Cng c b gii m a ch - lnh, nhng c thm cc thanh ghi cht s liu ra ghi s liu a ra t MVT. Li ra c th c thm s 3 trng thi c lp TBN vi bus ca MVT A0 - An WR D0 D1 D2 D3 D Q C D Q C D Q C D Q C DO3 DO2 DO1 DO0 Gii m i ch

5.2. Cc vi mch m, cht (74LS245, 74LS373) 5.2.1. Vi mch m 74LS245: Vi mch 74LS245 cho tn hiu vo ra 2 chiu dng m s liu trong my tnh PC/XT (VXL 8086). Vi mch ny c 2 ng iu khin chnh, tn hiu /G l tn hiu cho php vi mch hot ng, khi /G mc cao, cc chn d liu ca vi mch trng thai tr khng cao.

Inputs G L L H DIR L H X

Function A bus B bus Output Input Input Output High Impedance

Outputs A=B B=A Z

Tn hiu DIR xc nh chiu truyn d iu. DIR = 1 d liu c truyn t A sang B, ngc li, khi DIR = 0 d liu c truyn t B sang A 5.2.2. Vi mch cht 74LS373:

Vi mch bao gm cc vi mch cht v cc vi mch cng 3 trng thi. Vi mch ny thng c dng cht a ch trong my PC/XT v cht d liu trong cc ng dng ghp ni my tnh. C 2 ng tn hiu iu khin l /OE v LE. Tn hiu /OE l tn hiu cho php hot ng ca vi mch. Khi /OE mc cao, cc cng ca vi mch trng thi tr khng cao. Tn hiu LE l tn hiu cho php cht, tn hiu ny tch cc mc dng. i vi 74LS373, khi LE mc cao, tn hiu a vo t cng D c a ra cng Q. Khi LE chuyn sang mc thp, tn hiu cng Q c cht li.

5.3. Vi mch PPI 8255A 5.3.1. Gii thiu chung Vi mch vo ra song song lp trnh c PPI (Programable Parallel Interface) 8255 do hng Intel ch to. Ngoi kh nng cho php to mt giao din song song lp trnh c ghp ni vi my tnh, n cn c th hot ng vi cc ch khc nhau v kh nng lp xo bit ca C cho i thoi. Vi mch 8255 ny rt thng dng, thng c trong cc my tnh PC/XT, PC/AT v cc thit b trao i tin khc.
Bus ni b Nhm A Cng A iu khin nhm A

m bus D

Nhm A Cng C (cao)

PC4-PC7

iu khin nhm B RD WR A0 A1 R CS Logic iu khin ghi / c

Nhm B Cng C (thp)


PC0-PC3

Nhm B Cng B
PB0-PB7

Vi mch gm: B m s liu trao i tin v s liu hai chiu gia PPI v bus ca my tnh. B logic iu khin c vit: tc l b gii m a ch lnh cho cc thanh ghi m v thanh ghi iu khin. Phn ghp ni vi thit b ngoi c: Ca A: thanh ghi m s liu (8 bit), vo hoc ra tu theo chng trnh khi pht Ca B: thanh ghi m s liu (8 bit), vo hoc ra tu theo chng trnh khi pht Ca C: Chia lm 2 na, cao v thp Tu theo ch s dng cho bi t iu khin ca C c th c dng Trao i s liu vo hoc ra

iu khin hoc i thoi vi TBN v VXL khi ca A v B ch xc lp v xo tng bit PCi iu khin hoc i thoi vi TBN v VXL khi ca A v B ch 1 v 2 Cc mch iu khin ni b: C cc khi iu khin (nhm A, nhm B) cc ca A, B v C. 5.3.2. Cc lnh ghi v c cc cng v cc thanh ghi iu khin Vi t hp cc tn hiu a ch (A0, A1), chon vi mch (CS), v cc lnh c ghi (RD, WR) ca VXL, ta c cc lnh ghi c khc nhau cho cc ca (A, B, C) v thanh ghi iu khin nh bng 3.2, to ra s di chuyn s liu gia ng dy s liu, cc ca v thanh ghi iu khin. Nh vy, vi mch 8255 c c im l khng c lnh c thanh ghi trng thi m dng lnh c ca C khi vi mch ch 1 v 2, cn ch 0, khng c trng thi. A1 0 0 1 1 0 0 1 1 X A0 0 1 0 1 0 1 0 1 X
CS
WR

RD

Lnh (ca VXL) c cng A c cng B c cng C Ghi cng A Ghi cng B Ghi cng C Thanh ghi iu khin Trng thi in tr cao

0 0 0 0 0 0 0 0 1

0 1 1 0 1 1 1 1 X

1 1 1 1 0 0 0 0 X

Chiu di chuyn s liu (vi VXL) Cng A -> D0 - D7 Cng B -> D0- D7 Cng C -> D0- D7 Khng c gi tr D0 - D7 -> Cng A D0 - D7 -> Cng B D0 - D7 -> Cng C D0 - D7 -> Thanh ghi iu khin Khng c trao i d liu

5.3.3. Cc t iu khin 5.3.3.1. T iu khin thit lp ch :


Control Word (T iu khin)

5.3.3.2. T iu khin lp D7 bit: xo D6


Mode Flag 1 = Active

D5

D4

D3

D2

D1

D0

D7

D3

D2

D1

D0
C lp/xo

Nhm A Cng C cao


Cng A

Cng C thp

Nhm B

1 = Li vo 0: Lp xa 0 = Li ra bit 1 = Li vo 0 = Li ra 00 = Mode 0 01 = Mode 1 0X = Mode 2

1 = Li xo 0: vo 0 = Li ra

1: lp

Cng B
1 = Li vo 0 = Li ra

Mode

BitD3D2D1PC0000PC1001P 0 1 0 C20 PC3011PC4100PC51 010 0 1 01 110 111 0 PC61 PC71

Mode
1 = Mode 1 0 = Mode 0

5.3.3.4. Cc ch hot ng ca 8255A Ch 0

WR, RD Port B I/O PB0 - PB7

8255A

D0 - D7 Port C I/O PC0 - PC3 I/O PC4 - PC7

A0, A1, CS Port A I/O PA0 - PA7

Ch ny cn c gi l ch vo hoc ra c s v: Cc ca A, B, v 2 na ca ca C c s dng c lp vi nhau Cc ca c th l ca vo hoc ra tu t iu khin ch ghi vo thanh ghi iu khin S liu ra c cht S liu vo khng c cht Khng c tn hiu i thoi vi VXL cng nh TBN. Nu mun c tn hiu i thoi, phi dng cc bit ca ca no (thng l ca C) cc lp ln 1 v sau l xo v 0 bng cch ghi s liu hoc bng cch xc lp/ xo mt bit PCi ca ca C bi t iu khin vi D7 = 0. Khi cng C phi thit lp ch ra. Lp xo tng bit ca cng PC ch 0, ngi ta c th dng cc bit PCi ca ca C lp (t ln 1) v xo (xo v 0) iu khin hoc i thoi vi TBN. Mun vy phi ghi li lnh vi D7 = 0 vo thanh ghi iu khin ca 8255A sau khi ghi li iu khin ch . Ch 1:

Port B I/O

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

Port A I/O

INTRB

INTRA

Ca vo Ca ra

PB0 - PB7

IBFB STBB OBFB ACKB

STBA IBFA I/O I/O I/O

I/O

ACKA OBFA

PA0 - PA7

i thoi ca B

i thoi ca A

Ch ny cn gi l ch vo ra c i thoi vi cc bit ca C. Chia thnh 2 nhm.

Nhm A gm ca A trao i s liu v na C cao (PC3 PC7) i thoi vi VXL v TBN. Nhm B gm ca B trao i s liu v na C thp (PC0 PC2) i thoi vi VXL v TBN. Chiu v ch 1 ca ca A v B do t iu khin quyt nh, cn cc tn hiu i thoi PCi cn ph thuc chiu ca vo hay ra ca ca A, B PC0 lun l tn hiu ra INTRB: tn hiu yu cu ngt chng trnh cho B PC3 lun l tn hiu ra INTAA: tn hiu yu cu ngt chng trnh cho A PC2 lun l tn hiu vo, nhn cc tn hiu yu cu STB B v xc nhn /ACKB ca thit b ngoi cho ca B chung cho c 2 chiu vo hay ra. Cn na A, nu l ca vo, PC4 nhn /STBA ca thit b ngoi v PC6 nhn /ACK ca thit b ngoi nu ca A l ca ra. Cc bit cn li ca ca C l vo hay ra tu t iu khin ch Ch ra: Mi khi d liu c ghi ra cng, tn hiu /OBF chuyn sang mc tch cc 0 thng bo cho TBN bit d liu c cht cng ra v sn sng cho TBN c. Khi c c d liu, TBN kch hot tn hiu /ACK cho bit c d liu, khi tn hiu /OBF c t ng chuyn v mc cao.

/OBF (Output Buffer Full): L tn hiu ra thng bo cho TBN bit d liu c cht cng ra A hoc B. /ACK (Acknowledge): Tn hiu xc nhn bo v t TBN lm cho chn OBF chuyn ln mc cao. Tn hiu ny thng bo cho 8255 bit TBN nhn d liu. INTR: Tn hiu ny thng thng dng ngt VXL mi khi TBN gi li tn hiu /ACK INTE (Interrupt Enable): Bit ni, dng cho php hay cm tn hiu INTR. INTEA c lin kt vi PC6 nu cng A hot ng ch ra. PC4 nu ch vo INTEB lin kt vi PC2 vi c chiu ra v vo ca cng B Ch vo:

/STB: Chn nhn tn hiu xung cht. Khi c mt xung mc thp tc ng vo chn ny, d liu a t TBN vo 8255 s c cht cng vo. IBF: Khi tn hiu /STB tch cc tn hiu IBF s c chuyn sang mc cao, bo cho TBN bit 8255 cht d liu cng vo. Tn hiu ny s tr v mc thp khi VXL c tn hiu ang cht cng (khi tn hiu /RD tch cc) INTR: Tn hiu ngt VXL, tch cc khi /STB chuyn sang mc cao. Khi c tn hiu /RD tn hii\ ny s thi tch cc. Ch 2:

Port B I/O

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

Port A I/O

INTRA

PB0 - PB7

I/O (Ch 0) i thoi (Ch 1)

STBA IBFA

ACKA OBFA

PA0 - PA7 (2 chiu)

Ca B c th ch 0 hoc 1

Ca A ch i thoi 2 chiu

Ch ny ch dng cho ca A vi vo ra hai chiu v cc bit PC3 PC7 dng lm tn hiu hi thoi. Ca B lc ny c th hot ng ch 0 hoc 1, chiu vo hay ra c th t bng t iu khin. V d: Gi thit ta cn thit lp: PPI hot ng ch 0. Cng A vo, B ra, C cao vo, C thp ra. -> Ta c gi tr ca t iu khin l 98H Cng B hot ng ch 1, vo. Cng A hot ng ch 0, ra. Cng C cao ra, cng C thp khng quan tm - > Gi tr t iu khin: 87H hoc 86H 5.3.3.4. T trng thi Thng thng khi s dng 8255 ch 1 v 2, ta thng dng phng php iu khin bng ngt chng trnh. Tuy nhin ta c th s dung phng php hi vng trng thi bng cch c cng C bit c trng thi hot ng ca 8255. Do ta c th coi a ch cng C trong

ch 1 v 2 l a ch ca thanh ghi trng thi ca 8255. c thanh ghi trng thi ny, ta c th bit c cc thng tin sau: C yu cu ngt chng trnh trao i tin ca cc ca A (INTRA) hay B (INTRB) Cc thanh ghi m s liu vo c s liu (IBFA=1, IBFB=1) Cc thanh ghi m ra c s liu (/OBFA = 0, /OBFB = 0) Hoc ring vi ch 2, khi c ngt xy ra, ta cn phi c t trng thi bit c nguyn nhn gy ra ngt l do 8255 nhn c d liu hay gi c d liu c cc hot ng tng ng. 5.3.4. Ghp ni 8255A vi MVT v TBN 5.3.4.1. Ghp ni 8255A vi MVT v TBN S ghp ni ca vo ra theo chng trnh vi VXL v TBN nh hnh di. PPI 8255A t gia VXL v TBN, ng vai tr trung chuyn tin gia VXL v TBN qua cc ng dy ca MVT v TBN.

INTR

D0 D7

D0 D7

INTR INTR A
B

8 PA0 PA7

Reset

VXL A0
A1

RD WR
Gii m a ch

RST

8255 A

PC 8 PA0 PA7

TBN RD WR

A2 - An

C S
Phn ghp ni vi MVT Cc tn hiu v s liu (data bus) D0 D7, a ch thp (A0,A1), lnh c (RD), lnh ghi (WR) c ni thng vi cc li vo tng ng ca PPI 8255A

Tn hiu /CS (Chip Select) ca PPI c ni vi b gii m cc a ch cao (A2 An) ca VXL Cc tn hiu ra yu cu ngt chng trnh (INTRA , INTRB) ca 8255 c ni vo li vo INTR ca VXL qua mt vi mch logic OR Phn ghp ni vi thit b ngoi: Tu thuc loi TBN, s bit ca ng dy s liu v phng thc trao i tin m ta c cch mc ng dy khc nhau. Ch 0: Ba ng dy PA, PB, PC u c dng trao i s liu hoc tin v iu khin v trng thi mt cch bnh ng vi nhau v tu la chn. ch ny c th: o Khng cn i thoi gia 8255 v TBN, ch c trao i s liu trn 1 trong 3 cng o Nu cn tin v iu khin hay c trng thi ca TBN ta s dng thm cc ca khc cho mc ch ny ngoi ca trao i s liu Ch 1: Ch c hai ca A,B trao i s liu c lp nhau, cn cc ng PCi ca ca PC dng hi thoi cho cc ca A,B trn. Cc ng ny c chiu v vai tr xc nh do khng th thay i. Ch 2: Ch cho ca PA vi s liu vo/ra hai chiu. Cc bit ca PC cng c vai tr v chiu xc nh cc ch bt tay (i thoi), gia 8255 v TBN ch trao i hai tn hiu hi p m thi 5.3.4.2. Mt s ng dng ghp ni 8255 vi thit b ngoi: Mch ghp ni 8255 ch 0: INTR D0 D7 8 D0 D7 PC0 PC1 RST PC4 PA0 PA7 /ACK Busy Data Strobe PB0 PB7 EOC Start

My in

Reset

VXL A0
A1

RD WR
Gii m a ch

8255 A
PC3 PC5

RD WR
ADC

A2 - An

C S

Trong cch ghp ni 8255 vi my in qua cng PA c chiu ra, v ghp ni vi mt b bin i tng t - s qua cng PB c chiu vo nh trn, cng C c dnh cho cc tn hiu i thoi. Trong : Na C thp l ca vo, c trng thi ca my in v ADC o PC0 cho trng thi my in bn (busy) o PC1 cho tn hiu ACK ca my in o PC2 Cho tn hiu EOC (End of Convertion) ca ADC Na C cao a ra cc tin v iu khin o PC4 a ra tn hiu cht d liu cho my in o PC5 a ra tn hiu Start cho ADC. Ghp ni 8255 ch 1:

INTR

D0 D7

D0 D7 PC3 PC0 PA /ACK Busy Data Strobe PB EOC Start

Reset

VXL A0
A1

RD WR
Gii m a ch

RST

My in

8255 A

RD WR
ADC

A2 - An

C S
5.3.4.4. Chng trnh trao i tin cho 8255A Tu theo cch mc v TBN, chng trnh cn c cc khi lnh c bn sau: 1. Khi to: l lnh ghi vo thanh ghi iu khin ca 8255 vi a ch thp A0, A1 = 11 ti t iu khin. Cc bit t iu khin ny c xc nh bi: - Ch ca cc ca

- Chiu (vo/ra) ca cc ca 2. iu khin TBN: Cn a ni dung ca cc bit cho cc ca dng iu khin TBN. Nu ch 1,2 cc bit nay l cc bit PCi ca i thoi, ta khng cn phi vit lnh a gi tr ra na. Cn trng hp ch 0 ta c th dng mt trong hai cch sau: - Lp/ xo tng bit PCi ca ca PC - a tin ra cc bit ca cc ca 3. c v kim tra trng thi: - Cc lnh c vo o Thanh ghi trng thi nu ca dng ch 1, 2 o Mt ca bt k ch 0 dng ghi trng thi ca TBN. - Lnh v logic (AND) chn cc bit khng cn kim tra - Lnh so snh (CMP) vi cc gi tr 1 ca bit - Lnh tr v v tr c lnh c trng thi nu kt qu so snh khng ng trng thi cn xt 4. Trao i s liu: - a s liu vo (IN v VXL h 86) hay chuyn s liu MOV (ca VXL 8085) - a s liu ra (OUT) hay chuyn s liu MOV 5.4. Ghp ni song song qua cng my in 5.4.1. Gii thiu chung Cng my in l giao din thng c s dng nhiu nht trong cc ng dng ghp ni my tnh n gin, do tnh ph cp v n gin trong vic ghp ni v iu khin cng vi yu cu ti thiu v thit b phn cng thm vo. Cng ny cho php a vo ti 13 bit v a ra 12 bit song song, trong c 4 ng iu khin, 5 ng bo trng thi v 8 ng d liu. Trong hu nh bt k PC no ta cng c th tm thy cng my in pha sau. u ni ny c dng DB 25 chn (gic ci female).

Cc cng song song gn y c chun ho theo chun IEEE 1284 a ra nm 1994. Chun ny m t 5 ch hot ng ca cng my in nh sau: Ch tng thch (Compatibility mode) Ch Nibble Ch Byte Ch EPP Ch d ECP

Ch c s (hay cn gi l Centronics mode) c bit dn t lu. Ch ny ch cho php a d liu theo mt chiu ra (output), vi tc ti a 150kB/s. Mun thu d liu (input) ta phi chuyn sang ch Nibble hay Byte. Ch Nibble c th cho php a vo 4 bit song song mt ln. Ch Byte s dng tnh nng song song hai hng ca cng my in a vo mt byte. a ra mt byte ra my in (hoc cc thit b khc) trong ch c s, phn mm phi thc hin cc bc sau: (1) Vit d liu ra cng my in (ghi vo thanh ghi d liu) (2) Kim tra my in c bn khng, nu my in bn, n s khng chp nhn bt c d liu no, do d liu ghi ra lc s b mt (3)Nu my in khng bn, t chn Strobe (chn 1) xung thp (mc 0), bo vi my in l c d liu trn ng truyn (chn 2 - 9) (4)Sau ch 5 microgiy v t chn Strobe ln cao (mc 1). Ch m rng (EPP) v nng cao (ECP) s dng cc thit b phn cng tch hp thm vo thc hin v qun l vic i thoi vi thit b ngoi. ch ny cho phn cng kim tra trng thi my in bn, to xung strobe v thit lp s bt tay thch hp. Do ch cn s dng mt lnh vo ra trao i d liu nn gip tng tc thc hin. Khi cng ny c th a d liu ra vi tc 1 2 MB/s. Ngoi ra ch ECP cn h tr s dng knh DMA v c thm b m FIFO. 5.4.2. Cu trc cng my in Chun IEEE 1284 a ra 3 u ni dng cho cng my in. Dng A (DB25) c th thy hu ht cc my PC, dng B (36 chn) thng thy my in, v dng C, 36 chn, ging dng B nhng nh hn, c cc thuc tnh in tt hn v c thm 2 ng tn hiu dnh cho cc thit b i mi sau ny. S hiu chn (DB25) 1 2-7 10 11 12 13 14 15 16 17 18 - 25 Tn nStrobe Data 0 nAck Busy Paper-Out / Paper-End Select nAuto-Linefeed nError / nFault nInitialize nSelect-Printer / nSelect-In Ground Hng (In/Out) In/Out Out In In In In In/Out In In/Out In/Out Gnd Thanh ghi Control Data Status Status Status Status Control Status Control Control M t Byte c in ng d liu (D0 - D7) Xc nhn (Acknowledge) My in bn Ht giy ( Paper Empty) La chn ( Select ) T np giy ( Auto Feed) Li t li my in

nXXXX: Tch cc mc thp Tn hiu ra ca cng my in thng cc mc logic TTL.

a ch 378h - 37Fh 278h - 27Fh

Cng LPT 1 LPT 2

Khi khi ng BIOS gn a ch cho cc cng my in v lu thng tin a ch ny trong b nh a ch cho bng di: a ch bt u M t 0000:0408 a ch c bn cng LPT1 0000:040A a ch c bn cng LPT2 0000:040C a ch c bn cng LPT3 0000:040E a ch c bn cng LPT4 Chng trnh v d c thng tin a ch ca cc cng my in c trong my tnh:
#include <stdio.h> #include <dos.h> void main(void) { unsigned int far *ptraddr; /* Pointer to location of Port Addresses*/ unsigned int address; /* Address of Port */ int a; ptraddr=(unsigned int far *)0x00000408; for (a = 0; a < 3; a++) { address = *ptraddr; if (address == 0) printf("No port found for LPT%d \n",a+1); else printf("Address assigned to LPT%d is %Xh\n",a+1,address); *ptraddr++; } }

5.4.3. Cc thanh ghi ca cng my in: 5.4.3.1. Thanh ghi d liu (Data Register) a ch Base + 0 Tn Data Port Read/Write Write S hiu bit Bit 7 0 M t Data 7 - 0

a ch c s (Base address) thng gi l cng d liu (Data port) hay Thanh ghi d liu (Data Register) thng s dng a d liu ra cc chn tn hiu (Chn 2 9). Thanh ghi ny thng l thanh ghi ch ghi. Nu ta c d liu cng ny ta s thu c gi tr m ghi ra gn nht. Nu cng my in l hai chiu th ta c th thu gi liu vo t cng ny. 5.4.3.2. Thanh ghi trng thii (Status Register):

a ch

Tn

Read/Write Read Only

S hiu bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

M t Busy Ack Paper Out Select In Error IRQ (Not) Reserved Reserved

Base + 1 Status Port

Thanh ghi trng thi l thanh ghi ch c. Bt k d liu no vit ra cng ny u b b qua. Cng trng thi c to bi 5 ng tn hiu vo (Chn 10, 11, 12, 13, 15), mt bit trng thi ngt IRQ v 2 bit dnh. Ch rng bit 7 (Busy) l u vo tch cc thp, ngha l khi c mt tn hiu +5V chn 11, bit 7 s c gi tr logic 0. Tng t vi bit 2 (nIRQ) nu c gi tr 1 c ngha l khng c yu cu ngt no xut hin. 5.4.3.3. Thanh ghi iu khin (Control Register): a ch Base + 2 Tn Control Port Read/Write Read/Write S hiu bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 M t Unused Unused Enable Bi-Directional Port Enable IRQ Via Ack Line Select Printer Initialize Printer (Reset) Auto Linefeed Strobe

Thanh ghi iu khin c d nh l ch ghi. Khi mt my in c ni vi my tnh, 4 ng iu khin s c s dng. l cc ng Strobe, Auto Linefeed, Inittialize v Select Printer, tt c u l u ra o tr ng Initialize. Bit 4 v 5 l cc bit iu khin ni. Bit 4 cho php ngt v bit 5 cho php ch vo ra 2 chiu. t bit 5 cho php thu liu vo qua ng Data 0 7. 5.4.3.4. Thanh ghi iu khin m rng ECR (Extended Control Register): Address Base + 402H Bit 7:5 000 Standard Mode 001 Byte Mode 010 Parallel Port FIFO Mode Function Selects Current Mode of Operation

011 ECP FIFO Mode 100 EPP Mode 101 Reserved 110 FIFO Test Mode 111 Configuration Mode 4 3 2 1 0 ECP Interrupt Bit DMA Enable Bit ECP Service Bit FIFO Full FIFO Empty

5.4.4. EPP - Enhanced Parallel Port Cng song song nng cao (EPP) a c thit k bi s lin kt gia cac hang Intel, Xircom & Zenith Data Systems. Cng EPP ban u c thit k theo chun va sau o la chun IEEE 1284 ra i nm 1994. EPP co hai chun: EPP 1.7 va EPP 1.9. Co mt vai s khac nhau gia cac chun nay ma chung co nhng anh hng ti cac thao tac x ly cua thit bi. Vn nay se con c noi n trong phn sau. EPP co tc truyn d liu theo tiu chun la t 500KB/s ti 2MB/s. iu nay cho phep cac thit bi phn cng tai cac cng tao ra tin hiu bt tay (tin hiu moc ni, hi thoai) chng han nh tin hiu stroble, phn mm x ly chung, vi du nh cua Centronics. EPP c s dung rng rai hn ECP. EPP khac vi ECP ch cng EPP phat ra cac tin hiu iu khin va iu khin tt ca qua trinh truyn d liu t no ti thit bi ngoai vi. Bn canh o thi ECP lai yu cu thit bi ngoai vi co s hi thoai tr lai bi mt tin hiu moc ni. iu nay la khng mm deo cho vic thit lp mt lin kt logic va nh vy cn co mt b iu khin chuyn dung hoc mt chip ngoai vi ECP. EPP Hardware Properties (cac c trng phn cng EPP) Khi s dung ch EPP, mt tp cac tac vu khac nhau (co tn tng ng) c sp xp trn mi ng dy tin hiu. Cac tin hiu nay c chi ra trong bang 4. Chung s dung cac tn chung trong SPP va EPP trong cac bang m ta v cng song song va cac tai liu. iu nay co th lam cho no rt cng nhc chi r chinh xac nhng gi ang xy ra. Mc du tt ca cac tai liu y u se s dung tn theo EPP. Pin 1 2-9 10 11 12 13 14 15 16 17 18-25 SPP Signal Strobe Data 0-7 Ack Busy Paper Out / End Select Auto Linefeed Error / Fault Initialize Select Printer Ground EPP Signal Write Data 0-7 Interrupt Wait Spare Spare Data Strobe Spare Reset Address Strobe Ground IN/OUT Out In-Out In In In In Out In Out Out GND Function Mc thp th hin mt chu k ghi, mc cao ch nh l ang c Data Bus. Hai chiu Interrupt Line. Ngt xut hin sn dng ca xung Used for handshaking. A EPP cycle can be started when low, and finished when high. Spare - Not Used in EPP Handshake Spare - Not Used in EPP Handshake Khi mc thp, ch nh l ang truyn d liu (data) Spare - Note used in EPP Handshake Reset - Tch cc thp Khi mc thp, ch nh ang truyn i ch Ground

Cac tin hiu Paper Out, Select va Error khng c xac inh trong tp cac tin hiu bt tay cua EPP. Cac tin hiu nay co th c s dung tuy y theo s inh nghia cua ngi s dung. Trang thai cua cac c tin hiu nay co th c xac inh tai bt ky thi im nao theo s xp xp tin hiu cua thanh ghi trang thai. ang tic la khng co u ra tha. iu nay co th tr nn phc tap cho vic xac inh trang thai tai mt thi im nao o cua cho ky truyn/nhn thng tin. Cc thanh ghi trong ch EPP Ch EPP c mt tp cc thanh ghi mi, trong c 3 thanh ghi c t ch SPP Address Base + 0 Base + 1 Base + 2 Base + 3 Base + 4 Base + 5 Base + 6 Base + 7 Port Name Data Port (SPP) Status Port (SPP) Control Port (SPP) Address Port (EPP) Data Port (EPP) Undefined (16/32bit Transfers) Undefined (32bit Transfers) Undefined (32bit Transfers) Read/Write Write Read Write Read/Write Read/Write -

Qu trnh bt tay ca EPP Theo trinh t thc hin mt chu ky truyn d liu hp khi s dung EPP, chung ta phai theo th t bt tay cua EPP. Do phn cng lam tt ca moi vic nn cac tin hiu bt tay nay chi c s dung cho phn cng cua chung ta ma khng c s dung cho phn mm nh trong trng hp vi SPP. khi tao cho mt chu ky EPP, phn mm chi cn thc hin mt thao tac vao/ra khi tao cho thanh ghi EPP. Chi tit v vn nay se noi cu th sau. EPP Data Write Cycle 1. Chng trnh ghi d liu vo thanh ghi d liu EPP (Base+4) 2. /Write c xo v 0. (Cho bit ang c mt thao tc ghi) 3. D liu c t ln ng truyn d liu (2 9). 4. /Data Strobe c kch hot nu /Wait ang mc thp (Sn sng bt u mt chu k mi) 5. My tnh ch tn hiu xc nhn th hin bi /Wait chuyn sang mc cao 6. Ngng kch hot /Data Strobe Enhanced Parallel Port Data Write Cycle. 7. Chu k ghi d liu EPP kt thc

Qu trnh gi a ch EPP (Address Write Cycle)

Enhanced Parallel Port Address Write Cycle. EPP Chu k c d liu

1. Chng trnh ghi gi tr a ch vo thanh ghi a ch EPP (Base+3) 2. /Write c xo v 0. (Cho bit qa trnh ghi) 3. Gi tr a ch c t ln ng truyn d liu (2 7). 4. /Address Strobe c kch hot nu /Wait ang mc thp (Sn sng bt u) 5. My tnh ch tn hiu xc nhn vng vi /Wait t ln mc cao (TBN c a ch xong) 6. Tn hiu /Address Strobe ngng tch cc 7. Chu k gi a ch EPP 1. Chng trnh ra lnh c thanh ghi d liu EPP (Base+4) 2. /Data Strobe c kch hot nu /Wait ang mc thp(Sn sng mt chu k mi) 3. My tnh ch tn hiu xc nhn (/Wait chuyn sang mc cao) 4. D liu c c t cc chn tn hiu ca cng 5. Ngng kch hot tn hiu /Data Strobe 6. Kt thc chu k c d liu

Enhanced Parallel Port Data Read Cycle. EPP Address Read Cycle

1. Program reads EPP Address Register (Base+3) 2. nAddr Strobe is asserted if Wait is Low (OK to start cycle) 3. Host waits for Acknowledgment by nWait going high 4. Data is read from Parallel Port Pins 5. nAddr Strobe is de-asserted 6. EPP Address Read Cycle Ends Enhanced Parallel Port Address Read Cycle. Chu y: Nu s dung EPP 1.7 (trc IEEE 1284) tin hiu Strobes cho d liu va ia chi co th c dung xac nhn s bt u cua mt chu ky ri cua trang thai i. EPP 1.9 se chi bt u mt chu ky i mc thp. Ca EPP 1.7 va EPP 1.9 chuyn tin hiu i (strobe) ln mc cao kt thuc chu ky.

Cc thanh ghi s dng trong ch EPP Cng EPP cung co mt tp cac thanh ghi mi. Tuy nhin co 3 thanh ghi la a co trc trong cng song song chun. Bang sau cho thy cac thanh ghi a co va cac thanh ghi mi. Address Base+0 Base+1 Base+2 Base+3 Base+4 Base+5 Base+6 Base+7 Port Name Data Port (SPP) Status Port (SPP) Control Port (SPP) Address Port (EPP) Data Port (EPP) Undefined (16/32bit Transfers) Undefined (32bit Transfers) Undefined (32bit Transfers) Read/Write Write Read Write Read/Write Read/Write -

Nh ta co th thy, 3 thanh ghi u la ging ht cac thanh ghi trong tp thanh ghi cua cng song song chun va chc nng cung la ging. Vi th nu ta s dung mt EPP ta co th a d liu ra thanh ghi d liu (Base+0) theo kiu ging nh ta co th a d liu ra nu s dung SPP (Standard Parallel Port). Nu ta a kt ni vi mt may in va s dung ch phu hp, sau o ta phai kim tra xem cng co bn khng, tip theo ta co th bao (strobe) va kim (Ack) tra thng qua vic ghi/oc thanh ghi iu khin va trang thai. Nu mun truyn thng vi mt thit bi tng thich EPP th tt ca cng vic ta phi lm l gi d liu ra thanh ghi d liu EPP (EPP Data Register) tai ia chi Base+4 va cng my in se sinh ra tt ca cac tin hiu bt tay cn thit. Tng t nh vy, nu mun gi mt ia chi ti thit bi, ta s dung thanh ghi ia chi EPP (EPP Address Register) tai ia chi Base+3. Ca thanh ghi a ch (Address Register) va d liu (Data Register) u co th oc va ghi, do oc d liu t thit bi ta c th s dung cng mt thanh ghi. mc d, card may in phi khi pht mt chu ky oc vi tn hiu Data Strobe hoc Address Strobe u ra. Thit bi ngoi vn co th a ra tin hiu yu cu c qua ng tin hiu yu cu ngt va ISR (chng trinh con phuc vu ngt) s thc hin cng vic oc. Cng trang thai co mt s thay i nh. Bit 0 la d tr i vi tp thanh ghi cua SPP thi gi y no la Bit Time-out EPP. Bit nay se c lp khi xut hin mt Time-out EPP. S kin nay xay ra khi ng tin hiu nWait la khng c xac nhn tr lai trong khoang 10us (gia tri nay tuy thuc vao cng khac nhau) cua tin hiu IOR hoc IOW a c xac nhn. Cac tin hiu IOR va IOW la cac tin hiu oc va ghi thit bi (I/O Read va I/O Write) trn bus ISA. Ch EPP co gian thi gian rt ging vi gian thi gian cua bus ISA. Khi thc hin mt chu ky oc, cng phai am nhn trach nhim iu khin phu hp cac tin hiu hi thoai Read/Write va tra lai d liu nh trong chu ky bus cua ISA. Tt nhin qua trinh nay khng ng thi vi chu ky bus ISA, vi th cng s dung tin hiu iu khin IOCHRDY (I/O Channel Ready) trn bus ISA cho bit trang thai i cho n khi hoan thanh chu ky bus. By gi ta co th tng tng rng nu mt qua trinh oc hoc ghi EPP c bt u nu nh khng co thit bi ngoai vi nao ni vao thi se ra sao? Cng se khng bao gi nhn c mt tin hiu xac nhn (nWait) vi th ma co c mt yu cu cho trang thai i, may tinh phai thc hin mt vong lp kim tra. , do

n duy tr vic gi tn hiu yu cu v ch kt thc trng thi wait, v my tnh s b treo. Vi vy ma EPP thc hin mt kiu kim tra watchdog ma thi gian time out la xp xi 10uS. Ba thanh ghi: Base+5, Base+6 va Base+7 co th c s dung cho cac thao tac oc/ghi 32 bits d liu nu nh cng co h tr cho no. iu nay co th lam giam cac thao tac vao/ra cua ta. Cng song song co th chi truyn d liu 8 bits tai mt thi im cho nn bt ky mt word 16 hay 32 bits c ghi ti cng song song se c chia thanh cac byte va c gi qua 8 bits (ng) d liu cua cng song song. Lp trnh cng my in trong ch EPP. EPP chi co 2 thanh ghi chinh va mt c trang thai time-out, chung ta co th thit lp chung nhng gi? Trc khi ta co th bt u bt ky mt chu ky EPP bng vic oc va ghi ti thanh ghi d liu va thanh ghi ia chi thi cng phai c cu hinh mt cach ung n cho ch lam vic cua no. trong trang thai t do, cng EPP cn phai co cac tin hiu nAddress Strobe, nData Strobe, nWrite va nReset trang thai khng tich cc ( mc cao - high level). Mt vai cng yu cu ta phai thit lp cac tin hiu nay trc khi thc hin mt chu ky bus EPP. Vi vy nhim vu u tin cua chung ta la khi tao mt cach thu cng cac tin hiu nay bng vic s dung cac thanh ghi cua SPP. Cu th la ghi gia tri xxxx 0100 ti thanh ghi iu khin khi tao. Trn mt vai card, nu cng song song c t trong ch ngc lai, thi mt chu ky ghi EPP se khng th thc hin c. Vi vy no se t bit phai t cng vao ch hp l trc khi s dung EPP. Xoa bits 5 cua thanh ghi iu khin co th lam cho vic lp trinh tr nn thu vi hn ma khng lam pha v s phat trin chng trinh. Bit time-out cua EPP EPP: Khi bit nay c lp, cng EPP co th khng am bao ung chc nng cua no. Mt s kin chung la lun lun oc gia tri 0FFh t ca chu ky ia chi va chu ky d liu. Bit nay nn c xoa cac thao tac c tin cy va no phai lun c kim tra. n tp : Cu 1 : Phn tch xc nh cc vn k thut cn gii quyt khi tin hnh trao i song song gia my tnh IBM-PC vi mi trng bn ngoi. Cu 2 : Thit k mt giao din n gin kt ni my tnh vi mi trng bn ngoi bng mch 8255A. Cu 3 : Thit k mch v chng trnh cho php dng my tnh iu khin h thng n Led thng qua cng LPT.

Chng 6: GHP NI TRAO I TIN NI TIP 6.1. t vn Mt trong nhng k thut ghp ni c s dng rng ri l k thut ghp ni TBN qua cng ni tip Qua cng ni tip c th ghp ni chut, modem ngoi, my in, b bin i A/D, cc thit b o lng, Cc cch ghp ni ny s dng phng php truyn thng tin (d liu) theo kiu ni tip. cc bit d liu c truyn ni tip nhau trn mt ng dy duy nht. Ti mt thi im ch c mt bit d liu c truyn trn ng dy. Truyn thng ni tip c u im l cn t ng dy, c th s dng mt ng truyn, mt ng nhn. Thng tin thu nhn l tin cy, tuy nhin tc truyn l chm. Chun RS232 c xy dng thnh chun chnh thc dnh cho truyn thng ni tip, do hip hi cc nh cng nghip in t EIA (Electronic Industries Association) nm 1962. Chun ny cho php truyn vi tc cc i 19.600 bit/s vi khong cch nh hn 20 m Sau ra i mt s chun nh RS422, RS449, RS485 c tc truyn v khong cch cho php xa hn. Vd: RS422: Tc truyn 10Mbit/s, khong cch >1000m 6.2. Yu cu v th tc trao i tin ni tip: 6.2.1. Yu cu: Khi khong cch gia hai thit b trao i tin l rt ln, vic s dng phng php truyn tin song song s i hi chi ph tn km v ng dy ng thi cng kh khn trong vic chng nhiu trn ng truyn. Do vi vic truyn tin khong cch xa v yu cu v tc khng ln th phng php truyn tin ni tip c s dng. Truyn thng ni tip cn thm cng on gia cng tn hiu chuyn tn hiu song song thnh tn hiu ni tip gi i, sau phi chuyn t tn hiu ni tip thnh song song ni nhn. Vic gia cng tn hiu ny cng tn mt khon chi ph nhng cng gim hn nhiu so vi truyn thng song song. Cac thit bi u cui trong lin kt ni tip co th la cac loai thit bi khac nhau nhng chung phai thng nht vi nhau v cac quy tc v giao thc cung nh inh dang d liu. S thng nht nay am bao d liu c gi ti bn nhn va bn nhn co th hiu c d liu o. Phn nay se trinh bay v inh dang d liu va giao thc truyn d liu s dung trong truyn thng ni tip, va se chu trong hn ti phng phap truyn thng khng ng b do c dung trong chun RS232 cua cng ni tip COM Trong truyn tin ni tip, tai mt thi im chi co mt bit d liu c truyn i va cac bit d liu c truyn tun t nhau. Mt lin kt gia hai bn co th s dung hai ng d liu truyn theo hai hng ring bit hoc co th s dung chung mt ng d liu truyn theo ca hai hng vao cac thi im khac nhau. Vic truyn thng se dung chung mt ng tin hiu cho ca hai hng goi la truyn ban song cng (Half-duplex) con trng hp s dung hai ng tin hiu ring cho hai hng cho phep truyn ng thi ca hai hng thi c goi la truyn song cng y u (Full-duplex). Trong may tinh PC, lin kt ni tip s dung dang Full-duplex. Co mt tin hiu phai co trong truyn tin ni tip o la tin hiu xung ng h (clock). Tin hiu nay giup iu khin dong d liu. Bn gi va bn nhn s dung tin hiu nay quyt inh khi nao

gi va nhn mi bit. Co hai phng phap truyn thng ni tip la truyn thng ng b (Synchronous) va truyn thng khng ng b (Asynchronous). Vi mi loai thi cach s dung tin hiu clock la khac nhau. 6.2.2. Trao i tin ng b: Synchronous Trong truyn thng ng b, hai bn truyn thng s dung chung mt ng tin hiu clock. Tin hiu nay c phat ra bi mt bn hoc bi mt thit bi phat xung ng b ring. Tin hiu ng b nay co th co tn s thay i hoc co mt chu ky khng xac inh. Nghia la mi bit truyn i c xac inh tai mt thi im khi co s thay i mc tin hiu cua tin hiu clock. Bn nhn cung s dung s thay i mc o xac inh khi nao thi oc bit d liu gi ti. Thi du nh bn nhn se cht d liu gi ti khi xut hin sn ln cua xung clock hay la s thay i mc tin hiu t thp ln cao. Truyn ng b bn nhn khng cn phi bit trc tc trao i tin m ch cn qua tm ti tn hiu ng b pht trn ng dy ng b. Truyn thng ng b rt hu ich khi truyn khoang cach gn bi no cho phep truyn thng vi tc cao. Tuy vy vi khoang cach xa, vic truyn thng ng b la khng kha thi do no oi hi co thm mt ng tin hiu clock, nh vy cn mt ng dy thm vao, hn na se d bi nhiu trn ng truyn. Mi khi tin ng b thng gm nhiu byte, cc khi c nh du bi cc byte nh du khung tin, cc byte ny c gi tr l 16H (m ASCII ca ch Sync) Truyn thng ng b phi thc hin lin tc, khi khng c d liu cn truyn th bn pht vn tip tc phi truyn cc d liu trng duy tr s ng b. Truyn thng ng b thc hin kim tra li bng phng php s d vng (chia tng tin ca khung cho mt a thc - gi l a thc sinh). S d ca php chia c ghi vo mt byte FCS (Frame Check Sum). pha thu, cng tnh tng t v so snh kt qu. Nu bng nhau th tin truyn khng b li. 6.2.3. Trao i tin khng ng b - Asynchronous: Trong truyn thng khng ng b, ng truyn se khng cn co thm mt ng tin hiu clock bi vi mi bn a co b phat xung ng b cua ring no. lam c nh vy, hai bn phai thng nht mt tn s xung chung, va tt ca cac xung clock phai khp nhau mt mc nao o. Mi byte truyn i se bao gm mt bit Start ng b xung ng h gia hai bn va mt bit Stop anh du kt thuc byte c truyn. Cng RS-232 cua may PC s dung inh dang khng ng b truyn thng vi cac thit bi ngoai nh modem, may in cung nh truyn thng vi may tinh khac. Tuy rng cng RS-232 co th s dung phng phap truyn ng b nhng phng phap truyn khng ng b vn thng c s dung nhiu hn. Vic truyn thng s dng phng php khng ng b khng cn phi thc hin lin tc. Trong trng thi ngh, ng tn hiu truyn tin s c trng thi tng ng vi mc tn hiu ca bit Stop. Qua trinh truyn thng khng ng b s dung mt s inh dang khac nhau. Thng dung nht la dang 8-N-1. Trong o mi byte d liu gi i bao gm mt bit Start, tip theo o la 8 bit d liu, bt u bng bit 0 (hay bit LSB) va kt thuc bng mt bit Stop. Ky t N trong 8-N-1 co nghia la trong d liu truyn i khng co bit chn le (Parity bit). Bit chn le c s dung nh mt phng phap kim tra li truyn mt cach n gian. Bit chn le co th la bit Chn hoc bit Le. Bit chn co nghia la bit parity c t la chn hay le sao cho s cac bit co gia tri 1 trong cac bit d liu bao gm ca bit Parity la mt s chn, va ngc lai vi Parity le. Khi bn nhn nhn c byte d liu no se kim tra tinh gia tri parity cua byte c nhn, sau o so sanh vi bit parity trong byte va nhn. Nu khng trung nhau co nghia la a co li xay ra trn ng truyn. Bn nhn se thng bao lai bn gi truyn lai byte d liu o.

S bit d liu truyn i trong mt ln truyn co th la t 5 n 8 bit tuy theo tng ng dung. Nu truyn ky t ASCII thi ta truyn 7 bit, nu truyn gia tri nhi phn (truyn file) thi s dung 8 bit. S bit stop cung la mt tham s cn quan tm. S 1 trong 8-N-1 chi ra rng y ta s dung 1 bit Stop. S bit stop co th la 1,5 hoc 2 bit. Tham s rt quan trong trong qua trinh truyn thng o la tc truyn d liu. Tc truyn la s bit c truyn trn ng dy trn mt n vi thi gian, thng thng c tinh bng n vi baud. Trong a s trng hp, n vi nay tng tng ng vi n vi bit trn giy (b/s). Vi inh dang 8-N-1, tc truyn mt byte d liu bng 1/10 tc truyn. Nu ta truyn vi tc 9600 baud thi trong mt giy truyn c 960 byte. 6.3. Truyn thng ni tip s dung giao din RS-232: Chung ta thy rng vic truyn thng ni tip oi hi rt nhiu thao tac phai thc hin. Ta phai chuyn mt byte d liu t dang song song thanh dang ni tip (bi vi hu ht cac h thng s u lam vic vi cac d liu dang song song). Tip theo ta phai tao ra mt li tin theo ung inh dang cho trc bng cach thm cac bit Start, Stop, Parity phu hp. Sau o ta mi truyn d liu i di dang ni tip. Cng ni tip cua may PC co mt vi mach chuyn dung iu khin truyn thng ni tip. Do o, khi s dung cng RS-232 cua may PC truyn thng, tt ca cng vic cua chung ta la gi byte d liu cn truyn ra thanh ghi d liu cua vi mach nay. Sau o moi thao tac cua qua trinh truyn thng k trn se c vi mach thc hin da theo nhng thit lp trong qua trinh khi tao. 6.3.1. Qua trinh truyn mt byte d liu: Trong trang thai ri, gia tri logic trn ng truyn lun bng 1. bao vic bt u truyn d liu, bn gi a gia tri logic 0 ln ng truyn trong khoang thi gian bng dai mt bit. Bit o goi la bit Start. Khi truyn vi tc 300 baud, mt bit co dai la 3,3 ms, trong khi vi tc 9600 baud thi co dai 0,1 ms. Ngay sau bit Start, bn truyn gi tip 8 bit d liu k tip nhau, bt u bng bit LSB. Tip sau o bn truyn se gi tip mt bit co gia tri logic 1 ln ng truyn va duy tri trong khoang thi gian it nht la dai mt bit. Ngay sau o hoc sau mt khoang thi gian bt ky, bit Start tip theo se c gi bt u truyn mt byte mi. 6.3.2. Cng ni tip RS 232 6.3.2.1. Phn cng Nhng thuc tinh cua phn cng Nhng thit bi s dung cap ni tip cho vic truyn thng c chia lam hai loai. o la DCE (Data Communications Equipment) va DTE (Data Terminal Equipment) DCE la nhng thit bi c s dung nh mt modem cua chung ta, b tip hp TA, may ve, ... trong khi o DTE lai c s dung nh may tinh hoc Teminal cua chung ta. Nhng phat minh v cng ni tip cua EIA (Electronics Industry Association) trong o tiu biu la chun RS 232C. No a ra nhiu thng s nh: A Space (logic 0) gia +3V va +12V. A Mark (logic 1) gia -3V va -12V. Vung gia +3V va -3V la khng xac inh. Lit k trn chi la mt phn cua danh sach cua chun EIA. Trong o bao gm ca Line Capacitance, Maximum Baud Rates, ... bit chi tit hn xin tham khao chun EIA RS-232C. Tuy nhin no tht thu vi ghi nh rng Chun RS -232C chi r tc cc i 20,000bps, iu ma

lam cho no kha chm trc nhng tiu chun cua ngay nay. Mt tiu chun mi, RS -232D gn y a c phat hanh. Cng ni tip co hai loai chn cm, o la b ni D-Type 25 chn va b ni D-Type 9 chn, ca hai loai nay u co chung mt c im khac hn vi cng may in la ch ni vi may in may PC la cm, trong khi cac cng ni tip lai la phich cm nhiu chn. Bn di la bang kt ni chn cho b kt ni 9 chn va 25 chn D-Type. D-Type-25 Pin No Chn 2 Chn 3 Chn 4 Chn 5 Chn 6 Chn 7 Chn 8 Chn 20 Chn 22 Chc nng cua cac chn Ch vit tt TD RD CTS DCD DSR DTR RTS RI Tn y u Transmit Data Receive Data Clear to Send Data Carrier Detect Data Set Ready Data Terminal Ready Request To Send Ring Indicator Chc nng Serial Data Output (TXD) - u ra cua d liu Serial Data Input (RXD) - D liu c nhp vao Bao rng Modem sn sang trao i d liu. Khi nao modem phat hin ra mt Carrier t mt modem kt thuc khac cua phone line, thi Line nay tr thanh tich cc. Thng bao vi UART rng modem sn sang thit lp mt mi lin kt . y la s i lp vi DSR. Bao vi Modem rng UART sn sang lin kt . Thng bao cho Modem rng UART sn sang trao i d liu. Goes active when modem detects a ringing signal from PSTN. D-Type-9 Pin No Chn 3 Chn 2 Chn 7 Chn 8 Chn 6 Chn 5 Chn 1 Chn 4 Chn 9 Abbreviation TD RD RTS CTS DSR SG CD DTR RI Full Name Transmit Data Receive Data Request To Send Clear To Send Data Set Ready Signal Ground Carrier Detect Data Terminal Ready Ring Indicator

Null Modems Mt Null Modem c s dung ni cho hai DTE cung nhau. Nhng modem nay thng c s dung nh mt cach ni mang cho nhng tro chi hoc chuyn giao gia cac file may tinh s dung giao thc Zmodem Protocol, Xmodem Protocol, ... iu nay cung co th c s dung vi nhiu Microprocessor Development Systems (h thng phat trin b vi x ly).

Trn y la phng phap u tin cua vic ni dy cua mt Null Modem. No chi yu cu 3 dy (TD, RD & SG) mc c xuyn thng qua vi vy anh hng ln n chi phi s dung chay cap dai. Nguyn ly cua thao tac thi n gian co ly. Muc tiu la lam cho may tinh cho rng no la mt modem hn la mt computer khac. Any data transmitted from first computer must be received by second thus TD is connected to RD. iu th hai may tinh phai co cung c cu nh vy thi RD c ni ti TD. Bao hiu rng Signal Ground (SG) cung phai c ni sao cho ca hai grounds ph bin ti mi may tinh. Data Terminal Ready (DTR) lp lai khi chn Data Set Ready (DSR) va Data Carrier Detect (DCD) co mt trn ca hai (on both computers) may tinh. Khi chn Data Terminal Ready mc tich cc thi chn Data Set Ready va chn Data Carrier Detect ngay lp tc tr thanh tich cc (active). Vao thi im nay may tinh cho rng Virtual Modem sn sang c ni va phat hin ra carrier cua modem khac. Va vn cn lo lng by gi la chn Request to Send va chn Clear To Send. Trong khi ca hai may tinh giao thip vi nhau cung mt tc , vi vy vic iu khin lung la khng cn thit vi hai tuyn nay vi chung co th kt ni cung nhau trn mi may tinh. Khi may tinh mun gi d liu, no xac nhn s co mt cua chn Request to Send mc cao va khi o no moc ni vi chn Clear to Send, luc nay ngay lp tc may tinh nhn c cu tra li rng no co th gi d liu va no thc hin ngay. Chu y rng ring indicator se khng kt ni ti bt ky cai gi of each end. ng nay chi s dung chi cho may tinh bit rng co mt ringing signal ang s dung ng dy phone. Trong khi chung ta khng co mt modem kt ni ti ng dy phone thi ng nay c ngng kt ni.

Loopback plug thit bi nay co th tr nn v cung d s dung khi vit nhng chng trinh truyn thng s dung cng ni tip RS232. No co th nhn va truyn nhiu tuyn ng cung nhau, vi th ma moi th c truyn ra ngoai cua cng ni tip thi ngay lp tc nhn c bi cung cng o. Nu chung ta ni thit bi nay vi cng ni tip nap vao Terminal Program, thi bt c cai gi chung ta anh may se ngay lp tc c hin ln trn man hinh (displayed on screen). Xin chu y rng thit bi nay cha c d inh cho vic s dung vi nhng chng trinh Chn oan (Diagnostic Programs) va se co le khng lam vic. Bi vi nhng chng trinh ma chung ta yu cu khac nhau se bao cho Loop Back plug cai ma co th thay i t chng trinh nay n chng trinh khac. Tc DTE / DCE Chung ta a noi tom tt v DTE va DCE. Mt thit bi u cui d liu (Data Terminal Device) tiu biu la mt may tinh va mt thit bi truyn thng d liu (Data Communications Device) tiu biu la mt Modem. Ngi ta thng nhc n tc cua DTE to DCE hoc DCE to DCE. DTE to DCE la tc gia modem va may tinh cua chung ta, i khi c cp n nh la tc cua thit cui cua chung ta. DTE to DCE cn phai chay mt tc nhanh hn tc cua DCE to DCE. DCE to DCE la s kt ni gia cac modem, i khi c goi la tc line speed. Hu ht moi ngi ngay nay co nhng modem vi tc 28,8K hoc 33,6K. Bi vy chung ta cn phai ch i tc cua DCE to DCE cung nh tc cua modem la 28,8K hoc 33,6K. Suy cho cung vi tc cao cua modem nn chung ta mong mun tc cua DTE to DCE se at n khoang 115,200 BPS (Maximum Speed of 16550a UART). Nhng chng trinh truyn thng ma chung ta s dung a t tc cho DCE to DTE. Tuy nhin, chung chi co tc 9,6 KBPS, 14,4 KBPS ... va coi nh no la tc modem cua chung ta. Nhng modem ngay nay co th nen d liu vao trong chung (Data Compression). iu nay cung nh rt nhiu PK-ZIP nhng phn mm trong modem cua chung ta co th nen va giai nen d liu. Khi a ra ung cach thc chung ta co th mong i vic nen s truyn vi ty l 1:4 hoc thm chi con cao hn. Ty l nen d liu 1:4 la rt tiu biu cho vic nen d liu cua nhng file vn ban. Nu chung ta chuyn nhng file vn ban o 28,8K (DCE-DCE), thi khi modem nen no chung ta thc s ang chuyn 115,2 KBPS gia nhng computers va nh vy tc cua DCEDTE la 115,2 KBPS. Nh vy do la ly do tai sao tc cua DCE-DTE cn phai cao hn tc kt ni cua modem. Vai nha san xut modem a trich dn mt ty l nen cc ai la 1:8. lam vi du cho li trich dn o ho a ra mt modem mi vi tc 33,6 KBPS khi o chung ta co th co mt s chuyn i cc ai 268,800 BPS gia modem and UART. Nu chung ta chi co a 16550a nhng chung ta co th lam 115,200 BPS tops, then you would be missing out on a extra bit of performance. Buying a 16C650 should fix your problem with a maximum transfer rate of 230,400 BPS. Tuy nhin, hay khoan lam dung modem cua chung ta nu chung ta khng co nhng tc mong mun.o la nhng ty l nen cc ai. Trong vai trng hp ca bit nu chung ta c gng gi cho mt file nen, modem cua chung ta co th mt nhiu thi gian hn nen no, vi vy chung ta co tc truyn chm hn tc kt ni cua modem. Nu iu nay xay chung ta nn c gng tt vic nen d liu cua chung ta lai. Luc nay cn phai c inh trn nhng modem mi hn. Mt vai file nen d dang hn nhng file khac vi vy bt ky file nao ma nen n gian thi t nhin se co mt ty l nen cao hn. iu khin Lung (Flow Control)

Nh vy nu tc cua DTE to DCE la nhanh hn gp vai ln tc cua DCE to DTE PC co th gi d liu ti modem cua chung ta tai 115,200BPS. Sm hay mun d liu se bi mt khi b m bi tran, trng hp nay iu khin lung se c s dung. iu khin lung co hai dang c ban, phn cng (hardware) hoc phn mm (software). iu khin lung phn mm (Software flow control), i khi c biu thi nh Xon/Xoff s dung hai dang ky t Xon va Xoff. Xon thng cho bit bi nhng ky t cua ASCII 17 trong khi o ky t ASCII 19 c s dung cho Xoff. Nhng modem chi co mt b m nh vi th khi may tinh phu y no, Modem gi mt ky t Xoff bao cho may tinh dng cng vic gi d liu. Khi modem co phong cho nhiu d liu hn, no gi mt ky t Xon va may tinh se gi nhiu d liu hn. Kiu iu khin lung th nay co nhiu li th rng no khng yu cu bt ky thng ip nao nh nhng ky t c gi qua nhng ng TD/RD. Tuy nhin mi ky t yu cu lin kt chm mt 10 bits iu o co th lam chm vic truyn thng lai. iu khin lung phn cng (Hardware flow control) cung c bit nh iu khin lung RTS/CTS flow control. No s dung hai dy trong cap ni tip cua chung ta hn la truyn thm nhng ky t trong ng d liu cua chung ta. iu khin lung Phn cng cung c bit nh iu khin lung RTS / CTS. Vi vy iu khin lung phn cng (hardware flow control) se khng lam chm vic truyn thng lai nh vic s dung Xon-Xoff does. Khi may tinh mun gi d liu no se iu khin hoat ng cua ng Request to Send. Nu modem co phong cho d liu nay, thi modem se bng vic iu khin hoat ng cua ng Clear to Send va may tinh bt u gi d liu. Nu modem khng co phong thi no se khng gi tin hiu cho Clear to Send. UART (8250 and Compatibles) UART - Stands for Universal Asynchronous Receiver/Transmitter. a s cac card se co UART's tich hp vao trong nhng mach in t chip khac ma cung co th iu khin cng song song cua chung ta, cng games, floppy hoc ia cng (hard disk drives) va tiu biu la nhng thit bi surface mount. 8250 series, bao gm 16450, 16550, 16650, & 16750 UARTS la nhng kiu thng thy trn PC cua chung ta.

16550 la chip tng thich vi 8250 & 16450. Chi khac hai chn 24 va 29. Chn 24 trn 8250 la vic la chon chip ngoai ma chc nng chi la vic chi bao ti nu chip hot ng hoc khng. Chn 29 khng c kt ni trn 8250/16450 UARTs. 16550 a vao hai chn mi trong no. o la Transmit Ready va Receive Ready ma co th thc thi vi DMA (Direct Memory Access).

Nhng chn nay co hai kiu thao tac khac nhau. Mode 0 h tr vic chuyn giao n DMA trong khi mode 1 h tr Multi-transfer DMA. Mode 0 cung c goi la mode 16450. Mode nay c la chon khi b m FIFO c v hiu hoa qua bit 0 cua FIFO Control Register hoc khi b m FIFO c cho phep nhng DMA Mode Select = 0. (Bit 3 cua FCR) Trong mode nay RXRDY la tich cc mc thp khi it nht mt characters (Byte) co mt trong Receiver Buffer. RXRDY se khng hoat ng mc cao khi khng co nhiu characters tn tai trong Receiver Buffer. TXRDY se hoat ng mc thp khi khng co k t trong Transmit Buffer. No se khng hoat ng mc cao sau khi characters/byte u tin c tai vao trong Transmit Buffer. Mode 1 la khi b m FIFO c kich hoat va DMA Mode Select = 1. Trong mode 1, RXRDY se hoat ng mc thp khi trigger level la reached hoc khi 16550 Time Out xay ra va se quay tr lai trang thai khng hoat ng khi khng co characters trong FIFO. TXRDY se c kich hoat khi khng co characters co mt bn trong Transmit Buffer va se khng c kich hoat khi FIFO Transmit Buffer la hoan toan Full. Chn Chn 1:8 Chn 9 Chn 10 Chn 11 Chn 12 Chn 13 Chn 14 Chn 15 Chn 16 Chn 17 Chn 18 Chn 19 Chn 20 Chn 21 Chn 22 Chn 23 Chn 24 Chn 25 Chn 26 Tn D0:D7 RCLK RD TD CS0 CS1 nCS2 nBAUDOUT XIN XOUT nWR WR VSS RD nRD DDIS nTXRDY nADS A2 Data Bus Receiver Clock Input. Tn s u vao nay cn phai cn bng vi receivers baud rate * 16 Nhn d liu (Receive Data) Truyn d liu (Transmit Data) Chip Select 0 - Active High Chip Select 1 - Active High Chip Select 2 - Active Low Baud Output - Output from Programmable Baud Rate Generator. Frequency = (Baud Rate x 16) u vao External Crystal Input S dung cho Baud Rate Generator Oscillator u ra External Crystal Output Write Line Inverted (ao) Write Line - Not Inverted (khng ao) Kt ni ti Common Ground Read Line - Inverted Read Line - Not Inverted V hiu hoa b phn iu khin (Driver Disable). Chn nay ri vao mc thp khi CPU oc t UART. Co th kt ni ti Bus Transceiver trong trng hp bus d liu co dung lng cao. Transmit Ready Xung ia chi (Address Strobe). S dung nu tin hiu khng n inh trong sut qua trinh oc hoc ghi cycle Address Bit 2 M t

Chn Chn 27 Chn 28 Chn 29 Chn 30 Chn 31 Chn 32 Chn 33 Chn 34 Chn 35 Chn 36 Chn 37 Chn 38 Chn 39 Chn 40

Tn A1 A0 nRXRDY INTR nOUT2 nRTS nDTR nOUT1 MR nCTS nDSR nDCD nRI VDD Address Bit 1 Address Bit 0 Receive Ready Interrupt Output User Output 2 Request to Send Data Terminal Ready User Output 1 Master Reset Clear To Send Data Set Ready Data Carrier Detect Ring Indicator + 5 Volts

M t

Tt ca cac chn cua UARTs u thich hp vi TTL. Bao gm TD, RD, RI, DCD, DSR, CTS, DTR va RTS ma tt ca cac giao din trong o la serial plug cua chung ta, typically a D-type connector. Vi vy RS232 Level Converters (ma chung ta se noi cu th sau) a c s dung. Cai nay thng thng la DS1489 Receiver va DS1488 as PC has +12 and -12 volt rails ma co th s dung bi nhng thit bi nay. Trinh chuyn i RS232 se chuyn i tin hiu TTL vao trong RS232 Logic Levels. The UART yu cu mt Clock chay. Nu chung ta xem xet card ni tip cua chung ta a common crystal tim thy cung la a 1.8432 MHZ hoc a 18.432 MHZ Crystal. crystal bn trong c kt ni ti chn XIN-XOUT cua UART s dung thm mt s thanh phn ma giup crystal khi ng oscillating. Clock nay se c s dung cho chng trinh Programmable Baud Rate Generator la nhng giao din trc tip bn trong mach chuyn i thi gian (the transmit timing circuits) nhng khng trc tip bn trong mach receiver thi gian (the receiver timing circuits). i vi vic kt ni ngoai nay c lam t chn 15 (BaudOut) n chn 9 (Receiver clock in). Chu y rng tin hiu clock se tai Baudrate*16. Nu chung ta thc s nghim tuc trong vic nghin cu tim hiu v 16550 UART xuc tin s dung trong PC cua chung ta, thi hay xut vic downloading mt ban sao cua trang tinh d liu PC16550D t National Semiconductors Site. Trang tinh d liu (Data sheets) thi sn co trong dang mu .PDF vi th chung ta se cn Adobe Acrobat Reader oc nhng iu o.Texas Instruments co released 16750 UART ma co 64 Byte FIFO's. Trang tinh d liu cho TL16C750 sn co dung trong Texas Instruments Site. Thanh ghi cua cng ni tip Port Addresses & IRQ's Tn ia chi IRQ

COM 1 COM 2 COM 3 COM 4

3F8 2F8 3E8 2E8

4 3 4 3

Trn la bang standard port addresses. Chung lam vic trong a s cac PC. Nu chung ta tinh c hay may mn s hu mt IBM P/S2 ma co micro-channel bus, thi chung ta mong i mt s thitlp khac cua ia chi va IRQ.Ging nh cng LPT, d liu c s cho cac cng COM co th oc t Vung D liu BIOS (BIOS Data Area). Start Address 0000:0400 0000:0402 0000:0404 0000:0406 Function COM1's Base Address COM2's Base Address COM3's Base Address COM4's Base Address

Trn la bang cho thy ia chi ma chung ta co th tim thy Communications (COM) ports addresses trong BIOS Data Area. Mi ia chi se chim 2 bytes. Chng trinh mu sau vit bng ngn ng C, Hin ra th nao chung ta co th oc nhng vi tri nay thu c nhng ia chi cua cng truyn thng cua chung ta.
#include <stdio.h> #include <dos.h> void main(void) { unsigned int far *ptraddr; /*Pointer to location of Port Addresses */ unsigned int address; /* Address of Port */ int a; ptraddr=(unsigned int far *)0x00000400; for (a = 0; a < 4; a++) { address = *ptraddr; if (address == 0) printf("No port found for COM%d ",a+1); n else printf("Address assigned to COM%d is %Xh",a+1,address); n *ptraddr++; } }

Bng gi tr thanh ghi Base Address DLAB Read/Write Abr. Register Name

=0 +0 =0 =1 +1 +2 +3 +4 +5 +6 +7 =0 =1 -

Write Read Read/Write Read/Write Read/Write Read Write Read/Write Read/Write Read Read Read/Write

IIR

Transmitter Holding Buffer Receiver Buffer Divisor Latch Low Byte Divisor Latch High Byte Interrupt Identification Register

IER Interrupt Enable Register

FCR FIFO Control Register LCR Line Control Register MCR Modem Control Register LSR Line Status Register MSR Modem Status Register Scratch Register

DLAB Chung ta nn chu y trong bang cua Register co ct DLAB. Khi DLAB thit lp 0 hoc 1 se co mt vai thay i cua register. y la ly do tai sao URAT co th co 12 register (bao gm ca thanh ghi scratch) mc du chi co 8 cng ia chi. DLAB thay th cho Divisor Latch Access Bit. Khi DLAB thit lp ti 1qua ng thanh ghi iu khin (control register), hai thanh ghi tr thanh sn co t o chung ta co th t tc truyn thng u n cua chung ta trong bits per second. The UART se co mt crystal ma cn phai dao ng xung quanh 1.8432 MHZ. UART kt hp cht che mt divide bi 16 counter ma n gian divides incoming clock bao hiu bi 16. Gia thit rng chung ta co 1.8432 MHZ clock signal, ma co th cho phep chung ta co mt cc ai, 115,200 hertz bao hiu lam cho URAT tr nn co kha nng truyn va nhn tai 115,200 Bits Per Second (BPS). o tht tuyt vi cho cac modem nhanh hn va cac thit bi ma co th iu khin tc cua no nhanh hn, but others just wouldn't communicate at all. Bi vy UART phu hp vi Programmable Baud Rate Generator ma c iu khin bi hai register. vi du chung ta mun truyn thng tai 2400 BPS. Chung ta lam vic bn ngoai ma phai chia 115,200 bi 48 co th thc hin c 2400 Hertz Clock. "Divisor", trong case 48 nay, c ct gi trong hai registers iu khin bi "Divisor Latch Access Bit". Divisor nay co th la bt ky s nao ma co th ct gi trong 16 bits (ie 0 to 65535). UART chi co mt bus d liu 8 bit, vi vy y la ni hai register c s dung. Register u tin (Base + 0 khi DLAB = 1) ct gi "Divisor latch low byte" trong khi register th hai (base + 1 khi DLAB = 1) ct gi "Divisor latch high byte". Bn di la mt bang mt s tc va Divisor cht cua chung byte thp va byte cao. Chu y rng tt ca cac Divisor u c a vao H 16.

Speed (BPS) Divisor (Dec) 50 300 600 2304 384 192

Divisor Latch High Byte 09h 01h 00h

Divisor Latch Low Byte 00h 80h C0h

2400 4800 9600 19200 38400 57600 115200

48 24 12 6 3 2 1

00h 00h 00h 00h 00h 00h 00h

30h 18h 0Ch 06h 03h 02h 01h

Thanh ghi cho php ngt (IER - Interrupt Enable Register) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes Reserved Reserved Enables Low Power Mode (16750) Enables Sleep Mode (16750) Enable Modem Status Interrupt Enable Receiver Line Status Interrupt Enable Transmitter Holding Register Empty Interrupt Enable Received Data Available Interrupt

IER co th la mt trong nhng register n gian nht va d hiu trn UART. Thit lp bit 0 mc cao cho Received Data Available Interrupt ma tao ra mt ngt khi nhn register/FIFO cha d liu oc bng CPU. Bit 1 cho phep Transmit Holding Register Empty Interrupt. Ngt nay CPU khi b m truyn thng tin trng. Bit 2 cho phep nhn ng ngt trang thai. UART se ngt khi nhn s chuyn i ng trang thai. Tng t nh vy i vi bit 3 thi cho phep ngt modem trang thai. Bit 4 n 7 thi d dang hn. Chung c lu tr n gian (If only everything was that easy).

Thanh ghi nhn dng ngt (IIR - Interrupt Identification Register) Bit Bits 6 and 7 Notes Bit 6 Bit 7 0 0 0 1 No FIFO FIFO Enabled but Unusable

1 Bit 5 Bit 4 Bit 3

FIFO Enabled

64 Byte Fifo Enabled (16750 only) Reserved 0 1 0 Reserved on 8250, 16450 16550 Time-out Interrupt Pending 0 1 0 1 Modem Status Interrupt Transmitter Holding Register Empty Interrupt Received Data Available Interrupt Receiver Line Status Interrupt

Bit 2 Bit 1 Bits 1 and 2 0 1 1 Bit 0 0 1

Interrupt Pending No Interrupt Pending

IIR la thanh ghi chi oc (read only register). Bits 6 va 7 a ra trang thai FIFO Buffer. Khi ca hai bit nay bng 0 thi khng co FIFO buffers c kich hoat. iu nay cn phai la kt qua duy nht chung ta se co 8250 hoc 16450. Nu bit 7 la tich cc nhng bit 6 la khng tich cc thi UART co cho phep b m cua no nhng lai khng th dung c (it's buffers enabled but are unusable). iu nay xay ra trn 16550 UART khi co li trn FIFO buffer lam khng th dung c FIFO. Nu ca hai bit la '1' thi FIFO buffers la tich cc hoan toan co th dung c. Bits 4 va 5 c lu tr. Bit 3 cho thy trang thai cua time-out interrupt trn 16550 or higher cao hn. cho nhay n Bit 0 ma cho thy interrupt xut hin. Nu mt interrupt xut hin trang thai cua no se hin bi bits 1 va 2. Nhng ngt o lam vic trang thai quyn u tin. Line Status Interrupt co quyn u tin cao nht, sau o la Data Available Interrupt, tiip theo la Transmit Register Empty Interrupt va k o la Modem Status Interrupt ma co quyn u tin thp nht. Thanh ghi iu khin FIFO (FCR - First In/First Out Control Register) FCR chi ghi (write only register). Register nay c s dung iu khin FIFO (First In/First Out) buffers ma c tim thy trn 16550 cao hn. Bit 0 cho phep thao tac nhn va truyn cua FIFO. Ghi '0' ti bit nay se v hiu hoa thao tac truyn va nhn cua FIFO, vi vy chung ta phai loose ct tt ca d liu trong FIFO buffers. Bit's 1 va 2 iu khin vic lam sach vic truyn hoc nhn cua FIFO. Bit 1 chiu trach nhim cho b m nhn trong khi bit 2 chiu trach nhim cho b m truyn. Thit lp nhng bit nay ln 1 se chi lam sach ni dung cua FIFO va se khng anh hng n thanh ghi. Hai bit nay se cung c xac lp lai, vi vy chung ta khng cn thit lp bit nay v 0 khi kt thuc. Bit Notes Bit 6 0 1 Interrupt Trigger Level 1 Byte 4 Bytes

Bits 6 and Bit 7 7 0 0

1 1 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved

0 1

8 Bytes 14 Bytes

Enable 64 Byte FIFO (16750 only) DMA Mode Select. Thay i trang thai cua chn RXRDY & TXRDY t mode 1 n mode 2. Clear Transmit FIFO Clear Receive FIFO Enable FIFO's

Bit 3 cho phep DMA la chon mode ma c tim thy trn 16550 UARTs va cao hn. More on this later. Bits 4 va 5 la nhng bit co kiu n gian, d tr. Bits 6 and 7 c s dung thit lp triggering level on Receive FIFO. Vi du nu bit 7 c thit lp nn '1' va bit 6 c thit lp xung '0' thi trigger level se thit lp vi 8 bytes. Khi co 8 bytes cua d liu trong receive FIFO thi ngt Received Data Available c thit lp (See IIR). Thanh ghi iu khin ng truyn LCR - Line Control Register) Thanh ghi iu khin ng truyn thit lp nhng tham s c ban cho vic truyn thng. Bit 7 la Divisor Latch Access Bit hoc DLAB khng tn tai lu (for short). Chung ta a noi v nhng cai gi ma no lam c (See DLAB). Bit 6 thit lp cho phep dng (the Break). Khi tich cc, ng TD i vao trang thai "Spacing" ma nguyn nhn lam dng (the Break) receiving UART. Thit lp bit nay v '0' v hiu hoa Break (Disables Break). Bits 3, 4 and 5 select parity. Nu chung ta nghin cu 3 bit nay, chung ta se thy rng bit 3 iu khin chn le (controls parity). o la, nu no thit lp v '0' thi khng co parity c s dung, nhng nu no thit lp ti '1' thi parity c s dung. Nhay qua ti bit 5, chung ta co th thy rng no iu khin sticky parity. Sticky parity la n gian khi parity bit lun lun truyn va kim tra '1' hoc '0'. Bit nay co rt it thanh cng trong vic kim tra li nh nu 4 bit u tin co li nhng sticky parity bit cha vic thit lp bit thich hp, thi mt parity li se khng cho kt qua. Sticky parity cao la s dung '1' cho parity bit, trong khi opposite, sticky parity thp thi s dung '0' cho parity bit. Nu bit 5 iu khin sticky parity, thi s i hng bit nay khng phai cho kt qua binh thng parity c cung cp bit 3 la se thit lp ln '1'. Odd parity la khi bit parity phat tin hiu '1' hoc '0' vi th ma co odd number of 1's. Even parity must khi o thanh parity bit produces va even number of 1's. Bit 7 1 0 Bit 6 Bits 3, And 5 Divisor Latch Access Bit Truy cp ti Receiver buffer, Transmitter buffer & Interrupt Enable Register

Set Break Enable 4 Bit 5 Bit 4 Bit 3 Parity Select X 0 0 X 0 1 0 1 1 No Parity Odd Parity Even Parity

1 1 Bit 2 0 1

0 1

1 1

High Parity (Sticky) Low Parity (Sticky)

Length of Stop Bit One Stop Bit 2 Stop bits for words of length 6,7 or 8 bits or 1.5 Stop Bits for Word lengths of 5 bits. 0 1 0 1 5 Bits 6 Bits 7 Bits 8 Bits

Bits 0 And 1 Bit 1 Bit 0 Word Length 0 0 1 1

iu nay cung cp s kim tra li tt hn nhng vn khng phai la hoan hao, vi th CRC-32 c s dung thng xuyn cho sa li phn mm. Nu mt bit bi ao vi even parity hoc odd parity, thi mt parity bi li se xay ra, tuy nhin nu hai bit bi lt theo mt cach nao o ma no sinh ra correct parity bit thi vic parity bi li la khng th xay ra. Bit 2 thit lp dai cua nhng stop bits. Vic thit lp nhng bit nay v 0 se em lai mt stop bit, tuy nhin nu thit lp no ln 1 se em lai 1.5 hoc 2 stop bits phu thuc vao word length. Chu y rng receiver chi kim tra stop bit u tin. Bits 0 and 1 thit lp word length. This should be pretty straight forward. Mt word length cua 8 bits thng c s dung ngay nay. Thanh ghi iu khin Modem (MCR - Modem Control Register) The Modem Control Register la mt Read/Write Register. Bits 5,6 va 7 la reserved. Bit 4 kich hoat loopback mode. Trong Loopback mode vic truyn thng ni tip ra ngoai c t vao trong trang thai anh du. receiver serial input c ngng kt ni. Vic truyn ra ngoai c lp lai khi receiver in. DSR, CTS, RI & DCD c ngng kt ni. DTR, RTS, OUT1 & OUT2 c kt ni ti modem control inputs. Nhng chn modem control output c t trong trang thai khng hoat ng. Trong mode nay bt ky d liu nao ma c t trong transmitter registers cho u ra received bi receiver circuitry trn cung mt chip va sn sang tai b m receiver. iu nay co th s dung kim tra thao tac UARTs. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Notes Reserved Reserved Autoflow Control Enabled (16750 only) LoopBack Mode Aux Output 2 Aux Output 1 Force Request to Send

Bit 0

Force Data Terminal Ready

Aux Output 2 co th kt ni ti external circuitry iu khin ngt x ly UART-CPU. Aux Output 1 thng thng c ngng kt ni, nhng trn nhiu card c s dung chuyn i gia 1,8432MHZ crystal to a 4MHZ crystal c s dung cho MIDI. Bits 0 and 1 n gian iu khin nhng ng d liu thich hp cua chung. Vi du v vic thit lp bit 1 ln '1' lam yu cu gi line active. Thanh ghi trng thi ng truyn LSR - Line Status Register) The line status register la thanh ghi chi oc. Bit 7 la bit error in received FIFO bit. Bit nay la bit cao khi co it nht mt li break, parity hoc framing xay ra trn mt byte ma c cha trong FIFO. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes Error in Received FIFO Empty Data Holding Registers Empty Transmitter Holding Register Break Interrupt Framing Error Parity Error Overrun Error Data Ready

Khi bit 6 c thit lp, thi ca hai thanh ghi transmitter holding register va thanh ghi shift register trng. Thanh ghi UART's holding gi byte tip theo cua d liu se c gi n parallel fashion. Thanh ghi dich chuyn (shift register) c s dung chuyn i byte ni tip, vi th ma no cot th truyn trn mt ng. Khi bit 5 c thit lp, thi chi thanh ghi transmitter holding register trng. Vi th s khac nhau gia hai bit o la gi? Khi bit 6 c thit lp, thi thanh ghi transmitter holding va thanh ghi shift registers trng, khng co qua trinh chuyn i ni tip nao xay ra vi th phai khng co qua trinh hoat ng nao trn ng truyn d liu. Khi bit 5 c thit lp, thi thanh ghi transmitter holding register trng, vi th nhng byte khac co th dc gi n cng d liu, nhng vic chuyn i ni tip ang s dung thanh ghi dich chuyn (shift register) co th chim ch. The break interrupt (Bit 4) xay ra khi ng d liu a nhn c gi trong trang thai lgic '0' (Space) cho khoang thi gian hn thi gian no dung n khi gi mt word y u. Thi gian o bao gm ca thi gian cho start bit, data bits, parity bits and stop bits. A framing error (Bit 3) xay ra khi bit cui cung khng phai la stop bit. iu nay xay ra vi mt li tinh toan thi gian. Thng thng chung ta se gp phai mt li framing error khi s dung mt null modem lin kt hai may tinh hoc protocol analyzer when speed at which data is being sent is different to that of what chung ta phai thit lp UART nhn no. A overrun error thng thng xay ra khi chng trinh cua chung ta khng th oc t cng u nhanh. Nu chung ta khng co mt byte u vao ngoai cua thanh ghi u nhanh (register fast enough), va byte khac nhn, thi byte cui cung se bi mt va mt li tran se xay ra.

Bit 0 cho thy data ready, co nghia la mt byte c nhn bi UART va b m sn sang oc. Thanh ghi trng thi Modem MSR - Modem Status Register) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes Carrier Detect Ring Indicator Data Set Ready Clear To Send Delta Data Carrier Detect Trailing Edge Ring Indicator Delta Data Set Ready Delta Clear to Send

Bit 0 cua modem status register cho thy delta clear to send, delta co nghia la mt s thay i bn trong, vi vy delta clear to send nghia la co mt s thay i bn trong ng clear to send, t ln oc cui cung cua thanh ghi nay. iu nay cung ung vi cac bits 1 va 3. Bit 1 cho thy s thay i bn trong ng Data Set Ready trong khi Bit 3 cho thy mt s thay i bn trong ng Data Carrier Detect. Bit 2 la Trailing Edge Ring Indicator chi bao rng co mt s bin i t trang thai thp n trang thai cao trn ng Ring Indicator. Bits 4 n bit 7 cho thy trang thai hin thi cua cac ng d liu khi oc. Bit 7 cho thy Carrier Detect, Bit 6 cho thy Ring Indicator, Bit 5 cho thy Data Set Ready & Bit 4 cho thycac trang thai cua ng Clear To Send. Scratch Register The scratch register khng s dung cho truyn thng nhng c s dung nh mt ni lu mt byte cua d liu. Vic s dung thc t cua no la xac inh UART la 8250/8250B hoc a 8250A/16450 va thm chi cai o khng phai la chinh thc nh 8250/8250B khng bao gi c thit k cho AT va khng th hack bus speed. n tp: Cu 1 : Phn tch , so snh phng php trao i ng b v khng ng b. Cu 2 : Thit k mch v chng trnh cho php trao i d liu gia 2 my tnh thng qua mch giao tip RS232. Cu 3: Thit k chng trnh thit lp cc thng s c bn cho cng COM.