Interrupt Handling

Problem Definition: • The processor has to energize a relay coil for one second whenever switch SW is pressed. • During the said period of one second, all switch presses will be ignored. • After every system reset, the relay coil should be de-energized. Solution • RST7.5 interrupt input is used to read the switch output. • SOD line is used to drive the transistor (in CE configuration) whose collector load is the relay coil.

Interrupt Handling

Interrupt Handling
Assembly Language Program

ORG 0000H JMP 0060H
ORG 003CH MVI A,0C0H SIM CALL DELAY MVI A,50H SIM MVI A,00H SIM EI

RET
ORG 0060H LXI SP,0F000H MVI A,5BH SIM MVI A,00H SIM EI L1: JMP L1 HLT DELAY: NOP RET

Interrupt Handling
Problem Definition: • To plan for an external latch circuitry that will hold an interrupt request at RST5.5 input. • To implement a setup to clear the latch output after the processor acknowledges the interrupt input. • After every system reset, clear the latch. Solution • Use a D-type latch with the interrupting source driving the CLK input. • Use the SOD line to drive the CLR input of the latch.

Interrupt Handling

Interrupt Handling
Assembly Language Program ORG 0000H JMP 0040H ORG 0040H LXI SP,0F000H MVI A,0C0H SIM MVI A,40H SIM MVI A,4EH SIM EI L1: JMP L1 HLT EI RET

ORG 002CH <ISR> MVI A,0C0H SIM MVI A,40H SIM

Memory Interface
The 8085 board uses a 32 kB PROM (27C256) and a 32 kB SRAM (62C256) and the memory map is as follows:

PROM (0000H – 7FFFH)
Start Address: 0000|0000|0000|0000 End Address: 0111|1111|1111|1111 SRAM (8000H – FFFFH) Start Address: 1000|0000|0000|0000 End Address: 1111|1111|1111|1111

Memory Interface

82C55A Interface
The 8085 board uses two 82C55A chips for interfacing with standard peripherals. The address map for the devices are as follows:

82C55A(#2)
Port A: F8H (1111|1000) Port B: F9H (1111|1001) Port C: FAH (1111|1010) CWR: FBH (1111|1011)

82C55A(#1)
Port A: FCH (1111|1100) Port B: FDH (1111|1101) Port C: FEH (1111|1110) CWR: FFH (1111|1111)

82C55A Interface

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