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Burst mode is most useful when the 80486 is filling its internal cache memory from the system

memory. The cache is updated each time the microprocessor performs a memory read (I/O read operations are not recorded in the cache). When the 80486 performs a memory read operation, it first checks the cache to see whether the requested data is there. If the data in the cache, no memory is read (and, therefore, no external bus access is required). This make for a very fast read operation However, if the data is not in the cache, the 80486 reads the actual memory location and then places the data in the cache.

Conversely, all 80846 memory-write operations are performed at the system memory, even if the data already in the cache. If the bus is busy when the 80486 needs to write data to memory, it can store the data in one of its four onboard write registers. The enables the microprocessor to continue processing internally and wait for a convenient inside the 80486, but unlike memory-write buffering, multiple IO writes must be written to memory before other internal processing can continue

The 80486’s internal cache controller monitor system’s address bus when other processors or bus masters gain control of bus system. The reason for this in to keep track of addresses where new data may be written into memory, but not into the cache. BY keeping tracks of these address locations, the cache controller can update the cache as soon as the 80486 regains control of the buses. Many manufacturers of 80486-based systems opt to include additional external cache memories on their systems boards.

In these systems, the 80486’s internal cache memory is referred to as the first-level cache, and the external cache is called the second-level cache, or L2 cache. Secondary caches are normally 128KB or 256KB.

When the 80486 writes data into memory, it generates a parity bit for each byte. As in other systems, the parity bit is stored in system RAM along with the data. When the data is read from memory, the parity bit is also read. If an error condition is detected by the 80486, the microprocessor activities is PCHK output line to notify the system. It is the responsibility of the system’s decision circuitry to handle the error condition. The 80486’s parity check circuitry checks only information retrieved from RAM, not internally generated data.