Draft notes or 22C: 040

Simplification of Boolean functions
Using the theorems of Boolean Algebra, the algebraic forms of functions can often be simplified, which leads to simpler (and cheaper) implementations.

Example 1

F

= = = =

A.B + A.B + B.C A. (B + B) + B.C A.1 + B.C A + B.C How many gates do you save from this simplification?

A

A

B B F C

F

C

2

B.C A.B.C + A.B. (1 + B) A.A + A.B.B.A + (C + C).B.B.C + A.C + A.B A.B Example 3 Show that A + A.C + C.B.Draft notes or 22C: 040 Example 2 F = = = = = A. C.C) + (A.C + A.C + (B + B).C + A.B.B.B.1 + A.C) + (A.C + A.B. B. A.B.B.C (A.B.B = A A + AB = = = = A.C + A.B B.C) (A + A).C + A.C + A.C + A.C + A. 1 A 3 .B.

Several examples will be worked out in the class. 4 .Draft notes or 22C: 040 Simplification using Karnaugh Maps A B 1 0 0 0 1 1 1 1 K-map of 2-variable OR function BC A 0 1 1 00 01 11 1 1 1 K-map of majority function 10 Follow the class lectures to understand how to simplify Boolean functions using K-maps.

A B A + B = A.Draft notes or 22C: 040 Other types of gates A A.B Exclusive OR (XOR) gate 5 .B + A.B B A B A+B NAND gate NOR gate Be familiar with the truth tables of these gates.

then we prove our point. OR and NOT gates. So if AND. How can we prove this? (Proof for NAND gates) Any boolean function can be implemented using AND. 1.Draft notes or 22C: 040 NAND and NOR are universal gates Any function can be implemented using only NAND or only NOR gates. Implement NOT using NAND A A 6 . OR and NOT gates can be implemented using NAND gates only.

B = A+B B B (Exercise) Prove that NOR is a universal gate.Draft notes or 22C: 040 2. 7 . Implementation of OR using NAND A A A. Implementation of AND using NAND A B A.B A 1.

OR and NOT gates to a version that uses NAND (or NOR gates only)? Additional properties of XOR XOR is also called modulo-2 addition. Why? A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F 0 1 1 0 1 0 0 1 A B = 1 only when there are an odd number of 1’s in (A.B).Draft notes or 22C: 040 Example (to be worked out in class) How to convert any circuit that uses AND. The same is true for A B C also. 1 0 A=A A=A Why? 8 .

Draft notes or 22C: 040 Logic Design Exercise Half Adder A A B Half Adder B 0 1 0 1 S 0 1 1 0 C 0 0 0 1 Sum (S) Carry (C) 0 0 1 S=A C = A.B B 1 A S B C 9 .

Cin + A. 10 .Cin How can you add two 32-bit numbers? It will be discussed in the class.Draft notes or 22C: 040 Full Adder Sum (S) A B Cin Full Adder Carry (Cout) A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 S 0 1 1 0 1 0 0 1 Cout 0 0 0 1 0 1 1 1 S=A B Cin Cout = A.B + B.

Examples are adders. but also on their past values. and all the circuits that we have studied so far Sequential circuits. We will study sequential circuits later. The output depends only on the current values of the inputs and not on the past values. 11 . Sequential Circuits Combinational circuits. subtractors. The output depends not only on the current values of the inputs. These hold the secret of how to memorize information.Draft notes or 22C: 040 Combinational vs.

n Enable D0 A B D1 D2 D3 A 0 0 1 1 B 0 1 0 1 D3 D2 D1 0 0 0 1 0 0 1 0 0 1 0 0 D0 1 0 0 0 A 2-to-4 decoder and its truth table.B D0 = A. When Enable = 0. Exercise.Draft notes or 22C: 040 Decoders A typical decoder has n inputs and 2 outputs.B D2 = A. all the outputs are 0. The decoder works per specs when (Enable = 1).B D1 = A.B Draw the circuit of this decoder. D3 = A. Design a 3-to-8 decoder. 12 .

A = D1 + D3 B = D2 + D3 13 . n D0 D1 D0 D1 D2 D3 A B 1 0 0 0 0 1 0 0 D2 D3 A 0 0 1 0 0 0 0 1 0 0 1 1 B 0 1 0 1 A 4-to-2 encoder and its truth table.Draft notes or 22C: 040 Encoders A typical encoder has 2 inputs and n outputs.

Design a 4-to-1 mux. A B 0 1 F S = 0. F = A S = 1. also called a selector. A + S.Draft notes or 22C: 040 Multiplexor It is a many-to-one switch. B Exercise. 14 . F = B Control S Specifications of the mux A 2-to-1 mux F = S.

15 . Design a 4-to-1 multiplexor using 2-1 multiplexors only. Design a 2-to-4 decoder using 1-to-2 decoders only.Draft notes or 22C: 040 Another design of a decoder A B C D D0 D1 D2 D3 2-to-4 decoder F S Exercise 1. To be discussed in the class. Exercise 2.

and its specification. Y = B A 1 S A 1-to-2 demux. A. So. We will discuss the design of a 1-bit ALU in class. 16 .Draft notes or 22C: 040 Demultiplexors A demux is a one-to-many switch. B Exercise. and Y = S. Design a 1-4 demux. X = A S = 1. X = S. 0 X Y S = 0.

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