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Software embedded into the system: Software is like the brain of the system Processor in embedded system executes software for a specific application Instruction codes and data are placed in the ROM or flash memory Software is called ROM image ROM image in a system memory is shown below:

Image consists boot-up program, stacks address pointers, program counter address pointers, application programs, ISRs, RTOS, input data and vector addresses

Coding of software in machine codes: During coding, programmer defines the addresses and corresponding bytes or bits at each addresses Machine code based coding Time consuming method Programmer must understand processor instruction and their machine codes Software in processor specific assembly language: Program or a small specific part can be coded in assembly language using assembler Assembler is software used for developing codes in assembly Needed for Invoking Processor Specific Instructions Requires understanding of the processor and instruction set. A program or a small specific part coded in the assembly language using an Assembler (software used for developing codes in assembly).
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Three steps when using assembly language before finally burned at the ROM: 1. 'Assembler', 2. 'Linker' and 3. 'Locator' Conversion Process for Assembly to ROM image:

Assembler translates assembly language to machine codes Linker links the machine codes with other required codes like standard code for delay from library. Loader performs reallocating the codes after finding the physical memory addresses available Reallocated codes are located as ROM image and permanently placed at the addresses available in ROM Device programmer takes the ROM image file and burns the image into the PROM or flash

Software in high level language: Time consumption can be reduced by developing software in high-level language like C, C++, VC++ or Java Need only to understand hardware organization Different programming layers in typical embedded C software is shown below:

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Process of converting a C program into ROM image is shown below:

A compiler generates the object codes and assembles the codes according to the processor instruction set and other specifications C compiler for embedded system uses a code optimizer that optimize before linking.

Software tools for designing embedded system:

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I/O Devices - Device I/O Types and Examples: Serial and parallel IO devices: a) Synchronous Serial IO Each bit in a byte is txed or rxed in synchronization Txn by a constant time period T, for a byte 8T is required Serial CLK and serial data IO lines are required If same line is used for clock and data, either encoding or modulation technique is used Different modes: Master Output slave Input (MOSI) and Master Input Slave Output (MISO) Used for inter-processor transfer, audio IO and streaming data, read/write operation in optical disk etc. b) Asynchronous serial IO Txd and RxD lines are used for data txn and rxn Bytes are txt by variable intervals Require start and stop bits between each byte Around 10T or 11T periods are required for txn and rxn of a byte Uses UART protocol Used in keypad, modem, printer, mouse etc c) Parallel port One or multibit input or output and are bidirectional IO Short distances, generally within a circuit board or IC or nearby external devices High data transfer rate More number of wires Capacitive effect in parallel wires reduces the length up to which communication in parallel can take place. Parallel port interfacings for keypad, LCD display and modem is shown below:

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Synchronous communication and Iso-synchronous communication: In synchronous a byte or frame of data is txed or rxed at constant time intervals with uniform phase differences Iso-synchronous communication is special case, where maximum time interval can be varied Example for synchronous serial communication is frame sent over a LAN, interprocessor communication in a multi-processor system Synchronous device port bits and the functions are: 1. Synch code bits or frame start and end signaling bits (optional): Few bits separated by a time interval as synch code for frame synchronization. Some cases flag bits are used for synchronization 2. Data bits (compulsory): m frame bits or 8 bits transmit, such that each bit is at the line for time T or each frame is at the line for time mT 3. Clock bits (mostly not optional): Either a separate clock line or a single line such that the clock information is also embedded with the data bits by an appropriate encoding or modulation Two characteristics of synchronous communications are: 1. Bytes maintain a constant phase difference; does not provide handshaking during the communication interval 2. A clock timing at a certain rate must always there to serially transmit the bits of all bytes. Methods of synchronous signals:

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Asynchronous Communications: Byte or frame is txed or rxed at variable time intervals Examples are voice data transmission over telephone line, keypad communication, RS232C communication between the UART devices etc. Two characteristics of asynchronous communication are: 1. Bytes need not maintain a constant phase differences; need handshaking between txr and rxr. 2. A clock must tick at a certain rate to transmit bits of a single byte serially An example with serial communication in asynchronous mode is shown below:

DTE: PC, DCE: Modem DCD- Data carrier detect DSR- Data set ready DTR- Data terminal ready RTS- Request to send CTS- Clear to send TxD- Transmit data RxD- Receive data Bits and its functions:

Protocols and its applications using synchronous and asynchronous serial port devices: A protocol is a standard adopted, which tells the way in which the bits of a frame must be sent from a device (or controller or port or processor) to another device or system. A protocol defines how are the framebits: 1) sent synchronously or Iso-synchronously or asynchronously and at what rate(s)?
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2) Preceded by the header bits? 3) How can the transmitting device address defined so that receiving device comes to know the source when receiving data from several sources? 4) How the frame-length defined so that receiving device knows the frame-size in advance? 5) Frame-content specifications Are the sent frame bits specify the controller device configuring or command or data? 6) Are there succeeding to frame the trailing bits so that receiving device can check the errors, if any in reception before it detects end of the frame ? 7) Frame bits minimum and maximum length permitted per frame 8) Line supply and impedances and line-Connectors specifications Some Protocols are: 1. HDLC, Frame Relay (for synchronous communication) 2. RS232C, UART, X.25, ATM, DSL and ADSL (for asynchronous transmission) 3. Ethernet and token ring protocols used in LAN Networks (for networking the physical devices in telecommunication and computer networks) Some Protocols in embedded network devices 1. Internet appliances application protocols and Web protocols HTTP (hyper text transfer protocol), HTTPS (hyper text transfer protocol Secure Socket Layer), SMTP (Simple Mail Transfer Protocol), POP3 (Post office Protocol version 3), ESMTP (Extended SMTP) (for Bridges and routers) 2. File transfer, Boot Protocols in embedded devices network TELNET (Tele network), FTP (file transfer protocol), DNS (domain network server), IMAP 4 (Internet Message Exchange Application Protocol) and Bootp (Bootstrap protocol). 3. Wireless Protocols in embedded devices network Embedded wireless appliances uses wireless protocols WLAN 802.11, 802.16, Bluetooth, ZigBee, WiFi, WiMax RS232C/RS485 Communication: Protocol used between DTE COM port and DCE COM port is UART Handshaking signals

Rxr end voltage level is from -3 to -25V for logic 1and +3 to +25V for logic 0, Txr end voltage level is -5 to -15V for logic 1 and _5 to +15V for logic 0. General baud rates are 300, 600,1200, 4800 and 9600 bps Transmission rate is 115.2kbps up to 0.25m and 38.4kbps up to 1m
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RS485 now called EIA-485, is a protocol for physical layer in case two wire full or half duplex serial connection between multiple points Transmission in RS485 is at 35Mbps up to 10m and 100kbps up to 1.2km Signals are between +12V and -7V, where logic 1 is +ve and 0 is reverse polarity UART: Protocol used with RS232C port UART mode is as follows: 1. A line is NRZ state 2. Start of serial bits is signaled by 1 to 0 transition (negative edge) for a period equal to reciprocal of baud rate 3. When sending a byte consists of a start bit, 8 data bit, optional parity bit and stop bit, each during the interval T, thus require 10T or 11T for a byte transmission 4. Data bits in certain cases can be 5 or 6or 7 instead of 8 5. Stop bit can be minimum interval of 1.5T or 2T instead of T in specific cases 6. Parity bit is used for parity detection or error detection UART 16550 includes a 16-byte FIFO buffer used commonly in IBM PC COM port UART communication can be full duplex or half duplex HDLC protocol: High Level Data Link Control is an International Standard protocol for a data link network used for synchronous serial data communication between physical devices on a network Used for linking data from point to point and multiple points Some applications are telecommunication and computer networks Bit-oriented protocol, the total number of bits is not necessarily an integer multiple of byte or a 32-bit integer Full duplex communication Network device port bits in an HDLC frame format and protocol are:

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Sophisticated interfacing features in Devices/Ports: 1. Operation voltage level expected for logic 1 is 5V and logic 0 is 0V. In built Schmitt trigger or external chip for Schmitt trigger provide noise elimination to get the logic level from the different voltage levels 2. The ports have power management. A new technology called Data Gate, in which programmable ON/OFF switch is used for power management. The port is active only when input or output signals are passed to the port. 3. Low voltage operations are there. LVTTL, LVCMOS gates are used at the device ports for 1.5V IO. HSTL and Stub-series Terminated Logic (SSTL) standards are used for high-speed operations 4. Device and bus-impedances during IO should match, else line reflection may occur 5. IO device may consist multiple gigabit (622Mbps to 3.125Gbps) transceivers 6. A device for an IO may integrate a SerDes (Serialization and De-serialization) subunit 7. Multiple IO standards for IO devices 8. IO device may integrate a digital Physical Coding Sublayer 9. IO device may integrate an analog unit Physical Media attachment

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Timer and Counting Devices: Timer: Timer is a device, which counts the input at regular interval (T) using clock pulses at its input. Has an input pin (or a control bit in control register) for resetting it for all count bits = 0s. Has an output pin (or a status bit in status register) for output when all count bits = 0s after reaching the maximum value, which also means after timeout or overflow. Counter: The counts increment on each pulse and store in a register, called count register Output bits (in a counter register or at the output pins) for the present counts. The counts multiplied by the interval T give the time. The (present counts initial counts) T interval gives the time interval between two instances when present count bits are read and initial counts were read or set. A device, which counts the input due to the events at irregular or regular intervals. The count gives the number of input events or pulses since it was last read. Has a register to enable read of present counts Functions as timer when counting regular interval clock pulses Has an input pin (or a control bit in control register) for resetting it for all count bits = 0s. Has an output pin (or a status bit in status register) for output when all count bits = 0s after reaching the maximum value, which also means after timeout or overflow. Timer or Counter Interrupt: When a timer or counter becomes 0x00or 0x0000 after 0xFF or 0xFFFF(maximum value), it can generate an interrupt, or an output Time-Out or set a status bit TOV Blind counting: Free running counter device with a pre-scalar for clock input Useful to alarm or processor interrupts at preset instances or after preset intervals with respect to another event from another source. Uses of Timer Device: 1. Real Time Clock 2. Initiating an event after a preset delay time 3. Initiating an event after a comparison between the preset time with counted value 4. Capturing the count-value at the timer on an event 5. Finding the time interval between two events 6. Wait for a message from a queue or semaphore for a preset time when using an RTOS 7. Watch dog timer 8. Baud rate for serial communication 9. Input pulse counting 10. Scheduling of various tasks 11. Time slicing of various tasks 12. Time division multiplexing
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States of timer: 1. Reset state 2. Initial load state 3. Present state 4. Overflow state 5. Overrun state 6. Running or stop state 7. Finished state 8. Reset enabled/disabled state 9. Load enabled/disable state 10. Auto reload enabled/disabled state 11. Service routine execution enable/disable state A hardware timer control and status signals are shown below:

Control signals: Timer enable, Timer start, Timer stop, Pre-scaling bits, Up-count enable, Down-count enable, Load enable, Timer interrupt enable, Time-out enable Status flag corresponding to time-out enable Forms of timer: 1. Hardware internal timer 2. Software timer (SWT) 3. User software controlled hardware timer 4. RTOS controlled hardware timer 5. Timer with periodic time-out events (auto reloading after overflow) 6. One shot timer 7. Up count action timer 8. Down count action timer
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9. Timer with its overflow status bit, which auto resets after ISR starts running 10. Timer with its overflow status bit, which does not auto reset A software timer control and status flags are:

Serial Bus Communication Protocol

Common types:

Inter IC (I C) Bus
2

Controller Area Network (CAN) Bus Universal Serial Bus (USB)

I2C Bus Different ICs can be interconnected by network using I2C bus Three standards: 1) Industrial 100kbps I2C 2) 100kbps SM I2C
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3) 400kbps I2C Developed by Philips Semiconductors Two line bus: one for serial clock (SCLK) and other is for bidirectional serial data (SDA) I2C signals during data transfer is shown below:

I2C bus protocol:

1. Start bit 2. 7 bit address of slave from master 3. R/W bit 4. Acknowledgement bit 5. 8 bit data 6. Negative Acknowledgement from master 7. Stop bit I2C bus signals

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Disadvantages: 1. Master device take long time to analyze the slave device hardware support or not 2. Less number of ICs have this protocol 3. Pull-up resistor is needed for master

CAN Bus: Distributed Control Area Network Example - a network of embedded systems in automobile, medical electronics, industrial plant controllers etc. Three standards: 1. 33kbps CAN 2. 110kbps Fault Tolerant CAN 3. 1Mbps High Speed CAN

Has a bidirectional serial line Have multi-master and multi-cast features Employs a twisted pair of maximum length 40m connection of 120 line impedance at each CAN controller A fundamental CAN characteristic is the opposite logic state between the bus, and the driver input and receiver output Normally, a logic-high is associated with a one, and a logic-low is associated with a zero, but not so on a CAN bus

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Line at logic 1 is called Recessive state (differential voltage is 0) Line at logic 0 is called Dominant state (differential voltage is high voltage) Each node has a current driver b/w output and serial line, node sends a logic 0 to line in its D-state Each node also has a buffer to receive logic from serial line

CAN Protocol: Standard CAN

1. SOF The single dominant start of frame (SOF) bit marks the start of a message, and is used to synchronize the nodes on a bus after being idle. 2. Identifier-The Standard CAN 11-bit identifier (address of destination device) establishes the priority of the message. Lower the binary value, the higher its priority. 3. RTR The single Remote Transmission Request (RTR) bit is dominant when information is required from another node. If RTR is 1, the packet is for device at destination address, else the packet is a request for the data from the device 4. IDE A dominant single identifier extension (IDE) bit means that a standard CAN identifier with no extension is being transmitted. 5. r0 Reserved bit
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6. DLC The 4-bit data length code (DLC) contains the number of bytes of data being transmitted. 7. Data Up to 64 bits of application data may be transmitted. 8. CRC The 16-bit (15 bits plus delimiter) cyclic redundancy check (CRC) contains the checksum (number of bits transmitted) of the preceding application data for error detection. 9. ACK Two bits, and first is ACK slot. The sender send it as 1 and rxr send back 0 when it detects error. Second bit is delimiter, it signals the end of ACK field 10. EOF This end-of-frame (EOF), 7-bit field marks the end of a CAN frame (message) and disables bit-stuffing, indicating a stuffing error 11. IFS This 7-bit inter frame space (IFS) contains the time required by the controller to move a correctly received frame to its proper position in a message buffer area. USB: Bus b/w host system and number of interconnected peripherals Maximum 127 devices can connect to a host Serial txn and rxn b/w host and serial devices at a rate ranges from 1.5Mbps to 480Mbps USB host includes controller for the function as bus master can connect flash, digital cameras, printer, mice, PocketPC, video games etc Three standards: 1. USB 1.1 (a low speed 1.5Mbps 3m channel with a high speed 12Mbps, 25m channel) 2. USB 2.0 (high speed 480Mbps 25m channel) 3. Wireless USB (high speed 480Mbps 3m) USB device can be hot swapped, that is the devices can be plugged and unplugged without rebooting the host or turning off the device USB device can either be bus-powered or self-powered USB host connects to devices using USB driving software and host controller connected to a root hub. A hub is one that connects to other nodes or hubs. It is a tree like topology

USB cable has four wires, one for +5V, two for twisted pairs and one for ground
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There are termination impedances at each end as per the speed of the device EMI shielded are used for high speed USB cables NRZ data signals and clock is encoded as synch data Four type data transfer: 1. Controlled data transfer 2. Bulk data transfer 3. Interrupt driven data transfer 4. Iso-synchronous data transfer USB is polled bus; host controller ckt regularly polls the presence of a device as scheduled by software Each USB transaction consists of a Token Packet: Consists field for type, direction, USB device address and device end-point number An optional Data Packet, (Containing the payload) A status Packet (Used to acknowledge transactions and to provide a means of error correction) Common USB Packet Fields USB packets consist of the following fields, Sync: All packets must start with a sync field. The sync field is 8 bits long at low and full speed or 32 bits long for high speed and is used to synchronize the clock of the receiver with that of the transmitter. The last two bits indicate where the PID fields starts. PID: PID stands for Packet ID. This field is used to identify the type of packet that is being sent. ADDR: The address field specifies which device the packet is designated for. Being 7 bits in length allows for 127 devices to be supported. Address 0 is not valid. ENDP: The endpoint field is made up of 4 bits, allowing 16 possible endpoints. Low speed devices, however can only have 2 additional endpoints on top of the default pipe. (4 endpoints max) CRC: Cyclic Redundancy Checks are performed on the data within the packet payload. All token packets have a 5 bit CRC while data packets have a 16 bit CRC. EOP: End of packet. Signaled by a Single Ended Zero (SE0) for approximately 2 bit times Advanced Serial High Speed Buses: An embedded system may need to connect multi gigabits per sec. transceiver and receiver serial interfaces. Some exemplary products are: WLAN, Gigabit Ethernet, SONET etc

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ISA Bus: IBM Standard Architecture bus connects only to an embedded device that has an 8086 or 80186 or 80286 processor Processor addressing and PC architecture addressing have limitations No geographical addressing ISA bus limitation for memory accesses can be in two ranges: 640 to 1MB and 15 to 16MB. The former range also overlaps with the range used by video boards and BIOS Addresses allocated in ISA are: 1. For DMA chip 8237 2. For programmable interrupt controller 8255 and timer 8253 3. For parallel port programmable parallel interface 4. For the components on motherboard. 5. Reserved addresses from peripherals 6. IBM COM ports 7. For hard disk and floppy diskette 8. For proto type card like ADC card 9. Synchronous Data Link Control 10. Display monitor ports Interrupt vectors are limited, only 256 vectors Extended ISA is a 32 bit data and address version of ISA EISA supports Serial Communication Interface controller and Ethernet devices PCI (peripheral Component Interconnect) and PCI/X buses: Synchronous parallel bus for interfacing PC-based device Superior throughput than ESIA Platform independent, it is independent to PC platform, interrupt vectors, IO addresses and memory allocations Different versions are: 32/33MHz, 64/66MHz, PCI-X 64/100MHz, PCI Super V2.3 264/528MBps 3.3V, 132/264 and PCI-X Super V1.01a for 800MBps 3.3V Has 32 bit data bus extendible to 64 bits Protocol specifies the interaction between the different components of a computer An application is exemplary PCI card has 16MB flash ROM with a router gateway for a LAN. Automatic detection of interface system and assigning new addresses Simple attachment and detachment of system peripherals Device or host identifies its address space by: i) IO port, ii) memory location and iii) configuration registers of total 256B with a 4B unique ID All devices within the host computer can share IO port addresses and memory locations but cannot share the configuration registers PCI device on boot up disable interrupt
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