HARISH SHARMA

E-mail:harishsharma234@gmail.com Contact No.: +91-8901058538

OBJECTIVE Looking for a challenging career which demands the best of my professional ability in terms of technical and analytical skills, and helps me in broadening and enhancing my current skill and knowledge. EDUCATIONAL QUALIFICATION 2011-2013 Pursuing M. Tech. in Electronics and Communication Engineering(ECE) from ITM University, Gurgaon with a CGPA of 6.81 till 2nd semester 2006-2010 B. Tech. in Electronics and Communication Engineering (ECE) from L.I.E.T. ,Alwar (Formerly: Laxmi Devi Institute of Engineering and Technology, affiliated to RTU Kota) with a percentage of 68.31% . 2005-2006 Higher Secondary from Yashwant sr. sec. school (affiliated to B.S.E.R.), Alwar (Rajasthan) 70.61%. 2002-2003 Senior Secondary from Yashwant sr. sec. school (affiliated to B.S.E.R.), Alwar (Rajasthan) 66.16% .

TECHNICAL-SKILLS Concurrent Languages - HDLs RTL Design in Verilog HDL and VHDL Scripting Languages Shell, Perl/Tk, TCL/Tk Operating Systems Linux RedHat v6, Windows XP/Vista/7 EDA Tools & Technology Cadence Design Systems NC-Sim,Virtuoso Mentor Graphics ModelSim SE v6.0a Xilinx

Xilinx ISE Design Suite 12.3/13.2, Xilinx ISE v7, FPGA Implementation Xilinx SPARTAN 3AN Tanner EDA

 Tanner 7 PROJECTS Dissertation in MULTI CLOCK FIFO for Network on Chip (noc). Verilog HDL: (i) Analysis & simulation of 5-bit Multiplier design using pipelined and
Non -pipelined approaches.

(ii) Design a synchronous circular FIFO structure using VerilogHDL. Training in VLSI Designs from DKOP Labs where I gained industrial insight into various technologies & tools like FPGA, TCL-TK, CMOS & Digital Design & Verilog. Design and FPGA Implementation of UART, PS2 Key Board Interfacing, Ripple Carry Counter, Seven Segment Display. Mini Project(M.tech) on Modeling and Simulation of I-V Char. Of SOLAR CELL Using LTspice. Major Project (B.tech) Radio Frequency Identifier For Security Systems. Mini Project (B.tech) Hardware Design of Mobile Bugg.

TRAINING ASSOCIATIONS DKOP Labs, Noida ITM University, Gurgaon Tool Command Language and Tk Toolkit (Tcl/Tk) Skills Development Program in RTL Design and Verification, VerilogHDL, VHDL, Xilinx FPGA, OrCAD Pspice. Industrial Training on PLCC (Power Line Carrier Communication) from Power Grid Sub Station, Kali Mori Alwar, Rajasthan.. INTERESTS Digital VLSI Design RTL Design and Verification EDA Tools Designing Physical Design Digital Electronics Electronic Device and Circuits.

PERSONAL INFORMATION Date of Birth: Fathers Name: Nationality: Sex: Marital Status: Languages known: Address: 23th April, 1988 Mr. Ram Prakash Sharma Indian Male Single English, Hindi Mr. Ram Prakash Sharma, H. No. 20 A,Hardeva Vihar Alwar Rajasthan-301001

DECLARATION I hereby declare that the information furnished above is true to best of my knowledge.

Place: Gurgaon Date: DEC 2012

Harish Sharma