http://www.codeproject.com/Tips/444385/Frequency-Dividerwith-VHDL library IEEE; use IEEE.STD_LOGIC_1164.

ALL; entity clk200Hz is Port ( clk_in : in STD_LOGIC; reset : in STD_LOGIC; clk_out: out STD_LOGIC ); end clk200Hz; architecture Behavioral of clk200Hz is signal temporal: STD_LOGIC; signal counter : integer range 0 to 124999 := 0; begin frequency_divider: process (reset, clk_in) begin if (reset = '1') then temporal <= '0'; counter <= 0; elsif rising_edge(clk_in) then if (counter = 124999) then temporal <= NOT(temporal); counter <= 0; else counter <= counter + 1; end if; end if; end process; clk_out <= temporal; end Behavioral; test bench LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY clk200Hz_tb IS END clk200Hz_tb; ARCHITECTURE behavior OF clk200Hz_tb IS COMPONENT clk200Hz PORT( clk_in : IN std_logic; reset : IN std_logic;

clk_out: OUT std_logic ); END COMPONENT; -- Inputs signal clk_in : std_logic := '0'; signal reset : std_logic := '0'; -- Outputs signal clk_out : std_logic; constant clk_in_t : time := 20 ns; BEGIN -- Instance of unit under test. uut: clk200Hz PORT MAP ( clk_in => clk_in, reset => reset, clk_out => clk_out ); -- Clock definition. entrada_process :process begin clk_in <= '0'; wait for clk_in_t / 2; clk_in <= '1'; wait for clk_in_t / 2; end process; -- Processing. stimuli: process begin reset <= '1'; -- Initial conditions. wait for 100 ns; reset <= '0'; -- Down to work! wait; end process; END;

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