Progress In Electromagnetics Research Symposium, Beijing, China, March 23–27, 2009


Design of a SiGe BiCMOS Power Amplifier for WiMAX Application
Cheng-Chi Yu, Yao-Tien Chang, Meng-Hsiang Huang, Luen-Kang Lin, and Hsiao-Hua Yeh Department of Communications Engineering, Feng-Chia University 100, Wen-Hua Rd., Taichung 407, Taiwan, R.O.C.

Abstract— Worldwide interoperability for microwave access (WiMAX) wireless communication
system has been gradually popular in recent years. WiMAX mainly provides a high data rate, long transmission distance, wide coverage, and good quality of service technology to improve the drawback in wireless fidelity (Wi-Fi). Power amplifier is one of the most important components in WiMAX transmitter. A power amplifier operating at 3.5 GHz for WiMAX application is proposed in this paper. The TSMC 0.35-µm SiGe BiCMOS technology is used in this design. The choice of using SiGe BiCMOS technology for this design is based on its better breakdown robustness than CMOS and Si BJT (for same fT ), its technology availability and maturity, and its singlechip integration potential with multi-million gate digital CMOS. The proposed power amplifier is design with two stages open collector common-emitter amplifier. The results demonstrate that it can provide a reasonable efficiency, linearity and good output power. 1. INTRODUCTION

Recently, worldwide interoperability for microwave access (WiMAX) wireless communication system has been gradually popular in wireless communication market. This technology provides not only point to point (PTP) and point to multipoint (PMP) message services, it can also offer a high data rate and long transmission distance. Power amplifier is one of the key components in mobile communications. It needs some characteristics, such as high output power, high linearity and high power added efficiency (PAE). In the past, such implementations were predominantly made in more expensive compound semiconductor technology like Gallium Arsenide (GaAs) and Indium Phosphide (InP). The SiGe-heterojunction bipolar transistor (SiGe-HBT) technology is becoming popular in microwave applications due to its characteristics of low power consumption, high integration level, and low cost than GaAs and InP. Many papers on SiGe technologies of power amplifiers have been published in the past [1–3]. In this paper, a power amplifier operating at 3.5 GHz for WiMAX application is studied. A two stages open collector common-emitter amplifier with active linearity bias circuit is designed. The utility of active linearity bias circuit is for the purpose of obtaining both high efficiency and low nonlinear distortions [4, 5]. The TSMC 0.35-µm SiGe BiCMOS technology is used in this design.

Figure 1 shows the schematic diagram of two stages WiMAX power amplifier. This power amplifier includes driver stage and power stage. In order to increase the available voltage swing at output, this topology utilizes high breakdown transistor for power transistor (Q2), and the power stage should be optimized for maximum power or efficiency. The power transistor (Q2) with emitter area 0.9 × 20.3 × 16 µm2 HBTs, resulting in a total emitter area (AE ) of 292.32 µm2 , is used for power stage in this circuit. On the other hand, high gain and high speed transistor is use for the driver transistor (Q1) to simultaneously achieve both high gain and high output power for the power amplifier. The driver transistor (Q1) with emitter area 0.3 × 20.3 × 8 µm2 HBTs, resulting in a total emitter area (AE ) of 48.72 µm2 , is used for driver stage. The parasitic inductors of the bonding wires of each stage are also considered in circuit design. The input impedance consisting of a bonding inductor with high pass on-chip capacitor and inductor matching network (L1, C1, C2) is matched to 50 Ω. The inter-stage matching network contains L2, C3, and C4. The quarter-wavelength transmission lines of two stages are used to isolate the RF signal from the supply voltage. The output matching network can constrict the high-order harmonics in the output signal. The schematic diagram of bias circuit is shown in Figure 2. The function of the bias circuit is to enhance linearity of power amplifier. When input power level is not big enough, the linearizer is not enabled. On the other hand, when at the high input power level, the impedance of the bias circuit is decreased by the capacitor Cb and the amount of RF power leaking into the bias circuit is increased. The linearizer shunt capacitor with the base-emitter diodes of the transistors compensates the decreased base bias voltage of the transistor (Q1). Therefore, the performance of 1-dB compression point will be improved.


PIERS Proceedings, Beijing, China, March 23–27, 2009

Bias circuit

Bias circuit

Figure 1: Schematic diagram of two stages power amplifier.

Figure 2: Schematic diagram of the bias circuit.


For high power design, a multitude of parallel devices were used to distribute large current among small unit devices. In ideal, the current is equally distributed through the devices. However, if devices are even slightly mismatched, one device will operate at a higher temperature than the others and draw a larger amount of current. Hence, the power gain is degraded by thermal effect. Figure 3 illustrates the power cell of the power stage. Every power cell is connected with four subcells. This type of power cell can make subcells be fed in equal phase, and reduce thermal effect and the parasitic overlap capacitance of base-collector paths. The layout of the two stages power amplifier is shown in Figure 4. Total layout chip size of the power amplifier is 1.094 × 0.792 mm2 .

The WiMAX power amplifier is designed by TSMC 0.35-µm SiGe BiCMOS technology. The software Agilent ADS is used to simulate the circuit characteristics. The simulated results of the circuit are also including parasitic effects of microstrip lines. The simulated S-parameters of the WiMAX power amplifier are depicted in Figure 5. The input return loss S11 , output return loss S22 , gain S21 , and reverse isolation S12 are −16 dB, −11 dB, 24.1 dB, and −49.7 dB, respectively. The output 1-dB compression point P1 dB is 22.1 dBm at operating frequency of 3.5 GHz. A reasonable PAE of 44.5% is obtained, as shown in Figure 6. The supply voltage of the power amplifier is 3 V and the quiescent power consumption is 220 mW.

Progress In Electromagnetics Research Symposium, Beijing, China, March 23–27, 2009


Figure 3: Power cell of the power stage.

Figure 4: Layout of the two stages power amplifier.

Figure 5: S-parameters of WiMAX SiGe power amplifier. 5. CONCLUSION

Figure 6: Output Power, Gain and PAE versus input power.

A SiGe BiCMOS power amplifier for WiMAX application is proposed. The chip area is 1.094 × 0.792 mm2 . The active linearity bias is used to improve 1-dB compression point and achieve high linearity and efficiency. The power amplifier has 24.1 dB power gain, 46.3% PAE, 22.1 dBm output power at P1 dB , and 23.7 dBm maximum output power under 3 V operation voltage. The total quiescent power consumption of the power amplifier is 220 mW.

The authors would like to thank National Chip Implementation Center (CIC) for technical support.

1. Peng, Y.-J., J.-Y. Song, and Z.-G. Wang, “A 3.3 V SiGe HBT power amplifier for 5 GHz WLAN application,” 8th International Conference on Solid-State and Integrated Circuit Technology, ICSICT ’06, 1541–1543, 2006. 2. Lin, C. H., Y. K. Su, Y. Z. Juang, C. F. Chiu, S. J. Chang, J. F. Chen, and C. H. Tu, “The optimized geometry of the SiGe HBT power cell for 802.11a WLAN applications,” Microwave and Wireless Components Letters, Vol. 17, 49–51, IEEE, 2007. 3. Liao, H.-Y., K.-Y. Chen, J. D.-S. Deng, and H.-K. Chiou, “0.35-µm SiGe BiCMOS variablegain power amplifier for WiMAX transmitters,” 2007. 4. Y. Ping-Chun, L. Kuei-Cheng, C. Y. Lee, and C. Hwann-Kaeo, “A 1.8-V monolithic SiGe HBT power amplifier with a novel proposed linearizing bias circuit,” The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, Vol. 1, 305–308, 2004. 5. Sub, N. Y. and P. C. Soon, “PCS/W-CDMA dual-band MMIC power amplifier with a newly proposed linearizing bias circuit,” IEEE Journal of Solid-State Circuits, Vol. 37, 1096–1099, 2002.

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