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Presented by Niket Agrawal (MTech VLSI)
What is a transistor (Digital Definition)
VGS V T Ron S D
An MOS Transistor
The NMOS Transistor
Threshold Voltage: Concept
S + VGS G D
n-channel p-substrate B
Transistor in Linear
VGS S G n+ – VDS D n+ L x ID
MOS transistor and its bias conditions
VT D G S n+ - VGS .VT + n+ Pinch-off .Transistor in Saturation VGS VDS > VGS .
Current-Voltage Relations Long-Channel Device .
0 V 0 0 0.5 V 5 4 Resistive Saturation VGS= 2.0 V 3 VDS = VGS .5 2 2.5 .Current-Voltage Relations 6 x 10 -4 VGS= 2.5 V Quadratic Relationship ID (A) 2 1 VGS= 1.VT VGS= 1.5 1 V DS (V) 1.
5 x (V/µm) .Velocity Saturation ( Deep sub micron Era) u n ( m /s) usat = 105 Constant velocity Constant mobility (slope = µ) xc = 1.
V T VDS .Perspective ID Long-channel device VGS = VDD Short-channel device V DSAT VGS .
5 -4 2 quadratic linear 1.5 2 2.5 quadratic 0.5 2 2.5 1 VGS(V) 0 0 1.5 ID (A) 3 2 1 1 0.5 1 VGS(V) 1.5 0 0 0.ID versus VGS 6 5 4 I D (A) x 10 -4 x 10 2.5 Long Channel Short Channel .
A unified model for manual analysis .
6 VGS = -2.5 -2 -1.5V -1 -2.0V Assume all variables negative! -0.4 ID (A) -0.5 0 .5V -0.2 VGS = -1.8 VGS = -2.0V -0.5 VDS (V) -1 -0.A PMOS Transistor 0 x 10 -4 VGS = -1.
MOS Capacitances G CGS S CGD D CSB CGB CDB B .
The Gate Capacitance Poly silicon gate Source n+ xd Ld Top view xd W Drain n+ Gate-bulk overlap Gate oxide tox n+ L Cross section n+ .
Gate Capacitance G CGC S D S G CGC D S G CGC D Cut-off Resistive Saturation Most important regions in digital design: saturation and cut-off .
Diffusion Capacitance Channel-stop implant N A1 Side wall W Source ND Bottom xj Side wall LS Channel Substrate N A .
n 1 Cox qVGS nkT 10 -8 10 -10 Exponential VT 0.5 1 VGS (V) 10 -12 0 1.5 .5 2 2.Sub-Threshold Region (MOS now a BJT) 10 -2 Linear 10 -4 10 ID (A) -6 Quadratic CD I D ~ I 0e .
html .com/semiconduct ors/semiconductors.Fabrication For a great tour through the IC manufacturing process and its different steps.fullman. check http://www.
CMOS Process at a Glance Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers .
Inverter Layout VDD PMOS In Out NMOS Metal Thick field oxide p+ n+ n+ p substrate p+ n well p+ n+ .
Fabrication Steps Start with blank wafer (typically p-type where NMOS is created) First step will be to form the n-well (where PMOS would reside) Cover wafer with protective layer of SiO2 (oxide) Remove oxide layer where n-well should be built Implant or diffuse n dopants into exposed wafer to form n-well Strip off SiO2 p substrate .
Oxidation Grow SiO2 on top of Si wafer 900 – 1200 C with H2O or O2 in oxidation furnace SiO 2 p substrate .
Photoresist Photo resist Photoresist is a light-sensitive organic polymer Property changes where exposed to light Two types of photo resists (positive or negative) Positive resists can be removed if exposed to UV light Negative resists cannot be removed if exposed to UV light Photoresist SiO 2 p substrate .
Lithography Expose photoresist to Ultra-violate (UV) light through the n-well mask Strip off exposed photo resist with chemicals Photoresist SiO 2 p substrate .
creates an opening to the silicon surface Photoresist SiO 2 p substrate .Etch Etch oxide with hydrofluoric acid (HF) Only attacks oxide where resist has been exposed N-well pattern is transferred from the mask to silicon-di-oxide surface.
Strip Photoresist Strip off remaining photoresist Use mixture of acids called piranah etch Necessary so resist doesn’t melt in next step SiO 2 p substrate .
only enter exposed Si SiO2 shields (or masks) areas which remain p-type SiO 2 n well .N-well N-well is formed with diffusion or ion implantation Diffusion Place wafer in furnace with arsenic-rich gas Heat until As atoms diffuse into exposed Si Ion Implanatation Blast wafer with beam of As ions Ions blocked by SiO2.
Strip Oxide Strip off the remaining oxide using HF Subsequent steps involve similar series of steps n well p substrate .
Poly silicon (self-aligned gate technology) Deposit very thin layer of gate oxide < 20 Å (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with Silane gas (SiH4) Forms many small crystals called polysilicon Heavily doped to be good conductor Polysilicon Thin gate oxide n well p substrate .
and n-well contact n well p substrate . drain.Self-Aligned Process Use gate-oxide/poly silicon and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nMOS source.
N-diffusion/implantation Pattern oxide and form n+ regions Self-aligned process where gate blocks ndopants Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing n+ Diffusion n well p substrate .
N-diffusion/implantation cont. Historically dopants were diffused Usually high energy ion-implantation used today But n+ regions are still called diffusion n+ n+ n well p substrate n+ .
P-Diffusion/implantation Similar set of steps form p+ “diffusion” regions for PMOS source and drain and substrate contact p+ Diffusion p+ n+ n+ p substrate p+ n well p+ n+ .
Contacts Now we need to wire together the devices Cover chip with thick field oxide (FO) Etch oxide where contact cuts are needed Contact Thick field oxide p+ n+ n+ p substrate p+ n well p+ n+ .
leaving wires Metal Metal Thick field oxide p+ n+ n+ p substrate p+ n well p+ n+ .Metalization Sputter on aluminum over whole wafer Gold is used in newer technology Pattern to remove excess metal.
CMOS INVERTER VDD V DD V DD Rp PMOS In Out NMOS Rn V out V out V in 5 V DD V in 5 0 .
5 2 0.5 Vin 0.5 PMOS In Out NMOS NMOS res PMOS off 2.5 1 1.5 1 1.5 2 .CMOS Inverter VTC Vout NMOS off PMOS res NMOS s at PMOS res NMOS sat PMOS sat NMOS res PMOS sat VDD 2.
5) VDD 0.CMOS Inverter Propagation Delay VDD tpHL = f(R on.36 Vin = V DD RonCL t .69 RonCL Vout Vout CL Ron 1 ln(0.5 0.CL) = 0.
5 0 -0.Transient Response 3 2.5 1 0.5 0 ? tp = 0.69 CL (Reqn+Reqp)/2 tpLH tpHL Vout(V) 0.5 2 1.5 1 t (sec) 1.5 2 x 10 2.5 -10 .
Design for Performance Keep capacitances small Increase transistor sizes watch out for self-loading! Increase VDD (???) .
2 1.6 1.8 tp(normalized) 1 1.4 V DD (V) .5 2 1.2 2.Delay as a function of VDD 5.5 4 3.5 5 4.5 3 2.4 1.5 1 0.8 2 2.
6 3.8 2.8 3.6 2.2 3 2.Delay as a function of Device Sizing 3.2 2 2 4 6 8 S 10 12 14 x 10 -11 (for fixed load) Self-loading effect: Intrinsic capacitances dominate tp(sec) .4 3.4 2.
Where Does Power Go in CMOS? • Dynamic Power Consumption Charging and Discharging Capacitors • Short Circuit Currents Short Circuit Path between Supply Rails during Switching • Leakage Leaking diodes and transistors .
Dynamic Power Dissipation Vdd Vin Vout CL L 2 dd L 2 dd Energy/transition = C * V Power = Energy/transition * f = C * V *f .
0 5.10 0.15 IVDD (mA) 0.0 3.0 Vin (V) 4.05 0.0 1.0 .Short Circuit Currents Vd d Vin CL Vout 0.0 2.
Leakage Vd d Vout Drain Junction Leakage Sub-Threshold Current Sub-threshold current one of most compelling issues Sub-Threshold Current Dominant Factor in low-energy circuit design! .
9 V by 2010!) Reduce switching activity Reduce physical capacitance .Principles for Power Reduction Prime choice: Reduce voltage! Recent years have seen an acceleration in supply voltage reduction Design at very low voltages still open question (0.6 … 0.
sell the same part for less money Price of a transistor has to be reduced But also want to be faster. lower power . smaller.Goals of Technology Scaling Make things cheaper: Want to sell more functions (transistors) per chip for the same money Build same products cheaper.
This is in contrast to the dynamic circuit class. The outputs of the gates assume at all times the value of the Boolean function. once again. . which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. the transient effects during switching periods).Static CMOS Circuit At every point in time (except during the switching transients) each gate output is connected to either VDD or Vss via a low-resistive path. implemented by the circuit (ignoring.
…InN) PDN PUN NMOS only PUN and PDN are dual logic networks .Static Complementary CMOS VDD In1 In2 InN In1 In2 InN PMOS only F(In1.In2.
VTn CL VDD |VTp| PDN D VDD 0 VGS VDD S CL S CL D .Threshold Drops PUN VDD S VDD D VDD D 0 VDD CL VGS S 0 VDD .
Example Gate: NAND .
Complex CMOS Gate B A C D OUT = D + A • (B + C) A D B C .
low output impedance Extremely high input resistance. nearly zero steady-state input current No direct path steady state between power and ground. high noise margins Logic levels not dependent upon the relative device sizes. ratioless Always a path to Vdd or Gnd in steady state. no static power dissipation Propagation delay function of load capacitance and resistance of transistors .CMOS Properties Full rail-to-rail swing.
5 0 100 200 300 400 A=1. B=01 A= 01. B=1 A=B=10 67 64 61 45 80 81 Voltage [V] 1.Delay Dependence on Input Patterns 3 2.5 0 -0. B=1 time [ps] .5 2 A=B=10 A=1 0. B=10 A= 10. B=1 A=1. B=10 Input Data Pattern Delay (psec) A=B=01 A=1.5 1 0.
decreasing gains as technology shrinks In3 In2 In1 M3 M2 M1 C3 C2 C1 .Fast Complex Gates: Design Technique 1 Transistor sizing as long as fan-out capacitance dominates Progressive sizing InN MN CL Distributed RC line M1 > M2 > M3 > … > MN (the fet closest to the output is the smallest) Can reduce delay by more than 20%.
C1 and C2 delay determined by time to discharge CL .Fast Complex Gates: Design Technique 2 Transistor ordering critical path critical path 01 In1 M3 In2 1 M2 In3 1 M1 In3 1 M3 In2 1 M2 In1 M1 01 charged CL C2 charged C1 charged charged CL C2 discharged C1 discharged delay determined by time to discharge CL.
Summary It was a big talk At last it finished Now I Want to enjoy Sunday .