~~~~~~~~~~~ uP-II ~~~~~~~~~~~~

**Singh And Singh:SS
**Sunil Mathur:SM
UNIT 1 + UNIT 2
SS 1.8, 17.1 to 17.28 "OR" SM Chapter 2,3,4,6
+
SM 16.10, 16.11, 17.10
+
Memory Segmentation
UNIT 3
Interfacing - 8086 and 80386: BHURCHANDI Notes (2nd Sessional)
+
Bus Protocols: Internet
+
SM chapter 8 excluding 8.8, 18.12, chapter 9
UNIT 4
SM 18.2, 18.3, 18.5(0verview of Registers), 18.6 to 18.11, 18.13, 18.14, 18.16,
18.17, 18.19, 18.21, 18.22, chapter 5
SS 22.1, 22.3, 22.4, 22.7, 22.8, 22.9, 22.11
+
DSP Processor, Bit Slice Processors, Transputer: Piyush Sir Notes
UNIT 5 OPTIONAL UNIT (80-1/2/3/4-86)
SS Chapter 20 "OR" SM Chapter 16,17