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Left Shift Ars

Left Shift Ars

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Published by Vicheka Phor

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Published by: Vicheka Phor on Jan 01, 2013
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03/07/2015

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Subj ect : ars

Fr om: Vicheka PHOR (phorvicheka@yahoo.com)
To: wuailx@gmail.com;
Dat e: Tuesday, December 18, 2012 3:34 PM
-------------------------------------------------------------------------------
-- Banc de registres
-- THIEBOLT Francois le 05/04/04
-------------------------------------------------------------------------------
--------------------------------------------------------------
-- Par defaut 32 registres de 32 bits avec lecture double port
--------------------------------------------------------------
-- Definition des librairies
library IEEE;
-- Definition des portee d'utilisation
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.cpu_package.all;
-- Definition de l'entite
entity ars is
-- definition des parametres generiques
generic (
-- largeur du bus de donnees par defaut
DSIZE : natural := 8 -- registre de 8 bits par defaut
);
-- definition des entrees/sorties
port (

-- bus d'adresse et donnees
DIN : in std_logic_vector(DSIZE-1 downto 0);

-- Shift positions
Shift: in std_logic_vector(log2(DSIZE)-1 downto 0);

-- Ports de sortie
DOUT : out std_logic_vector(DSIZE-1 downto 0) );
end ars;
-------------------------------------------------------------------------------
-- REGISTRES architecture in a behavioral style
-------------------------------------------------------------------------------
-- Definition de l'architecture du banc de registres
architecture behavior of ars is
-- n := conv_integer(Shift);
-- DOUT(DOUT'left-n downto 0) <= DIN (D'left downto n);
-- DOUT(DOUT'left downto DOUT'left-n+1) <= (other => DIN(DIN'left));

begin
-----------------
-- Process P_REGS
P_Shift: process(Shift,DIN)
variable n: natural range 0 to 8;
variable DOUT_tmp: std_logic_vector(DOUT'range);
---------------------------------
begin


n := conv_integer(Shift);
DOUT_tmp := DIN;

for i in 1 to n loop
DOUT_tmp := DIN(DIN'left) & DOUT_tmp(DOUT_tmp'left downto 1);
end loop;
DOUT <= DOUT_tmp;
end process P_Shift;
---------------------------------
-- affectation des bus en lecture
end behavior;

DOUT_tmp := DIN.REGISTRES architecture in a behavioral style -------------------------------------------------------------------------------. -. -. for i in 1 to n loop DOUT_tmp := DIN(DIN'left) & DOUT_tmp(DOUT_tmp'left downto 1). --------------------------------begin n := conv_integer(Shift). DOUT <= DOUT_tmp. ---------------------------------.Definition de l'architecture du banc de registres architecture behavior of ars is -. -------------------------------------------------------------------------------.affectation des bus en lecture end behavior.DIN) variable n: natural range 0 to 8. begin -----------------.Process P_REGS P_Shift: process(Shift.DOUT(DOUT'left downto DOUT'left-n+1) <= (other => DIN(DIN'left)).DOUT(DOUT'left-n downto 0) <= DIN (D'left downto n).end ars.n := conv_integer(Shift). end loop. . end process P_Shift. variable DOUT_tmp: std_logic_vector(DOUT'range).

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