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Fall 2000

**Microelectronic Devices and Circuits- EECS105 Final Exam
**

Wednesday, December 13, 2000

**Costas J. Spanos University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences
**

Your Name: ____________________________________________ (last) (first) Your Signature: __________________________________________ 1. Print and sign your name on this page before you start. 2. You are allowed three, 8.5”x11” handwritten sheets. No books or notes! 3. Do everything on this exam, and make your methods as clear as possible. Problem 1 ________ / 24 Problem 2 ________ / 26 Problem 3 ________ / 26 Problem 4 ________ / 24 TOTAL _________ / 100 MOS Device Data (you may not have to use all of these...) µn Cox = 50 µA/V 2, µpC ox = 25µ A/V2, V Tn = -V Tp = 1V, Lmin = 2µm. VBS = 0. λn = λp = 0.1V −1 when L = 1µm, and it is otherwise proportional to 1/L Cox = 2.3fF/µ m2 , Cjn = 0.1fF/µm 2, C jp = 0.3fF/µ m2 , Cjswn = 0.5fF/ µm, Cjswp = 0.35fF/µm, Covn = 0.5fF/µm, Covp = 0.5fF/ µm

total 24) Why are bipolar transistors capable of providing more drive current compared to MOS transistors that occupy similar area? (give a qualitative answer) Comparing a Common Collector to a Common Drain voltage buffer amplifier. W. Place a mark below to indicate your choice. trying to get the largest DC voltage gain. etc. base-width) and doping levels. one sees some advantages and disadvantages. Aspect Rin Rout Av CC CD In the IC industry “layout designers” can manipulate lateral device dimensions (L.EECS105 2 of 13 Fall 2000 Problem 1 of 4: Answer each question briefly and clearly. area of baseemitter junction. List a parameter that each designer can change to affect the respective parameter. or write “none” if the designer cannot affect the value of the respective parameter: Parameter VTn ro (NMOS) gm (NMOS) ro (npn) gm (npn) Cgs Layout Designer Process Designer . (4 points each.) while “process designers” manipulate vertical dimensions (Tox.

EECS105 3 of 13 Fall 2000 What advantage(s) does a cascode configuration has over a cascade configuration? Which conditions must be satisfied so that the open circuit time constant method leads to an exact solution? In your own words. how does the dreaded “Miller effect” limit frequency response of a high voltage gain amplifier? .

make sure that you show the expressions before you plug in the specific values. driven by a perfect current source (r oc= ∞ ) For each of the following questions. That comes later). even if the numerical calculation is incorrect! a) Find (W/L)1 ratio so that the overall Gm of this amp is 1mS.EECS105 4 of 13 Fall 2000 Problem 2 of 4 (26 points) Consider the following cascode amplifier. (5 points) Expression for (W/L)1 (W/L) 1= Value . A correct expression is worth 70% of the credit. (Do not specify values for W and for L here.

and calculate the respective value of the overall Rout of this amplifier.EECS105 5 of 13 Fall 2000 b) Assume that gm2=gm1. and ro2 = ro1 . (5 points) Expression for L1 L1 = Value Expression for Rout Rout = Value . Find the value of L1 so that ro1 = 200kΩ.

(5 points) Expression for Voltage Gain vout/vin = Value in db d) Calculate VBIAS (ignoring channel-length modulation).EECS105 6 of 13 Fall 2000 c) Find the open circuit voltage gain of this two stage amplifier (roc= ∞ ). Assume that (W/L)1 = (W/L)2 = 16 (note that this is not the correct answer to question 2.a) (5 points) Expression for VBIAS VBIAS = Value .

Explain your thinking in one sentence (ignore channel length modulation). find the value for VG2 that will give you the maximum voltage swing for this amp. (6 points) What limits Vout min? Expression for VG2 VG2 = Value .EECS105 7 of 13 Fall 2000 e) Assuming that (W/L) 2 = 16.

(5 points) Expression for VBIAS VBIAS= Value . (Be very careful with signs in this problem!). even if the numerical calculation is incorrect! a) Calculate VBIAS so that Vout = 2. For each of the following questions. make sure that you show the expressions before you plug in the specific values. IS= 10-17 A and VA = infinity. A correct expression is worth 70% of the credit.EECS105 8 of 13 Fall 2000 Problem 3/4 (26 points) Consider the following pnp CE amplifier. Note that βo = 50. Ignore I B and Rs for this question. (Do NOT assume that VBE is exactly -0.7V).5V.

so that it does not disrupt the biasing of the transistor.) (5 points) Expression for RL that cuts the gain by a factor of 2.EECS105 9 of 13 Fall 2000 b) Find Rout and the voltage gain. if R L = infinity. (8 points) Expression for Rout Rout = Value Expression for Voltage Gain vout/vin = Value c) Calculate the value of R L that will cut the gain by a factor of two. RL = Value . (Assume that R L is connected through a small coupling capacitor.

improved βo’ = Xβo. (Hint: assume that the new.EECS105 10 of 13 Fall 2000 d) If you could increase βo. how much would you have to increase it in order to increase the gain by 10%.) X= Value . (8 points) Expression for X (multiplier for increasing βo. and write an expression that you can use to calculate the value of the factor X).

. a) Find the low frequency voltage gain vout/vin. Do this in stages as shown in the table below: (6 points) Expression v2/vs = v3/v2 = vout/v3 = vout/vs = Value . a current buffer and a voltage buffer. (this means that you can ignore all the capacitors).EECS105 11 of 13 Fall 2000 Problem 4/4 (24 points) The following is a cascade of three 2-ports: a transconductance amplifier. The aim of this circuit is to produce lots of voltage gain over a wide bandwidth.

Cµ2 . CM3 . 2. Cµ3. 3 and 4. with their Miller equivalent CM1 . (6 points) Expression CM1 = CM2 = CM3 = c) Calculate the Open Circuit Time Constant for the nodes 1.EECS105 12 of 13 Fall 2000 b) Replace all “cross-over” caps Cµ1. (6 points) Value Expression RT1 = RT2= RT3= RT4= Total RC RC1 = RC2 = RC3 = RC4 = Value . CM2 .

EECS105 d) Calculate the ω3db of this amp (6 points) 13 of 13 Fall 2000 Expression for ω3db. ω3db = Value ~ That’s All Folks! ~ .

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