CoE 141 Lab Experiment 1

Patrice Abbie D. Legaspi
Kathleen D. Santiago

2009-29355
2009-26924

DATA GATHERED:
PMOS
width (um)

VIL (V)

VIH (V)

VOL (V)

VOH (V)

0.12

0.380

0.600

0.0850

1.140

230.0

115.0

0.15

0.402

0.625

0.0904

1.130

198.0

0.18

0.421

0.647

0.0934

1.130

0.21

0.439

0.666

0.0957

0.24

0.456

0.683

0.27

0.471

0.3

TpHL (ps) TpLH (ps) NMH (V)

NML (V)

NM (V)

0.540

0.2950

0.8350

118.0

0.505

0.3116

0.8166

173.0

122.0

0.483

0.3276

0.8106

1.120

155.0

123.0

0.454

0.3433

0.7973

0.0969

1.120

139.0

126.0

0.437

0.3591

0.7961

0.698

0.0978

1.110

132.0

127.0

0.412

0.3732

0.7852

0.486

0.711

0.0988

1.110

116.0

130.0

0.399

0.3872

0.7862

0.33

0.499

0.724

0.0983

1.100

105.0

134.0

0.376

0.4007

0.7767

0.36

0.512

0.736

0.0974

1.100

97.7

135.0

0.364

0.4146

0.7786

ANALYSIS:
From the results gathered, we noticed that as you decrease the width of the PMOS, the noise
margin increases. We want a noise margin that's big so that we can withstand a bigger amount of noise.
In this case, the best PMOS width would be 0.12 um.
We also saw that the Propagation Delay from high to low and the Noise Margin low are both
directly proportional to the width of the PMOS while the Propagation Delay from low to high and the
Noise Margin high are inversely proportional to the width of the PMOS.

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