# 147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

Department of ECE

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147451 Electronic Circuits II & Simulation Lab CIRCUIT DIAGRAM: CURRENT- SERIES FEEDBACK AMPLIFIER: Without feedback: Without feedback:

II Yr / IV sem

12Vdc

R1 51KΩ

RC 2.4KΩ C2

C1 0.1uF Vin = 20mV f = 20 Hz– 20KHz

Q1

0.1uF

BC107A

RL 4.7KΩ R2 9KΩ RE 600Ω

+
CRO

CE 5.3uF

Department of ECE

Page 2

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

1. CURRENT SERIES FEEDBACK AMPLIFIER
AIM:
1. To design a Current Series feedback amplifier for the following specifications. Vcc=12 V, Ic=2mA,VBE=0.6V, hfe=200. 2. To plot the frequency response graph for the amplifier with and without feedback. 3. To calculate the following parameters with and without feedback a) Voltage gain b) Bandwidth

EQUIPMENTS REQUIRED:
RANGE EQUIPMENT Power supply CRO Function generator (0-30)V (0-20)MHz (0-1)MHz QUANTITY 1 1 1

COMPONENTS REQUIRED:
COMPONENT BJT Resistors Capacitors BC107 QUANTITY 1

DESIGN:
Given Specifications are Vcc=12 V, Ic=2mA,VBE=0.6V, hfe=200. Rule of Thumb:

IC ≈ IE re=26mV/IE re=26×10-3/2×10-3 = 13 Ω hie=hfe re=2.6 KΩ Department of ECE Page 3

147451 Electronic Circuits II & Simulation Lab CURRENT.1uF BC107 RL 4.1uF Vin = 20mV f = 20Hz – 20KHz R2 9KΩ Q1 0.SERIES FEEDBACK AMPLIFIER: With Feedback: II Yr / IV sem 12Vdc R1 51KΩ RC 2.7KΩ RE 600Ω CRO + − 0 Department of ECE Page 4 .4KΩ C2 C1 0.

147451 Electronic Circuits II & Simulation Lab To find RE: II Yr / IV sem To find RC: To find biasing resistors R1 and R2: Current through R2: Applying Voltage divider rule. Department of ECE Page 5 .

Department of ECE Page 6 .147451 Electronic Circuits II & Simulation Lab MODEL GRAPH: Frequency Response of Current Series Feedback Amplifier II Yr / IV sem Bandwidth without feedback = f3 – f2. Bandwidth with feedback = f4 – f1.

2KΩ CC=1/ (2πfXcc) Department of ECE Page 7 .147451 Electronic Circuits II & Simulation Lab II Yr / IV sem by solving (1) & (2) we get To find CE: Let the smallest frequency f = 500 Hz To find CC: rin=hie=2.6KΩ XCC=3.

147451 Electronic Circuits II & Simulation Lab TABULATION: Without Feedback: Frequency Vo Volts Gain = Vo/Vs II Yr / IV sem Vin = Gain (dB) = 20log(Vo/Vs) With feedback: Frequency Vo Volts Gain = Vo/Vs Vin = Gain (dB) = 20log(Vo/Vs) Department of ECE Page 8 .

e. 5.. feedback loop. and follow the same procedure (1 to 7). Connect the circuit as per the circuit diagram 2. 7. Keeping the input voltage constant.147451 Electronic Circuits II & Simulation Lab PROCEDURE: II Yr / IV sem 1. Find the input and output impedances. 8. frequency. The results are summarized as follows:Current Series With Without Feedback Feedback Bandwidth Voltage Gain Department of ECE Page 9 . bandwidth. Remove emitter resistance (RE). 4. Plot the graph: gain (dB) vs. 6. i. Set Vs = 50mV. input and output impedance. Calculate the bandwidth from the graph. vary the frequency from 20Hz to 20 KHz in regular steps and note down the corresponding output voltage. Note the phase angle. using the signal generator 3. RESULT: Thus the Current-series feedback amplifier was designed for the given specifications and the frequency response graph was plotted for the circuit with and without feedback.

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

CIRCUIT DIAGRAM: VOLTAGE-SHUNT FEEDBACK AMPLIFIER: Without feedback:

12Vdc

R1 51KΩ

RC
2.4KΩ C2

C1 0.1uF Vin = 20mv f = 20Hz – 20KHz

Q1

0.1uF

BC107A

RL 4.7KΩ R2 9KΩ RE 600Ω CRO

+ −

CE 5.3uF

Department of ECE

Page 10

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

2. VOLTAGE SHUNT FEEDBACK AMPLIFIER
AIM:
1. To design a Voltage Shunt feedback amplifier for the following specifications. Vcc=12 V, Ic=2mA,VBE=0.6V, hfe=200. 2. To plot the frequency response graph for the amplifier with and without feedback. 3. To calculate the following parameters with and without feedback a. Voltage gain b. Bandwidth

EQUIPMENTS REQUIRED:
EQUIPMENT Power supply CRO Function generator RANGE (0-30)V (0-20)MHz (0-1)MHz QUANTITY 1 1 1

COMPONENTS REQUIRED: COMPONENT BJT Resistors Capacitors RANGE BC107 QUANTITY 1

DESIGN:
Given Specifications are Vcc=12 V, Ic=2mA,VBE=0.6V, hfe=200. Rule of Thumb:

IC ≈ IE re=26mV/IE re=26×10-3/2×10-3 = 13 Ω hie=hfe re=2.6 KΩ Department of ECE Page 11

147451 Electronic Circuits II & Simulation Lab VOLTAGE-SHUNT FEEDBACK AMPLIFIER: With Feedback:

II Yr / IV sem

12Vdc

R1 51KΩ 1 R5 2.2KΩ C1 0.1uF VAMPL = 20mV f=20Hz-20KHz V2 C4 0.1uF Q1

R3 2.4KΩ C2 0.1uF

BC107A

RL 4.7KΩ R2 9KΩ 9KΩ R4 600Ω CRO

+ −

C3 5.3uF

To find RE: Department of ECE Page 12

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem To find RC: To find biasing resistors R1 and R2: Current through R2: Applying Voltage divider rule. MODEL GRAPH: Department of ECE Page 13 .

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem Frequency Response of Voltage-shunt Feedback Amplifier Bandwidth without feedback = f3 – f2. Department of ECE Page 14 . Bandwidth with feedback = f4 – f1.

2KΩ CC=1/ (2πfXcc) Department of ECE Page 15 .147451 Electronic Circuits II & Simulation Lab II Yr / IV sem by solving (1) & (2) we get To find CE: Let the smallest frequency f = 500 Hz To find CC: rin=hie=2.6KΩ XCC=3.

147451 Electronic Circuits II & Simulation Lab TABULATION: With Feedback: Frequency Vo Volts Gain = Vo/Vs II Yr / IV sem Vin = -----.V Gain (dB) = 20log(Vo/Vs) Without feedback: Frequency Vo Volts Gain = Vo/Vs Vin = …… V Gain (dB) = 20log(Vo/Vs) Department of ECE Page 16 .

147451 Electronic Circuits II & Simulation Lab PROCEDURE:

II Yr / IV sem

1. Connect the circuit as per the circuit diagram 2. Set Vs = 50mV, using the signal generator 3. Keeping the input voltage constant, vary the frequency from 20Hz to 20 KHz in regular steps and note down the corresponding output voltage. 4. Plot the graph: gain (dB) vs. frequency. 5. Find the input and output impedances. 6. Calculate the bandwidth from the graph. 7. Note the phase angle, bandwidth, input and output impedance. 8. Connect the feedback resistor (Rf) between the base and the collector to form the feedback loop, and follow the same procedure (1 to 7). RESULT: Thus the Voltage-shunt feedback amplifier was designed for the given specifications and the frequency response graph was plotted for the circuit with and without feedback. The results are summarized as follows:Voltage-shunt With Without Feedback Feedback Bandwidth Voltage Gain

SERIES AND SHUNT FEEDBACK AMPLIFIER Sample viva questions:
1. 2. What are the advantages of negative Feedback amplifier when compare with amplifier? 3. What will happen to the Bandwidth, gain, output and input resistance of voltage series feedback amplifier because of feedback? 4. Define negative feedback. 5. What is the type of feedback employed in feedback amplifier? 6. Compare Oscillator and Amplifier. 7. Define Desensitivity and Sensitivity factor. 8. When a feedback amplifier is said to be stable? 9. A common – emitter circuit without By-pass capacitor is called a negative current feedback circuit why? 10. Current series amplifier is a Transconductance amplifier: Justify? 11. Voltage Shunt amplifier is a Transresistance amplifier: Justify? 12. A common – collector amplifier circuit is an example of which negative feedback circuit? CIRCUIT DIAGRAM: Department of ECE Page 17

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

RC PHASE SHIFT OSCILLATOR:

Department of ECE

Page 18

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

3. DESIGN OF RC PHASE SHIFT OSCILLATOR AIM:
1. To design and construct a RC Phase shift oscillator for the following specifications. Vcc = 12V, Ic = 2mA, VBE = 0.6V, hfe = 200, f = 2 KHz, C = 0.01µF 2. To plot the output sine waveform graph for the Oscillator.

EQUIPMENTS REQUIRED:
EQUIPMENT Power supply CRO RANGE (0-30)V (0-20)MHz QUANTITY 1 1

COMPONENTS REQUIRED: COMPONENT BJT Resistors Capacitors RANGE BC107 QUANTITY 1

DESIGN:
Given Specifications are Vcc = 12V, Ic = 2mA, VBE = 0.6V, hfe = 200, f = 2 KHz, C = 0.01µF Rule of Thumb:

IC ≈ IE re=26mV/IE re=26×10-3/2×10-3 = 13 Ω hie=hfe re=2.6 KΩ

Department of ECE

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147451 Electronic Circuits II & Simulation Lab II Yr / IV sem MODEL GRAPH: Department of ECE Page 20 .

147451 Electronic Circuits II & Simulation Lab To find RE: II Yr / IV sem To find RC: To find biasing resistors R1 and R2: Current through R2: Applying Voltage divider rule. Department of ECE Page 21 .

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem TABULATION: Amplitude (Volts) Time Period T (Seconds) Frequency f (KHz) Department of ECE Page 22 .

2KΩ CC=1/ (2πfXcc) Department of ECE Page 23 .6KΩ XCC=3.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem by solving (1) & (2) we get To find CE: Let the smallest frequency f = 500 Hz To find CC: rin=hie=2.

C = 0.01µF C = 1 / (2π f R√6) = 0.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem To find the feedback capacitor C: Given f = 2 KHz.01µF Department of ECE Page 24 .

Department of ECE Page 25 .2 K Ω – (7. Connect the circuit as per the circuit diagram.65K Ω || 2. 3.2 K Ω – 1.2 K Ω .94K Ω R´ = 260 Ω PROCEDURE: 1.Ri = 2. 2.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem To find R´ R´ = R. Note down the practical frequency and compare it with the theoretical frequency.6K Ω) = 2. RESULT: Thus the RC phase shift oscillator was designed for the given frequency and the output sine waveform was plotted.(R1 || R2 || hie) = 2. Switch on the power supply and observe the output on the CRO (Sine wave). Theoretical frequency of the oscillator Practical frequency of the oscillator = = 2 KHz.

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem CIRCUIT DIAGRAM: HARTLEY OSCILLATOR: Department of ECE Page 26 .

hfe = 200. Ic = 2mA. L1 = 1mH 2. To design and construct a Hartley oscillator for the following specifications.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem 4.6V. DESIGN OF HARTLEY OSCILLATOR AIM: 1. VBE = 0. Ic = 2mA. f = 100KHz. To plot the output sine waveform graph for the Oscillator. Vcc = 12V. hfe = 200.6V. L1 = 1mH Rule of Thumb: IC ≈ IE re=26mV/IE Department of ECE Page 27 . EQUIPMENTS REQUIRED: EQUIPMENT Power supply CRO RANGE (0-30)V (0-20)MHz QUANTITY 1 1 COMPONENTS REQUIRED: COMPONENT BJT Resistors Capacitors RANGE BC107 QUANTITY 1 Design: Given Specifications are Vcc = 12V. VBE = 0. f = 100KHz.

6 KΩ II Yr / IV sem MODEL GRAPH: Department of ECE Page 28 .147451 Electronic Circuits II & Simulation Lab re=26×10-3/2×10-3 = 13 Ω hie=hfe re=2.

Department of ECE Page 29 .147451 Electronic Circuits II & Simulation Lab II Yr / IV sem To find RE: To find RC: To find biasing resistors R1 and R2: Current through R2: Applying Voltage divider rule.

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem TABULATION: Amplitude (Volts) Time Period T (Seconds) Frequency f (KHz) Department of ECE Page 30 .

2KΩ CC=1/ (2πfXcc) Department of ECE Page 31 .6KΩ XCC=3.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem by solving (1) & (2) we get To find CE: Let the smallest frequency f = 500 Hz To find CC: rin=hie=2.

4mH Department of ECE Page 32 . L1 = 0. L2 = 2.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem To find the feedback capacitor C: Given f = 100 KHz.1 mH.

Connect the circuit as per the circuit diagram. Switch on the power supply and observe the output on the CRO (Sine wave). Theoretical frequency of the oscillator Practical frequency of the oscillator = = 100 KHz. RESULT: Thus the Hartley oscillator was designed for the given frequency and the output sine waveform was plotted. Note down the practical frequency and compare it with the theoretical frequency. Department of ECE Page 33 .147451 Electronic Circuits II & Simulation Lab II Yr / IV sem PROCEDURE: 1. 3. 2.

2mH Department of ECE C1 0.4KΩ Cc Cc 0.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem CIRCUIT DIAGRAM: COLPITTS OSCILLATOR: 12Vdc R1 51KΩ Rc 2.1uF Q1 0.1uF C2 0.1uF BC107A R2 9KΩ CRO R4 600Ω CE 5.01uF Page 34 0 .3uF 0 L 0.

To plot the output sine waveform graph for the Oscillator. hfe = 200. Vcc = 12V. f = 100KHz. VBE = 0.1µF 2. C1 = 0. EQUIPMENTS REQUIRED: EQUIPMENT Power supply CRO Components Required: COMPONENT BJT Resistors Capacitors RANGE BC107 QUANTITY 1 RANGE (0-30)V (0-20)MHz QUANTITY 1 1 DESIGN: Given Specifications are Vcc = 12V.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem 5.1µF Rule of Thumb: Department of ECE Page 35 . C1 = 0. Ic = 2mA. Ic = 2mA. f = 100KHz. hfe = 200.6V. DESIGN OF COLPITTS OSCILLATOR AIM: 1. VBE = 0. To design and construct a Colpitts oscillator for the following specifications.6V.

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem IC ≈ IE re=26mV/IE re=26×10-3/2×10-3 = 13 Ω hie=hfe re=2.6 KΩ TABULATION: Amplitude (Volts) Time Period T (Seconds) Frequency f (KHz) Department of ECE Page 36 .

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem To find RE: To find RC: Department of ECE Page 37 .

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem To find biasing resistors R1 and R2: Current through R2 : Applying Voltage divider rule. MODEL GRAPH: Department of ECE Page 38 .

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem by solving (1) & (2) we get To find CE: Let the smallest frequency f = 500 Hz Department of ECE Page 39 .

2KΩ CC=1/ (2πfXcc) To find the feedback capacitor C2: Given f = 100 KHz.1μF.6KΩ XCC=3.2mH. Department of ECE Page 40 .147451 Electronic Circuits II & Simulation Lab II Yr / IV sem To find CC: rin=hie=2. L = 0. Let C1 = 0.

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem PROCEDURE: 1. Note down the practical frequency and compare it with the theoretical frequency. RESULT: Thus the Colpitts oscillator was designed for the given frequency and the output sine waveform was plotted. Theoretical frequency of the oscillator Practical frequency of the oscillator = = 100 KHz. 3. 2. Connect the circuit as per the circuit diagram. Department of ECE Page 41 . Switch on the power supply and observe the output on the CRO (Sine wave).

147451 Electronic Circuits II & Simulation Lab OSCILLATORS Sample Viva Questions: II Yr / IV sem 1. Three RC sections are used in RC Phase Shift oscillators why? 9. why? 10. List out the applications of oscillators 4. Generally negative feedback is employed in amplifiers whereas positive feedback is employed in oscillators. we apply RC oscillators and not LC oscillators why? CIRCUIT DIAGRAM: Department of ECE Page 42 . Amplifier circuit is necessary in an oscillator. Which oscillator is suitable for low frequency applications? 7. Which oscillator is very suitable for audio range applications? 5. Which oscillator is suitable for RF range applications? 6. What type of feedback is preferred in oscillators? 2. For low frequency applications. why? 8. How does oscillation start in oscillators? 3.

TUNED CLASS C AMPLIFIER AIM: To design a Tuned Class C amplifier for the following specifications. f = 100KHz To plot the frequency response graph for the amplifier.2mH C3 1uF C1 1uF Q1 BC107 VAMPL = 1V FREQ = 100KHz R1 15KΩ CRO 0 6.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem 12Vdc 0. To calculate the following parameters with and without feedback Department of ECE Page 43 .01uF 0. Vcc = 12V.

147451 Electronic Circuits II & Simulation Lab c) Voltage gain d) Bandwidth EQUIPMENTS REQUIRED: EQUIPMENT Power supply CRO Function generator RANGE (0-30)V (0-20)MHz (0-1)MHz II Yr / IV sem QUANTITY 1 1 1 QUANTITY 1 COMPONENTS REQUIRED: COMPONENT RANGE BJT BC107 Resistors Capacitors PROCEDURE: 1. 3. 4. Plot the graph: Gain(dB) Vs frequency. Set Vs=50mV(say). using the signal generator. MODEL GRAPH: Department of ECE Page 44 . vary the frequency from 0Hz to 1 MHz in regular steps and note down the corresponding output voltage. Connect the circuit as per the circuit diagram 2. Keeping the input voltage constant.

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem TABULATION: Frequency Vo Volts Gain = Vo/Vs Vin = Gain (dB) = 20log(Vo/Vs) DESIGN: The given specification is Vcc = 12V. f = 100KHz Department of ECE Page 45 .

II Yr / IV sem L = 1 4π2(1002)k20.2mH Department of ECE Page 46 .01μ L = 0.147451 Electronic Circuits II & Simulation Lab Let us assume The resonant frequency f .

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem Department of ECE Page 47 .

Define Q factor. 3. 2. 5. What do you mean by tuned amplifier? Define Class C amplifier.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem RESULT: Thus the Tuned Class C amplifier was designed and constructed and the frequency response was plotted in the graph. The practical resonant frequency = The lower cut-off frequency = The upper cut-off frequency = Bandwidth of the tuned amplifier = Sample Viva Questions: 1. 6. 7. What is meant by loaded and unloaded Q of tank circuit? What is the need for neutralization in tuned amplifier? CIRCUIT DIAGRAM: Department of ECE Page 48 . Why Q factor is kept as high as possible in tuned circuit? Mention the applications of Class C tuned amplifier. 4. The results are summarized as follows : The theoretical resonant frequency = 100 KHz.

9kΩ 1.9kΩ C 620kΩ RB 620kΩ C 1.162nF Q2 RC 4.162nF Q1 BC107 BC107 7. DESIGN OF ASTABLE MULTIVIBRATOR AIM: 1.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem 10Vdc RB RC 4. To design and construct an astable multivibrator for the following given specifications: Department of ECE Page 49 .

EQUIPMENTS REQUIRED: EQUIPMENT Power supply CRO Function generator RANGE (0-30)V (0-20)MHz (0-1)MHz QUANTITY 1 1 1 COMPONENTS REQUIRED: COMPONENT BJT Resistors Capacitors DESIGN: The given specifications are.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem 2. MODEL GRAPH: Department of ECE Page 50 . RANGE BC107 QUANTITY 1 To find RC:Apply KVL to collector circuit. To plot the collector voltage and base voltage waveform of the two transistors. To find resistance R1 and R2:Apply KVL to the base.

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem TABULATION: Amplitude (V) Parameters VB2 VC1 VB1 VC2 Time (ms) Department of ECE Page 51 .

RESULT: Thus an astable multivibrator was designed and constructed for the given specifications and its output waveforms were observed. Plot the waveform. PROCEDURE: 1. 3. 4. 2. Observe the waveform both at base and collector of Q1 and Q2. Department of ECE Page 52 .147451 Electronic Circuits II & Simulation Lab II Yr / IV sem IB should be greater than IB(min) To find Capacitance C:Time Constant T for astable multivibrator is. Switch on the power supply. Connect the circuit as per the circuit diagram.

DESIGN OF MONOSTABLE MULTIVIBRATOR AIM: Department of ECE Page 53 .147451 Electronic Circuits II & Simulation Lab CIRCUIT DIAGRAM: MONOSTABLE MULTIVIBRATOR: II Yr / IV sem 8.

EQUIPMENTS REQUIRED: EQUIPMENT Power supply CRO Function generator RANGE (0-30)V (0-20)MHz (0-1)MHz QUANTITY 1 1 1 COMPONENTS REQUIRED: COMPONENT BJT Resistors Capacitors DESIGN: The given specifications are RANGE BC107 QUANTITY 1 For stable state assume transistor Q1 is OFF and Q2 is ON. Rc2 = Rc1 =Rc =10µA Select hence take IB2 = 2. To design and construct a monostable multivibrator for the following given specifications: 2.Due to symmetry.5 IB2 (min) Time Constant MODEL GRAPH: Department of ECE Page 54 . To plot the collector voltage and base voltage waveform of the two transistors.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem 1. .

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem TABULATION: Amplitude (V) Parameters VB2 VC1 VB1 VC2 Trigger Input Time (ms) Department of ECE Page 55 .

Sketch the waveform. 5.2 Assume R1 = 10kΩ R2 = 100kΩ Assume Commutative capacitor C1 = 100pF. Let us take 0 = -2R1 + R1 + R2 0.2R2 = 2R1 R2 = 2R1/ 0. RESULT: Thus the monostable multivibrator was designed and constructed for the given specifications and its output waveforms were observed. CIRCUIT DIAGRAM: Department of ECE Page 56 .2R2 R1 + R2 -2R1 + 0. 2.147451 Electronic Circuits II & Simulation Lab As II Yr / IV sem When Q1 is OFF. PROCEDURE: 1. Trigger the monostable multivibrator with a pulse and observe the change in waveform. 4. 3. Sketch the waveform and observe the changes before and after triggering the input to the circuit. Connect the circuit as per the circuit diagram. Switch on the power supply and observe the output waveform at the collector of Q1 and Q2.2R2 =0 0.

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem BISTABLE MULTIVIBRATOR 9. DESIGN OF BISTABLE MULTIVIBRATOR AIM: Department of ECE Page 57 .

EQUIPMENTS REQUIRED: EQUIPMENT Power supply CRO Function generator RANGE (0-30)V (0-20)MHz (0-1)MHz QUANTITY 1 1 1 COMPONENTS REQUIRED: COMPONENT BJT Resistors Capacitors RANGE BC107 QUANTITY 1 DESIGN: The given specifications are Assume Q1 is at cut-off and Q2 is at saturation. To plot the collector voltage and base voltage waveform of the two transistors. so VB1 should be at negative potential. Assume R1 = 10KΩ MODEL GRAPH: Department of ECE Page 58 . To design and construct a monostable multivibrator for the following given specifications: 3.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem 1. Q1 is at cut-off.

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem Department of ECE Page 59 .

Q2 is in saturation.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem By symmetry RC1 = RC2= Rc If IB2 > IB2 (min). then Q2 is in saturation. TABULATION: Department of ECE Page 60 . where τ = RC. As IB2 > IB2 (min). The resolution time is 2τ.

147451 Electronic Circuits II & Simulation Lab Amplitude (V) Parameters VB2 VC1 VB1 VC2 Trigger Input Time (ms) II Yr / IV sem Department of ECE Page 61 .

Switch on the power supply and observe the output waveform at the collector of Q1 and Q2. 2. What is the multivibrator? List the applications of monostable multivibrator. 3. adjustable pulse width generator e. 4. 3. 7. Sketch the waveform.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem PROCEDURE: 1. Sketch the waveform. 6. frequency division d. memory device c. MULTIVIBRATORS Sample Viva Questions: 1. 5. 5. CIRCUIT DIAGRAM: Department of ECE Page 62 . What are the other names for bistable multivibrator? Which multivibrator would be useful for each of the following purpose? a. Connect the circuit as per the circuit diagram. RESULT: Thus the monostable multivibrator was designed and constructed for the given specifications and its output waveforms were observed. 4. Define commutating capacitor. reference clock to synchronize timings in digital systems. Which mutivibrator would function as a time delay unit? Why? How a Schmitt trigger is different from a multivibrator? Mention the applications of astable multivibrator. time-delay unit b. 2. 8. Apply a threshold voltage VT(pulse voltage) and observe the change of states Q1 and Q2.

f = 100 KHz Resistance R (ohms) 27 10 K 100 K Amplitude (Volts) Time (ms) Amplitude (Volts) Time (ms) 10. DESIGN OF DIFFERENTIATOR AND INTEGRATOR AIM: Department of ECE Page 63 . f = 1 KHz Resistance R (ohms) 1K 10 K 100 K INTEGRATOR: Vi = 2Vpp .147451 Electronic Circuits II & Simulation Lab II Yr / IV sem TABULATION: DIFFERENTIATOR: Vi = 2V pp.

To design a low pass RC circuit and observe its response for the given square waveform for T<<RC.Draw the input and output wave forms for different cases. T=RC and T>>RC. To design a high pass RC circuit and observe its response for the given square waveform for T<<RC. EQUIPMENTS REQUIRED: EQUIPMENT CRO Function generator RANGE (0-20)MHz (0-1)MHz QUANTITY 1 1 COMPONENTS REQUIRED: COMPONENT Resistors Capacitors RANGE QUANTITY PROCEDURE: Time constant of the circuit RC= 0. Apply a square wave of 2v p-p amplitude as input.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem 1. 3. 2.0198 ms 1. T=RC.T<<RC and observe the output in each case. T=RC and T>>RC. Adjust the time period of the waveform so that T>>RC. 2. MODEL GRAPH: Department of ECE Page 64 .

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem LOW PASS RC CIRCUIT: Department of ECE Page 65 .

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem HIGH PASS RC CIRCUIT: Department of ECE Page 66 .

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem Department of ECE Page 67 .

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem RESULT: Thus the integrator and differentiator circuits are designed and their output response for various time constants are obtained CIRCUIT DIAGRAM: Department of ECE Page 68 .

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem CLIPPERS: 11. CLIPPERS AND CLAMPERS Department of ECE Page 69 .

The half wave rectifier is the best and simplest type of clipper circuit which clips off the positive/negative portion of the input signal. The magnitude of R and C must be chosen such that the time constant. τ = RC. without distorting the remaining part of the waveform are called clipper circuits or Clippers. The clipper circuits are also called limiters or slicers. but it can also have an independent DC supply to introduce an additional DC shift. The network consists of a capacitor. above or below certain levels as per the requirements. CLAMPERS: Negative peak clamped at positive reference level: Department of ECE Page 70 . EQUIPMENTS REQUIRED: EQUIPMENT Power supply CRO Function generator RANGE (0-30)V (0-20)MHz (0-1)MHz QUANTITY 1 1 1 COMPONENTS REQUIRED: COMPONENT DIODE Resistors Capacitors RANGE IN4001 QUANTITY 1 THEORY: CLIPPERS: The basic action of a clipper circuit is to remove certain portions of the waveform. is large enough to ensure that the voltage across the capacitor does not discharge significantly during the interval when the diode is non-conducting. a diode and a resistance.147451 Electronic Circuits II & Simulation Lab AIM: II Yr / IV sem To obtain the output response for various non linear wave shaping circuits – Clippers and Clampers. CLAMPERS: The clamping network is one that will clamp an input signal to a different DC level. Thus the circuits which are used to clip off unwanted portion of the waveform.

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem Positive peak clamped at negative reference level: DESIGN: CLAMPER : For proper clamping. τ >100T Department of ECE Page 71 .

Negative peak clipper: Vr=2v. Vγ=0.4v When the diode is reverse biased Vo=Vi . Vγ=0.6v When the diode is reverse biased the Vo=Vi Positive base clipper: Vr=2v.6v When the diode is forward biased Vo =Vr+ Vγ =2v+0.6v = 1.6v = 2. Connect the circuit as per circuit diagram shown in Fig. 3.6)v =-2.4v When the diode is reverse biased Vo=Vi .6v = -1. Negative base clipper: Vr=2v.1 2. PROCEDURE: 1.6v When the diode is forward biased Vo=Vr –Vγ = 2v-0. MODEL GRAPH: Department of ECE Page 72 . Vγ=0. T=1ms τ = RL.6v When the diode is forward biased Vo = -Vr+ Vγ = -2v+0. Obtain a sine wave of constant amplitude 8 V p-p from function generator and apply as input to the circuit.C=100×T = 100ms Let C=1μf RL= 100KΩ Select C =1μF and RL =100 kΩ THEORETICAL CALCULATIONS: Positive peak clipper: Vr=2v.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem where T is the time period of input waveform If frequency is 1 kHz with peak-peak input voltage of 10V. Vγ=0. Draw the observed output waveforms.Observe the output waveform and note down the amplitude at which clipping occurs 4.6v When the diode is reverse biased Vo=Vi .6v When the diode is forward biased Vo= -(Vr+ Vγ) = -(2+0.

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem Department of ECE Page 73 .

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem Department of ECE Page 74 .

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem Negative peak clamped at positive reference level: Positive peak clamped at negative reference level: Department of ECE Page 75 .

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem RESULT: Thus the performance of various clipping and clamping circuits were observed. Department of ECE Page 76 .

5 m sM = 1 0m s V M b r e 5 a k N M M b r e 6 a k N 0 Department of ECE Page 77 .147451 Electronic Circuits II & Simulation Lab II Yr / IV sem CIRCUIT DIAGRAM: CMOS INVERTER: 0 V M M 1 0 k V P 1 d c b r e a V V 1 V 2 T D T R T F P W P E R = = = = = = 5 0 0 0 V VV 2 M M 2 k N 0 0 . 5 m s = 1 0m s b r e a 0 CMOS NAND gate: 0 5 V d c V 2 M 4 M b r e a k P M 3 V 1 V 2 T D T R T F P W P E R = = = = = = 5 0 V 0 0 V 1 M b r e a k P 0 0 . 5 m s = 1 0m s V 1 V 2 T D T R T F P W P E R = = = = = = 5 V 0 VV 3 0 0 0 0 .

Go to start  Orcad  capture  New project. then draw the circuit by taking appropriate components and simulate the diagram. NAND and NOR circuits. NAND AND NOR GATES AIM: To simulate the CMOS inverter. 2. Ebipolar – BC107A Breakout – mbreakP.2.L Department of ECE Page 78 . 3.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem 15.c. Create a blank project. Observe the output waveforms.mbreakN Source – Vdc. PROCEDURE: 1.VSRC.Vpulse. SIMULATION OF CMOS INVERTER.Vsin Analog P – r. SOFTWARE REQUIRED: PSPICE Orcad family release 9. 4.

5 m s 1 m sV V T T T P P M 1 2 D R F W E = = = R = = = = 0 0 0 0 0 vV 2 V 5 M b r e a k P 0 0. 5 m s 1 m s V M M M M 2 k N 1 k N b r e a b r e a 0 Department of ECE Page 79 .147451 Electronic Circuits II & Simulation Lab II Yr / IV sem CMOS NOR gate: 0 V 5 v M V 1 V 2 T D T R T F P W P E = = = = = R = 0 = 5 0 0 0 vV 3 V 4 d c 3 b r e a k P M 0 0.

NAND and NOR circuits were simulated and output waveforms are Department of ECE Page 80 .147451 Electronic Circuits II & Simulation Lab II Yr / IV sem RESULT: Thus the CMOS inverter.

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem CMOS inverter CMOS NAND Department of ECE Page 81 .

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem CMOS NOR GATE Department of ECE Page 82 .

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem CIRCUIT DIAGRAM: Department of ECE Page 83 .

SIMULATION OF DIFFERENTIAL AMPLIFIER AIM: To simulate the differential amplifier circuit and obtain the output waveform using PSPICE.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem 16.2. Create a blank project. PROCEDURE: 1. Department of ECE Page 84 . 2. Go to start  Orcad  capture  New project. RESULT: Thus the simulation of differential amplifier was done using PSPICE. SOFTWARE REQUIRED: PSPICE Orcad family release 9. 3. Observe the output waveforms. then draw the circuit by taking appropriate components and simulate the diagram.

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem CIRCUIT DIAGRAM: R 1 D C = A C = T R A N 4 k V 1 0 v V 0 = 0 R 2 0 V 3 U + 2 7 4 0 D C = A C = T R A N V 22 k 0 v V 0 = 0 1 5 v5 O S 2 U S v 1 5 5 v 6 T 1 1 V 0 R D C = A C = T R A N v 13 k 5 v V 0 = 0 3 0 u A 7 4 1 4 0 R 1 k 4 TABULATION : b 0 b1 b2 Theoritical Value Practical Value Digital to analog Department of ECE V- 2 - V+ O O 0 Page 85 .

SIMULATION OF DIGITAL TO ANALOG CONVERTER AIM: To simulate the digital to analog converter using PSPICE. Go to start  Orcad  capture  New project. Department of ECE Page 86 . SOFTWARE REQUIRED: PSPICE Orcad family release 9.2. 3. THEORY: Binary weighed resistor DAC makes use of a summing amplifier using opamp. Observe the output waveforms. V0 = -Rf [ bo/ Ro + b1/R1 + b2/R2] PROCEDURE: 1. Create a blank project. then draw the circuit by taking appropriate components and simulate the diagram.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem 17. When there are n-bits in the digital codes there is a requirement of n number of binary weighed resistors from R to R / 2n-1. 2.

CIRCUIT DIAGRAM: Department of ECE Page 87 .147451 Electronic Circuits II & Simulation Lab II Yr / IV sem RESULT: Thus the simulation of digital to analog converter was done using PSPICE.

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem 18. SOFTWARE REQUIRED: PSPICE Orcad family release 9. To design a second order Butterworth low-pass filter for the following given specifications 2. The general form the second-order low-pass filter is given by where K is the dc gain. DESIGN AND SIMULATION OF II ORDER LOW-PASS BUTTERWORTH FILTER AIM: 1. Use PSPICE to plot the frequency response of the output voltage of the filter designed from 10Hz to 10 KHz. The Butterworth response requires that of The transfer function Department of ECE Page 88 . DESIGN: A second order filter exhibits a stop band roll off of -40 dB/decade.2.

Given specifications are Let us consider the design of the II order LPF from that we can design the Butterworth II order LPF. II ORDER LOW-PASS FILTER DESIGN: The cut-off frequency fo is given by.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem the sallen-key circuit gives to achieve a Butterworth response with sallen key topology. Therefore we must reduce the gain by 1/K. Department of ECE Page 89 .

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem Therefore. Let C = 0. II ORDER BUTTERWORTH LOW-PASS FILTER DESIGN: The transfer function of sallen key circuit gives The transfer function of Butterworth filter gives Department of ECE Page 90 .01μF Gain of the amplifier is. Choose C less than or equal to 1μF.

Solving these two equations for Ra and Rb Here K=4. reduce gain by 1/K.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem To achieve the Butterworth response. The values of Ra and Rb must be such that Rin = R2 and the voltage across Rb is Vi/K. The gain reduction can be achieved by adding a voltage-divider network consisting of Ra and Rb.e. Butter worth low pass Department of ECE Page 91 . i. Voltage across Rb.

Choose location C: programfiles/orcad/…… Create a blank project. 4. Department of ECE Page 92 . Select file in the menu bar → new project. Go to start → all → programs → capture. 8. Create new simulation profile from Pspice menu. 3. Draw the circuit diagram in the schematic editor. 6.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem PROCEDURE: 1. 5. Save the project and click run and observe the output waveform. Choose the frequency range from 10Hz to 10 KHz. In simulation settings select ac sweep and logarithmic scale. 7. 2.

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem RESULT: Thus the Butterworth low pass filter of second order was designed and simulated using PSPICE. CIRCUIT DIAGRAM: Department of ECE Page 93 .

reduce gain by 1/K. fo = 1 KHz. Department of ECE Page 94 . Use PSPICE to plot the frequency response of the output voltage of the filter designed from 10Hz to 10 KHz. To design a second order Butterworth low-pass filter for the following given specifications |H(jω) |= 1. DESIGN AND SIMULATION OF II ORDER HIGH-PASS BUTTERWORTH FILTER AIM: 1. The gain reduction can be achieved by adding a voltage-divider network consisting of Ca and Cb.e. Q = 0. The values of Ca and Cb must be such that Cin = C2 and the voltage across Cb is Vi/K. 2. DESIGN: II ORDER BUTTERWORTH HIGH-PASS FILTER DESIGN: The transfer function of sallen key circuit gives The transfer function of Butterworth filter gives To achieve the Butterworth response.707. SOFTWARE REQUIRED: PSPICE Orcad family release 9.2.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem 19. i. Vcc = 15V.

3. In simulation settings select ac sweep and logarithmic scale.305 nF. 2.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem C a + Cb = C 2 Then. Create new simulation profile from Pspice menu.586 = 6.305nF = 3. Save the project and click run and observe the output waveform. PROCEDURE: 1.965 nF. Draw the circuit diagram in the schematic editor. Ca / (Ca +Cb) = 1/K Ca = C2/K C2 = 0. 4.01 × 10-6 / 1. Department of ECE Page 95 . Cb = C2 – 6. Choose the frequency range from 10Hz to 10 KHz.

What do you mean by Linear Wave Shaping? Department of ECE Page 96 . VIVA QUESTIONS: 1. Why RC circuits are preferred over RL circuits for large time constant applications. 5. 6. Explain condition of RC circuit to work as differentiation. Why response of amplifier does not remain flat at all frequencies. What is difference between linear and non-linear wave shaping circuits. What do you mean by a linear network? 8. 2. What is meant by fractional tilt? 4.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem RESULT: Thus the butterworth high pass filter of second order was designed and simulated using PSPICE. 7. What is meant by lower 3-db frequency of high-pass circuit? 3.

16. Why? 11. What is drawback of having diode as shunt element in clipper? 15. Integrators are preferred over the differentiators. 6 7 K R 2 9 1 . CIRCUIT DIAGRAM 0 V 3 1 2 V R 4 5 . What is difference between output from clipping and clamping circuit? 17.1 T D = 0 T R = 0 T F = 0 P W = 0 P E R = 0 V V 2 2 v V 0. 5 M S R = 1V m 1 s = 1 2 V 2 = . 10. For a long time constant RC high pass circuit with a symmetrical square wave input. find the tilt. 6 B C 7 K 1 0 7 A 1 2V V 1 . 9 CK 1 Q B V 1 D C R 5 5 . What is drawback of having diode as series element in clipper? 14. Why RC circuits are commonly used as compared to RL circuits? 12. Why does comparator differ from clipper? 13. Define common-mode rejection ratio. What is the difference between regenerative and non-regenerative comparator.1 2 v V = 0 = 0 = 0 = 0 0. 9 K 2 0 0 P 0 K R 6 1 0 7 A F C 1 1 0 0 P R 1 3 0 K Q 2 F 1 V C 0 V 1 V 2 T D T R T F P W P E = = R 1 9 1 . 18. 5 M 1 m s S Department of ECE Page 97 . Define an ideal differential amplifier.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem 9.

PROCEDURE: 1. SIMULATION OF BISTABLE MULTIVIBRATOR AIM: To simulate the bistable multivibrator circuit and obtain the output waveform using PSPICE. 2. Create a blank project. SOFTWARE REQUIRED: PSPICE Orcad family release 9. then draw the circuit by taking appropriate components and simulate the diagram. Department of ECE Page 98 .2. Observe the output waveforms. 3.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem 20. Go to start  Orcad  capture  New project.

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem RESULT: Thus the bistable multivibrator was designed and simulated using PSPICE. CIRCUIT DIAGRAM: Department of ECE Page 99 .

Department of ECE Page 100 . SOFTWARE REQUIRED: PSPICE Orcad family release 9.2.SIMULATION OF ASTABLE MULTIVIBRATOR AIM: To simulate the astable multivibrator circuit and obtain the output waveform using PSPICE.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem 21.

Create a blank project. Go to start  Orcad  capture  New project. Observe the output waveforms. 3. then draw the circuit by taking appropriate components and simulate the diagram.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem PROCEDURE: 1. MODEL GRAPH: Department of ECE Page 101 . 2.

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem Department of ECE Page 102 .

Department of ECE Page 103 .147451 Electronic Circuits II & Simulation Lab II Yr / IV sem RESULT: Thus the astable multivibrator was designed and simulated using PSPICE.

SIMULATION OF MONOSTABLE MULTIVIBRATOR Department of ECE Page 104 .147451 Electronic Circuits II & Simulation Lab CIRCUIT DIAGRAM II Yr / IV sem 22.

147451 Electronic Circuits II & Simulation Lab AIM: II Yr / IV sem To simulate the monostable multivibrator circuit and obtain the output waveform using PSPICE. MODEL GRAPH: Department of ECE Page 105 . PROCEDURE: 1. Create a blank project. Observe the output waveforms. 3. SOFTWARE REQUIRED: PSPICE Orcad family release 9. Go to start  Orcad  capture  New project. then draw the circuit by taking appropriate components and simulate the diagram. 2.2.

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem Department of ECE Page 106 .

SPECIFICATIONS: Department of ECE Page 107 .147451 Electronic Circuits II & Simulation Lab II Yr / IV sem RESULT: Thus the monostable multivibrator was designed and simulated using PSPICE.

Low Current (max. 100mA) Low Voltage (max. 45 V) For IC = 2mA.147451 Electronic Circuits II & Simulation Lab II Yr / IV sem BC 107 – NPN GENERAL PURPOSE TRANSISTOR FEATURES: . VCE = 5V hfe(min) = 110 hfe(max) = 450 Vbe(min) = 550mV Vbe(typ) = 620mV Vbe(max) = 700mV Department of ECE Page 108 .

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem Department of ECE Page 109 .

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