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problem set 1

problem set 1

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Published by Pradyumn Paliwal
computer architecture
computer architecture

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Published by: Pradyumn Paliwal on Jan 30, 2013
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EC-252: Computer Architecture and Microprocessors

Problem Set 1
Policy for submission of solutions: Submit by 22.01.2012. Late submissions will NOT be evaluated (solutions will be uploaded on 23.01.2012). Solve the problems in A4 sheets and submit all sheets stapled together. There should be one title sheet with the student’s name, class, roll number, serial number, and problem set number.

1. Simplify the following Boolean functions, using 3-variable maps: a. F (x,y,z) = ∑(0,2,6,7) b. F(A,B,C) = ∑ (0,2,3,4,6) 2. Simplify the following Boolean functions, using 4-variable maps: a. w’z + xz + x’y + wx’z b. wxy + yz + xy’z + x’y 3. Simplify the following Boolean function F, together with the don’t-care conditions d, and then express the simplified function in sum of min-terms: a. F(x,y,z) = ∑ (0,1,2,4,5), d(x,y,z) = ∑ (3,6,7) b. F(A,B,C,D) = ∑ (1,3,5,7,9,15), d(A,B,C,D) = ∑ (4,6,12,13) 4. Given the Boolean function F = xy’z + x’y’z + xyz a. List the truth table b. Draw the logic diagram of the original function using 2-input gates c. Simplify the function using Boolean algebra d. List the truth table of the simplified function e. Draw the logic diagram of the simplified function (using 2-input gates) f. Draw the logic diagram of the simplified function using only 2-input NAND gates 5. Implement the following Boolean function together with the don’t-care conditions d, using no more than three NOR gates: F(A,B,C,D) = ∑ (0,1,9,11) d(A,B,C,D) = ∑ (2,8,10,14,15) 6. Derive the circuits for a three-bit parity generator and four-bit parity checker using odd parity bit. 7. Consider the combinational circuit in the figure below. a. Derive the Boolean expressions for T1 through T4. Derive outputs F1 and F2 as function of the four inputs. b. List the truth table (4 variables). Then list T1 through T4, F1 and F2.

Design a binary multiplier that multiplies two 4-bit numbers. Implement the circuit using exclusive-OR gates. 12. f. . The numeric display chosen to represent the decimal digit is shown Figure b. 10. Construct a 4-to-16-line decoder with five 2-to-4 line decoders with enable.c. d. 8. 11. c. as shown in Figure a. g) select the corresponding segments in the display. A BCD-to-seven-segment decoder is a combinational circuit that converts a decimal digit in BCD to an appropriate code for the selection of segments in a display indicator used for displaying the decimal digit in a familiar form. A combinational circuit is defined by the following three Boolean functions: F1 = x’y’z’ + xz F2 = xy’z’ + x’y F3 = x’y’z + xy Design the circuit with a decoder and external gates. Use K-maps to simplify these expressions and show that they are equivalent to the ones obtained in (a). e. The seven outputs of the decoder (a. b. Use AND gates and binary adders. The six invalid combinations should result in a blank display. Design a combinational circuit that converts a 4-bit gray code to a 4-bit binary number. 9. Design this decoder using a minimum number of gates.

Determine the Boolean function that the multiplexer implements. The data inputs I0 through I7. D) = (0. Transitions should be marked based on both inputs x and y. and corresponding circuit using D flip-flops. create the state table. I3 = I5 = 1. 4. An 8 x 1 multiplexer has inputs A. 16. Implement the following Boolean function with a multiplexer: F(A. Construct a 16 x 1 multiplexer with two 8 x 1 and one 2 x 1 multiplexers. B. C. using the convention XY.13. Use block diagram. . 14. I0 = I4 = D. 15) 15. S1. respectively. 9. are as follows: I1= I2 = I7 = 0. From the following state diagram. and I6 = D’. B. 8. Derive the state diagram for the following circuit. 3. 1. Output Z should be encoded in the state. and S0. 17. and C connected to the selection inputs S2.

Design a four bit binary synchronous counter with D flip-flops and logic gates. 22. What is the parity value for the 8bit binary number 10110101? Place the bits into the appropriate places in the parity+data word. 2G x 16 d. Show the Parity bits for a 16-bit and 32-bit number.5.6) B(x.6) C(x. How many address lines and data lines are needed for the following memory? a.2.6.1. 256K x 64 c.y.y. 19. Suggest how to correct this problem.2. 20 x 4 21.4.6.18.z) = Σ(0.7) How big should the ROM be? What is the memory content at addresses 0 and 5? .3. Design a counter which cycles through the binary sequence (1.5. 16K x 8 b. Create the truth table for a ROM that implements the Boolean functions: A(x. Show that when states 000 and 011 are used as don’t care statements the counter may not operate properly.z) = Σ(1.3. 20.y.7) using J/K flipflops.z) = Σ(1.z) = Σ(0.y.5) D(x.

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