# BC0046 – Microprocessor

Assignment Set – 1

Q1.Convert the decimal number 123.145 to octal and hexadecimal.
Decimal to Octal conversion using Repeated Division Method 8 8 8 For absolute part 321 40 1 LSB 5 0 0 5 MSB 321(10) = 501(8) So, 321.145(10) = 501. 221(8) Decimal to Hexadecimal conversion using Repeated Division Method 16 16 1 6 For absolute part 321 20 1 LSB 1 4 0 1 321(10) = 141(16) MSB and 16 16 For fractional part 145 9 1 LSB 0 9 MSB 145(10) = 91(16) 8 8 8 For fractional part 145 18 1 LSB 2 2 0 2 MSB 145(10) = 221(8)

and

So, 321.145(10) = 141. 91(16)

Q2. Write an assembly language program to find the smallest among two numbers.

Program MVI B, 30H MVI C, 40H MOV A, B CMP C JZ EQU JC GRT OUT PORT1 HLT EQU: MVI A, 01H OUT PORT1 HLT GRT: MOV A, C OUT PORT1 HLT

Q3. Draw and explain the internal architecture of 8085.
System Bus Typical system uses a number of busses, collection of wires, which transmit binary numbers, one bit per wire. A typical microprocessor communicates with memory and other devices (input and output) using three busses: Address Bus, Data Bus and Control Bus.

Fig 2.1: Internal Architecture of 8085

Address Bus One wire for each bit, therefore 16 bits = 16 wires. Binary number carried alerts memory to ‘open’ the designated box. Data (binary) can then be put in or taken out. The Address Bus consists of 16 wires, therefore 16 bits. Its “width” is 16 bits. A 16 bit binary number allows 216 different numbers, or 32000 different numbers, ie 0000000000000000 up to 1111111111111111. Because memory consists of boxes, each with a unique address, the size of the address bus determines the size of memory, which can be used. To communicate with memory the microprocessor sends an address on the address bus, eg 0000000000000011 (3 in decimal), to the memory. The memory selects box number 3 for reading or writing data. Address bus is unidirectional, i.e numbers only sent from microprocessor to memory, not other way. Data Bus Data Bus: carries ‘data’, in binary form, between microprocessor and other external units, such as memory. Typical size is 8 or 16 bits. The Data Bus typically consists of 8 wires. Therefore, 28 combinations of binary digits. Data bus used to transmit “data”, ie information, results of arithmetic, etc, between memory and the microprocessor. Bus is bi-directional. Size of the data bus determines what arithmetic can be done. If only 8 bits wide then largest number is 11111111 (255 in decimal). Therefore, larger number have

‘interrupts’. Size of the bus therefore limits the number of possible instructions to 256. Cannot function correctly without these vital control signals.to be broken down into chunks of 255. single binary digit. each specified by a separate number. ‘reset’ etc. This slows microprocessor. . Data Bus also carries instructions from memory to the microprocessor. Eg: Read/NotWrite line. Control Bus Control Bus are various lines which have specific functions for coordinating and controlling microprocessor operations. 0 = Write. Typically microprocessor has 10 control lines. controls whether memory is being ‘written to’ (data stored in mem) or ‘read from’ (data taken out of mem) 1 = Read. May also include clock line(s) for timing/synchronising.

BX. and the segment group. which is a set of special purpose base registers. Except for the instruction register. which is essentially the set of arithmetic registers. . Draw and explain the internal architecture of 8086. counting. or the upper and lower bytes can be accessed separately. CX is used as an implied counter by certain instructions. and I/O roles: BX may be used as a base register in address calculations. There is a data group. The data group consists of the AX. All of the registers are 16 bits wide. the pointer group. which is actually a 6-byte queue. Fig 3. CX and DX registers. respectively.1 shows the internal architecture of the 8086.Q4. For example. These registers can be used to store both operands and results and each of them can be accessed as a whole. CX and DX registers play special addressing.1: Internal Architecture of 8086 In addition to serving as arithmetic registers. Figure 3. but also contains the program counter and stack pointer. the BX. which includes base and index registers. or the upper byte BH or the lower byte BL can be used by itself by specifying BH or BL. either the 2 bytes in BX can be used together. DX is used to hold the I/O address during certain I/O operations. the control unit and working registers are divided into three groups according to their functions.

and the stack.3. beginning at an address that is divisible by 16. Since in 2’s complement negative numbers have a 1 in the MSB and for nonnegative numbers this bit is 0. The condition flags are: SF (Sign FIag)-Is equal to the MSB of the result. which control the execution of special functions. Allows the instruction. which reflect the result of the previous operation involving the ALU. data.Permit a program and/or its data to be put into different areas of memory each time the program is executed. Facilitate the use of separate memory areas for a program. and the segment address multiplied by 16 as the beginning physical segment address. An illustration of the example above is given in Fig.3( a) and the overall segmentation of memory is shown in Fig.e. or stack segment.3 The 8086’s PSW contains 16 bits. The flags are summarized in Fig. 3. 3. or simply. or paragraph.3(b). Allow the memory capacity to be 1 MB even though the addresses associated with the individual instructions are only 16 bits wide. boundary. and the control flags. Each bit in the PSW is called a flag.The utilization of the segment registers essentially divide the memory space into overlapping segments. The advantages of using segment registers are that they: 1. 2. its data. data. . Fig Memory segmentation 3.4. The 8086 flags are divided into the conditional flags. but 7 of them are not used. i. with each segment being 64K bytes long and beginning at a 16byte. We will hereafter refer to the contents of a segment register as the segment address. the beginning segment address.. this flag indicates whether the previous result was negative’ or nonnegative. or stack portion of a program to be more than 64K bytes long by using more than one code. 3.

and a subtraction causes it to be set if a borrow is needed. Other instructions also affect this flag and its value will be discussed when these instructions are defined. CF (Carry Flag)-An addition causes this flag to be set if there is a carry out of the MSB. i. PF (Parity Flag)-Is set to 1 if the low-order 8 bits of the result contains an even number of 1’s. otherwise it is cleared. a result is out of range. As an example. AF (Auxiliary Carry Flag)-Is set if there is a carry out of bit 3 during an addition or a borrow by bit 3 during a subtraction. For subtraction. OF (Overflow Flag)-Is set if an overflow occurs. it is set when the MSB needs a borrow and there is no borrow from the MSB or vice versa. More specifically.. for addition this flag is set when there is a carry into the MSB and no carry out of the MSB or vice versa. if the previous instruction performed the addition 0010 0011 0100 1101 + 0011 0010 0001 0001 0101 0101 0101 1110 then following the instruction: SF=0 ZF=0 PF=0 CF=0 AF=0 OF=0 Fig 3.ZF (Zero Flag)-Is set to 1 if the result is zero and 0 if the result is nonzero. This flag is used exclusively for BCD arithmetic.4: PSW register of 8086 If the previous instruction performed the addition 0101 0100 0011 1001 + 0100 0101 0110 1010 1001 1001 1010 0011 .e.

a certain type of interrupt (a maskable interrupt) can be recognized by the CPU. the string is processed from its beginning with the first element having the lowest address. IF (Interrupt Enable Flag)-If set. these interrupts are ignored. Otherwise. If zero. the string is processed from the high address towards the low address. otherwise. . TF (Trap Flag)-If set.then the flags would be: SF = 1 ZF = 0 PF = 1 CF = 0 AF = 1 CF = 1 The control flags are: DF (Direction Flag)-Used by string manipulation instructions. a trap is executed after each instruction.

15. Write a sequence of instructions to reverse a two digit hexadecimal number available in the register AX using shift and rotate instructions? Fig 4.Q5. CNT. For the . 4.15: Shift and rotate instructions The shift and rotate instructions for the 8086 are defined in Fig. These instructions shift all of the bits in the operand to the left or right by the specified count.

zeroes are shifted into the right end of the operand and the MSBs are shifted out the left end and lost. however. except that the least significant bit of these MSBs is retained in the CF flag. SAR (shift arithmetic right) does not automatically insert zeroes from the left. The rotate instructions differ from the shift instructions in that the operand is treated like a circle in which the bits shifted out of one end are shifted into the other end. it extends the sign of the operand by repeatedly inserting the MSB. The RCL and RCR instructions include the carry flag in the circle and the ROL and ROR do not. The shift right instructions similarly shift bits to the right.shift left instructions. although the carry flag is affected in all cases. .

The general process for creating and executing a program is illustrated in Fig 5. must be linked together to form a load module before the program can be executed. normally the linker prints a memory map that indicates where the linked object modules will be loaded into memory.1: Creation and Execution of a program . Explain the concept of Linking and Relocation. normally the I/O is done by I/O drivers that are part of the operating system.Q6. Linking and Relocation In constructing a program some program modules may be put in the same source module and assembled together. The arrows indicate that corrections may be made after anyone of the major stages. All that appears in the user’s program are references to the I/O drivers that cause the operating system to execute them. but the general concepts are the same. 5. After the load module has been created it is loaded into the memory of the computer by the loader and execution begins. some of which may be grouped into libraries. In addition to outputting the load module. must be terminated by an END statement with the entry point specified. and each of the other modules must be terminated by an END statement with no operand.1. then the main module. In any event. which has the first instruction to be executed. Fig. If they are assembled separately. The process for a particular system may not correspond exactly to the one diagrammed in the figure. Although the I/O can be performed by modules within the program. the resulting object modules. others may be in different source modules and assembled separately.

AT-The AT combine-type is followed by an expression that evaluates to a constant which is to be the segment address. the ASM-86 assembler provides a means of regulating the way segments in different object modules are organized by the linker. The ordering in the concatenation is specified by the linker command. they are combined to form one large stack. COMMON-If the segments in different object modules have the same name and the combine-type is COMMON. Sometimes segments with the same name are concatenated and sometimes they are overlaid. and if it . object modules that are being linked together must be able to refer to each other. In effect. The possible combinetypes are: PUBLIC-If the segments in different object modules have the same name and the combine-type PUBLIC. If an identifier is defined in an object module. Segments that have different names cannot be combined and segments with the same name but no combine-type will cause a linker error. That is. A SEGMENT directive may have the form Segment name SEGMENT Combine-type where the combine-type indicates how the segment is to be located within the load module.Segment Combination In addition to the linker commands. there must be a way for a module to reference at least some of the variables and/or labels in the other modules. then it is said to be a local (or internal) identifier relative to the module. Just how the segments with the same name are joined together is determined by modifiers attached to the SEGMENT directives. It allows the user to specify the exact location of the segment in memory. Access to External Identifiers Clearly. If more than one segment with the MEMORY combine type is being linked.. the others will be overlaid as if they had COMMON combine types. MEMORY-This combine-type causes the segment to be placed at the last of the load module. The length of the common segment is that of the longest segment being overlaid. then they become one segment whose length is the sum of the lengths of the individually specified segments. STACK-If segments in different object modules have the same name and the combine-type STACK. then they are overlaid so that they have the same beginning address. only the first one will be treated as having the MEMORY combine-type. then they are concatenated into a single segment in the load module.

each module may contain two lists. the given module must include a list of the identifiers to which it will allow access. 5. . then there will be an undefined external reference and a linker error will occur. . Because the assembler must know the type of all external identifiers before it can generate the proper machine code. .VAR1…. . one containing the external identifiers it references and one containing the locally defined identifiers that can be referred to by other modules. . Identifier:Type and PUBLIC Identifier.. . If this is not the case. Identifier where the identifiers are the variables and labels being declared as external or as being available to other modules. then the module containing the statement must also contain a directive such as EXTRN . VAR1 :WORD.. . . For single-object module programs all identifiers that are referenced must be locally defined or an assembler error will occur. For multiple-module programs. These two lists are implemented by the EXTRN and PUBLIC directives. in order to permit other object modules to reference some of the identifiers in a given module. the assembler must be informed in advance of any externally defined identifiers that appear in a module so that it will not treat them as being undefined. One of the primary tasks of the linker is to verify that every identifier appearing in an EXTRN statement is matched by one in a PUBLIC statement.is not defined in the module but is defined in one of the other modules being linked. For a variable the type may be BYTE. which have the forms: EXTRN Identifier:Type.. or DWORD and for a label it may be NEAR or FAR.. In the statement INC VAR1 if VAR1 is external and is associated with a word. . . . Fig. Also. . then It is referred to as an external (or global) identifier relative to the module. WORD. Therefore. a type specifier must be associated with each identifier in an EXTRN statement. and the module in which VARl is defined must contain a statement of the form PUBLIC .2 shows three modules and how the matching is done by the linker while joining them together.

an offset and a segment address. but the offsets for the external identifiers and all segment addresses must be inserted by the linking process.2: Illustration of the matching verified by the linker As we have seen. . 5. The offsets for the local identifiers can be and are inserted by the assembler. there are two parts to every address.Fig. The assignment of the segment addresses is called relocation and is done after the king process has determined exactly where each segment is to be put in memory. The offsets associated with all external references can be assigned once all of the object modules have been found and their external symbol tables have been examined.

0 . to call a procedure the use of a directive is required.there are other programming languages which do allow it. Ah Mov Ah. Content of the procedure Mov B1. Example of procedure: For example. Ax Ret .Q7. on the other hand the call of macros is done as if it were an assembler instruction. Row MOV DL. and keep the addition in the BX register: Adding Proc Near . Column MOV BH. 02H MOV DH. End of procedure declaration and an example of Macro: Position MACRO Row. this is only applicable for the MASM . At the moment the macro is executed each parameter is substituted by the name or value specified at the time of the call. while the macro is a module with specific functions which can be used by different programs. Another difference between a macro and a procedure is the way of calling each one. The main difference between a macro and a procedure is that in the macro the passage of parameters is possible and in the procedure it is not. Column PUSH AX PUSH BX PUSH DX MOV AH. A macro is a group of repetitive instructions in a program which are codified only once and can be used as many times as necessary. 0 INT 10H POP DX . 00 Add Bx. We can say then that a procedure is an extension of a determined program. if we want a routine which adds two bytes stored in AH and AL each one. Differentiate macros and procedures. Return directive Add Endp . Declaration of the procedure Mov Bx.

POP BX POP AX ENDM .

logic and data transfer One number must be in AL or AX Multiplication & Division Input & Output BX .the accumulator register (divided into AH / AL): 1. Count (in CL) of bits to shift and rotate DX . Can be used for pointer addressing of data 2. Iterative code segments using the LOOP instruction 2. 4. Primarily used to access parameters passed via the stack 2.Q9. Offset address relative to DS DI . 3. 5. Offset address relative to ES BP . Generates shortest machine code Arithmetic. Repetitive operations on strings with the REP command 3.the base address register (divided into BH / BL). each register has its own name: AX .the count register (divided into CH / CL): 1.base pointer: 1. Offset address relative to SS SP . CX . Can be used for pointer addressing of data 2. 8086 CPU has 8 general purpose registers.destination index register: 1. Used as destination in some string processing instructions 3.stack pointer: . Specifying ports in some IN and OUT operations SI . Used as source in some string processing instructions 3. Describe about each flag of a 8086 flag register. DX:AX concatenated into 32-bit register for some MUL and DIV operations 2.the data register (divided into DH / DL): 1.source index register: 1. 2.

pointing at accessible blocks of memory. SS .1. Also. which is limited to 16 bit values. This way we can access much more memory than with a single register.generally points at segment where variables are defined. Offset address relative to CS IP register always works together with CS segment register and it points to currently executing instruction. For example if we would like to access memory at the physical address 12345h (hexadecimal). Always points to next instruction to be executed 2. Other general purpose registers cannot form an effective address. Always points to top item on the stack Offset address relative to SS Always points to word (byte at even address) An empty stack will had SP = FFFEh SEGMENT REGISTERS CS . ES . 4.points at the segment containing the stack. . BH and BL cannot.extra segment register. SI and DI registers work with DS segment register. By default BX. 3.the instruction pointer: 1. The CPU makes a calculation of the physical address by multiplying the segment register by 10h and adding the general purpose register to it (1230h * 10h + 45h = 12345h): The address formed with 2 registers is called an effective address.points at the segment containing the current program. BP and SP work with SS segment register. 2. SPECIAL PURPOSE REGISTERS IP . although BX can form an effective address. DS . The segment registers have a very special purpose . Segment registers work together with general purpose register to access any memory value. it's up to a coder to define its usage. Although it is possible to store any data in the segment registers. we could set the DS = 1230h and SI = 0045h. this is never a good idea.

when this flag is set to 0 . For example. When result is positive it is set to 0.this flag is used by some instructions to process data chains. 3. 5. 9. 8.set to 1 when result is negative.this flag is set to 1 when there is even number of one bits in result.. Zero Flag (ZF) .determines the current state of the processor..set to 1 when there is an unsigned overflow for low nibble (4 bits). Parity Flag (PF) .set to 1 when there is a signed overflow. when this flag is set to 1 the processing is done backward. Generally you cannot access these registers directly. Direction Flag (DF) .Used for on-chip debugging. 4. 1. 2. and to determine conditions to transfer control to other parts of the program. Trap Flag (TF) .set to 1 when result is zero. Sign Flag (SF) . Interrupt enable Flag (IF) .127).when this flag is set to 1 CPU reacts to interrupts from external devices.. They are modified automatically by CPU after mathematical operations. and to 0 when there is odd number of one bits. Carry Flag (CF) . . When there is no overflow this flag is set to 0. this allows to determine the type of the result. Overflow Flag (OF) ..255). For example when you add bytes 255 + 1 (result is not in range 0. (This flag takes the value of the most significant bit.) 6.this flag is set to 1 when there is an unsigned overflow.FLAGS REGISTER Flags Register . Auxiliary Flag (AF) .the processing is done forward. 7. when you add bytes 100 + 50 (result is not in range -128. For non-zero result this flag is set to 0.

Write an assembly program to add and display two numbers. 8BH MVI C.Q10. C ADD D OUT PORT1 HLT . Program MVI D. 6FH MOV A.

They are only 1 byte long. which cannot perform a memory-to-memory transfer. the advantages of the MOVS and CMPS instructions over the MOV and CMP instructions are: 1. is shown in Fig. When working with strings. what are the advantages of the MOVS and CMPS instructions over the MOV and CMP instructions? When working with strings.2(a). A solution that uses only the MOV instruction.BC0046 – Microprocessor Assignment Set – 2 Q2. 3. Fig. Both operands are memory operands.2: Program sequences for moving a block of data . thus decreasing overall processing time. 6. 6. Their auto-indexing obviates the need for separate incrementing or decrementing instructions. 2. As an example consider the problem of moving the contents of a block of memory to another area in memory.

depending on the type of STRING1 and STRING2.2(b). 6.A solution that employs the MOVS instruction is given in Fig. . Note that the second program sequence may move either bytes or words.

there is less than 5 microseconds to transfer each byte to or from memory. but other specially designed components can gain control of the bus by sending a bus request to the CPU. The 8086 receives bus requests through its HOLD pin and issues grants from its hold acknowledge (HLDA) pin. Normally. A request is made when a potential master sends a 1 to the HOLD pin. Taking control of the bus for a bus cycle is called cycle stealing. Explain the working of DMA. Some devices. then the communication can be performed using either programmed or interrupt I/O. such as magnetic tape and disk units and analog to-digital converters. and the computer must be capable of executing I/O according to the maximum speed of the device. block transfers. When the requesting device receives this grant signal it becomes the master. but they are often designed to accommodate more than one interface. not the CPU. then two bus cycles are required to complete the transfer and a grant will not be issued until after the second bus cycle. are required. which use DMA controllers to communicate directly with memory. Thus. a master must be capable of placing addresses on the address bus and directing the bus activity during a bus cycle. may operate at data rates that are too high to be handled by byte or word transfers. Just like the bus control logic. . one of the system components connected to the system bus is given control of the bus. Sometimes a DMA controller is associated with a single interface. After the current bus cycle is completed the CPU will return a bus grant signal and the component sending the request will become the master. One exception to the normal sequence is that if a word which begins at an odd address is being accessed. after the current bus cycle is complete the 8086 will respond by putting a 1 on the HLDA pin. The components capable of becoming masters are processors (and their bus control logic) and DMA controllers. If the data transfer rate to or from an I/O device is relatively low. For a disk unit the data rate is determined by the speed with which data pass under the read/write head and quite often this rate exceeds 200. For data rates of this magnitude. at which time the 8086 will drop the grant on the HLDA pin. This component is said to be the master during that cycle and the component it is communicating with is said to be the slave. During any given bus cycle. Data rates for I/O and mass storage devices are often determined by the devices. It will remain master until it drops the signal to the HOLD pin.Q3.000 bytes per second. The CPU with its bus control logic is normally the master.

This is all right if no other processing could be done while the input is taking place. . Interrupt is an event that causes the CPU to initiate a fixed sequence.99% 100. and the return address is the location of the REP prefix. because the prefix is considered as part of the instruction. known as an interrupt sequence. this allows the contents of both a segment register and a pointer to be changed without interruption. then a different approach is needed. In the above example. if the person typing on the terminal could type 10 characters per second and only 10 μs is required for the computer to input each character. otherwise. it can waste a considerable amount of time while waiting for ready bits to become active.7.Q4. but if other processing is unnecessarily delayed. the interrupt request is recognized after the primitive operation following the REP is completed. a line feed is to be automatically appended to the carriage return Interrupt IO Even though programmed I/O is conceptually simple. the currently executing instruction must be completed unless the current instruction is a HLT or WAIT instruction. As a more complete example.990 x 100% = 99. A typical programmed input operation is flowcharted in Fig. then approximately 99. suppose that a line of characters is to be input from a terminal to an 82-byte array beginning at BUFFER until a carriage return is encountered or more than 80 characters are input. In the case of the REP instruction. an interrupt request is not recognized until after the instruction following the MOV or POP instruction is executed.000 of the time is not being utilized. If a carriage return is not found in the first 81 characters then the message “BUFFER OVERFLOW” is to be output to the terminal. For MOV and POP instructions in which the destination is a segment register. the interrupt request is not recognized between the prefix and the instruction. . Before an 8086 interrupt sequence can begin. For a prefixed instruction.3. Write short notes on (i) programmed I/O and (ii) Interrupt I/O Programmed IO Programmed I/O consists of continually examining the status of an interface and performing an I/O operation with the interface when its status indicates that it has data to be input or its data-out buffer register is ready to receive data from the CPU. Provided that the segment register is filled first.

e.Q5. Explain about the semaphore operations. A serially reusable resource may be a hardware resource (such as a printer. let us consider a personnel file that is shared by processes 1 and 2. if both processes were allowed to access the file at the same time. Semaphore Operations In multiprogramming systems. card reader. However. For example. which is commonly referred to as a serially reusable resource. .. and process 2 puts the file in alphabetical order according to last names. A resource of this type. must be protected from being simultaneously accessed and modified by two or more processes. that section of code that accesses the serially reusable resource. The solution to this problem is to allow only one process at a time to enter its critical section of code. processes are allowed to share common software and data resources as well as hardware resources. To examine how this is done and some of the problems associated with this approach let us consider the possibility of using only one flag. or a shared memory area. One way to attain mutual exclusion is to use flags to indicate when the shared resource is already in use. a common resource may be accessed and updated by only one process at a time and other processes must wait until the one currently using the shared resource is finished with it. Preventing two or more processes from simultaneously entering their critical sections for accessing a shared resource is called mutual exclusion. the results would be unpredictable and almost certainly incorrect. deletions. a file of data. or vice versa. If accessed sequentially. Suppose that process 1 performs insertions. and changes. or tape drive). i. this file would either be updated by process 1 and then sorted by process 2. In many situations.

which is the address sent to the memory by the memory management hardware. In other words. also called a virtual space. Fig. Logical addresses are the addresses that are generated by the instructions according to the addressing modes. each logical address consists of two fields.8. the user can design a program in a logical space. a user “virtually” has more memory to work with than actually exists. First.6. Second. without consideration for the limitations imposed by the real memory. a program need not occupy a contiguous memory section. Therefore. memory fragmentation is reduced and less memory space is wasted. the segment number and the offset within the segment. and then resume the program’s execution. This allows a program’s size to be larger than the actual memory available. 8. dividing a program into several pieces with each mapped into an area in real memory. This provides two major advantages.Q6. Explain what a virtual memory is? Virtual Memory The more sophisticated memory management scheme can be achieved by the hardware dynamic address translation design illustrated in Fig. Whenever a portion of the program that is not currently in memory is referenced.6: Dynamic Address Translation Because the logical addresses may be different from the physical addresses. load in the required section of code. The number of bits representing the segment number governs the maximum number of segments allowed . the operating system can suspend the program. the program is divided into segments according to the logical structure of the program and the resulting memory management scheme is called segmentation. With address translation hardware. the logical address output by the CPU is translated into the physical address. When using segmentation. For each memory reference. it is not necessary to store the entire program in memory while it is executing.

8. either the entire segment table or that portion of the table containing the beginning addresses of the segments that are currently in use must be stored in registers which are part of the memory management hardware. the segment table register is updated to point to a new section of the segment table. The most common of these additional attributes are the. respectively. For example. a program may have up to 2m segments. which returns the beginning physical address X of the referenced segment. and the number of bits allocated to the offset specifies the maximum segment size. Depending on . the base address of that section of the segment table that is associated with the currently executing job is stored in a register called the segment table register. with each segment having a maximum size of 2n bytes.7 illustrates the mapping of logical addresses into physical addresses.in a program. if the segment number and offset have m and n bits. When the system switches from one job to another. Fig. The index S is made relative to the segment table register. Because each job may be assigned a separate area in the segment table. Because the address translation must be performed for every memory reference. Fig. a segment descriptor may include attributes in addition to the beginning segment address. 8. Each entry in the segment table is referred to as a segment descriptor.7: Segmentation Scheme The segment number S in a logical address is used as an index into the segment table.: . thus providing each user with a virtual storage of 2m+n bytes.the particular implementation. This address added to the offset L to form the physical address of the memory location.

Protection Field-Provides protection against unauthorized reading. writing. . Change field : Indicates whether or not the segment has been modified since being brought into memory . or execution.Status Field-Indicates whether or not the referenced segment is in the memory. Reference Field-Provides useful information in determining which segment is to be replaced. Segment Length Field-Indicates the size of the segment.

e. and P2 is an optional connector consisting of 60 auxiliary lines. these assumptions become formalized and constitute what is referred to as a bus standard The Intel MULTIBUS has gained wide industrial acceptance and several manufacturers offer MULTIBUS-compatible modules. At any point in time. and low cost. are built around a primary system bus which connects all of the major components in the system. . most microcomputers.13: Illustration of a module being plugged into MULTIBUS The P1 lines can be divided into the following groups according to their functions: 1. including those involving multiprocessor configurations. This bus is designed to support both 8-bit and 16-bit devices and can be used in multiprocessor systems in which several processors can be masters. a microcomputer manufacturer makes assumptions about the bus that is to be used to connect its devices together Frequently. Address lines. primarily used for power failure detection and handling. denoted PI and P2. 9. 9. only two devices may communicate with each other over the bus.Q8.. The master/slave relationship is dynamic with bus allocation being accomplished through the bus allocation (i. flexibility. The MULTIBUS has been physically implemented on an etched backplane board which is connected to each module using two edge connectors. request/grant) control signals. Explain the 8288 Bus controller.13. I shown in Fig. For reasons of simplicity. The connector P1 consists of 86 pins which provide-the major bus signals. In order to obtain a foundation while designing its products. one being the master and the other the slave. Fig.

. one may want to permit nonstandard MULTIBUS transfers between memory and an 8086. 3. Data transfers on the MULTIBUS bus are accomplished by handshaking signals in a manner similar to that described in the preceding sections. Command and handshaking lines. and auxiliary ROM in a common address space.e. There are 16 bidirectional data lines ( ). when the monitor is in control. I/O read ( ). If control is passed to the user.2. only eight of which are used in an 8-bit system. to verify the end of a transfer. where the numeric suffix represents the address bit in hexadecimal.) The two inhibit signals are provided for overlaying RAM. and I/O write ( ) lines are defined to be the same as they were in the discussion of the 8288 bus controller. memory write ( ). a bootstrap loader may be stored in an auxiliary ROM and a monitor in a ROM. could be raised while remains low. (It should be pointed out that because an 8086 expects a byte to be put on the high-order byte of the bus when is active. and could both be deactivated. The memory read ( ). Because a master must wait to be notified of the completion transfer. The MULTIBUS standard calls for all single bytes to be communicated over only the lower 8 bits of the bus.Then. The MULTIBUS has 20 address lines. i. and could both be activated while the loader is executing. Because the loader is needed only after a reset. For example. Data lines. This asynchronous nature enables the system to handle slow devices without penalizing fast devices . 4. thus allowing the RAM to fill the entire memory space during normal operation. labeled through . The address lines are driven by the bus master to specify the memory location or I/O port being accessed. therefore.. 5. the duration of a bus cycle varies depending on the speed of the bus master and the slave. Utility lines. Bus access control lines. any 16-bit interface must include a swap byte buffer so that only the lower data lines are used for all byte transfers. ROM. There is an acknowledge ( ) signal which serves the same purpose as the READY signal in the discussion of the bus control logic. In a general setting it may be received by bus master.

The 8087 Numeric Data Processor The 8087 numeric data processor (NDP) is specially designed to perform arithmetic operations efficiently. and so on. taking the tangent. As an example of its computing power. respectively. multiplication. such as taking the square root. Draw the block diagram of 8087. The 8087 provides a simple and effective way to enhance the performance of an 8086 based system. decimal. but also provides many useful functions. and division. the 8087 can multiply two 64-bit real numbers in about 27 μs and calculate a square root in about 36 μs. It can operate on data of the integer. and real types. The instruction set not only includes various forms of addition. subtraction. exponentiation.3. If performed by the 8086 through emulation. . particular when an application is primarily computational in nature. with lengths ranging from 2 to 10 bytes. A pin diagram of the 8087 is shown in Fig.Q9. the same operations would require approximately 2 ms and 20 ms. 10.

3: 8087 pin diagram The address/data. 10. and the / could be connected to the bus request/grant pin of an independent processor such as an 8089. the INT pin to the management logic (assuming the 8087 is enabled for interrupts). Among the remaining eight pins.Fig. status ready. ground. four of them are not used. The other pins are connected as follows: the BUSY pin to the host’s interrupt pin. reset. which consists of an 8086/8088 and an 8087. clock. . the / pin to the host’s / or / pin. This simple interface allows an existing maximum mode 8086-based system to be easily upgraded by replacing the original CPU with a piggyback module. and power pins of the NDP have the same pin positions as those assigned to the 8086/8088.

but by using an Intel 8087 numeric data processor as a coprocessor. The interaction between the CPU and the coprocessor when an instruction is executed by the coprocessor is depicted in Fig. Other than possibly fetching an operand for the coprocessor. the CPU does not need to take any further action if the instruction is executed by the coprocessor. It will be seen that. indicating what the coprocessor is to do and is simultaneously decoded by both the coprocessor and the host.1. which is written in a superset of the 8086 instruction set. At this point the host may simply go on to the next instruction or it may fetch the first word of a memory operand for the coprocessor and then go on to the next instruction. their instruction set is not sufficient to effectively satisfy some complex applications. Only the host CPU can fetch instructions. Both the CPU and coprocessor execute their instructions from 1M same program.10.Q10. the 8086 has no instructions for performing floating point arithmetic. but the coprocessor also receives all instructions and monitors the instruction sequencing of the host. except for the coprocessor itself. Although the 8086 is a powerful single-chip microprocessors. Explain why the processor utilization rate can be improved in a multiprocessor system by an instruction queue. the 8086 must be supplemented with coprocessors that extend the instruction set in directions that will allow the necessary special computations to be accomplished more efficiently. a coprocessor design does not require any extra logic other than that normally needed for a maximum mode system. An instruction to be executed by the coprocessor is indicated when an escape (ESC) instruction appears in the program sequence. An ESC instruction contains an external operation code. For such applications. For example. the coprocessor will capture the data word and its 20-bit physical address. . an application that heavily involves floating point calculations can be readily satisfied. If the CPU fetches the first word of an operand.

Fig. In either case.Both the host and the coprocessor share the same clock generator and bus control logic. 10. An ESC assembler language instruction has two operands. the 8086 will fetch a word from this location for the coprocessor and may pass the coprocessor an address for storing a result. At that time the host should execute a WAIT instruction and wait until its pin is activated by the coprocessor. the coprocessor ignores the data word fetched by the host and later the coprocessor will store the result into the captured address. which determines the action to be taken by the coprocessor. If the second operand specifies a memory location. If the memory operand specified in the ESC instruction is a destination. 10. It is. The WAIT instruction repeatedly checks the pin until it becomes activated and then executes the next instruction in sequence. the coprocessor will send a busy (high) signal to the host’s pin and. as the host continues processing the instruction stream.2. the coprocessor can obtain the remaining words by stealing bus cycles. the coprocessor will perform the operation indicated by the code in the ESC instruction. If the second operand is a register. then as explained above. possible to . The first of two operands indicates the external opcode. The interfacing of a coprocessor to a host CPU is shown in Fig. This parallel operation continues until the host needs the coprocessor to perform another operation or must have the results from the current operation. the register address is treated as part of the external op code and the CPU does nothing.1: Synchronization between 8086 and its coprocessor For a source operand that is longer than one word.

For the most part parallel lines can be used to connect the host to its coprocessors. For two coprocessors. if it is preceded by a branch instruction. Because instructions are prefetched by the CPU. In order for a coprocessor to determine when the host is executing an ESC instruction.lines and the ADl5-AD0 lines for fetched instructions.have two coprocessors connected to the same host CPU. it might not be executed at all. the coprocessors must be assigned distinct subsets of the set of external opcodes and each coprocessor must be able to recognize and execute the members of its subset. . one could use the / pin on the 8086 and the other could use the / pin. an ESC instruction might not be executed immediately or. The two coprocessors would be connected to separate 8259A interrupt request pins. When this is done. it must monitor the host CPU’s status on the .

it will compare the five MSBs of the first byte in the queue to 11011. then an ESC instruction is ready to be executed and. The queue status 10 indicates that the queue in the host is being flushed and. therefore. If there is a match. but if it is 01. If the queue’s status is 00. The 11 status combination indicates that the first byte in the queue is not the .Fig. this byte is ignored and is deleted from the queue. the coprocessor does nothing. it will perform the indicated operation. 10. otherwise. assuming that the coprocessor recognizes the external opcode.2: Coprocessor configurarion The coprocessor must track the instruction stream by monitoring the queue status bits QS1 and QS0 and maintaining an instruction queue identical to that of the host. causes the queue in the coprocessor to also be emptied.

If not part of an ESC instruction. .first byte of an instruction and this byte is looked at by the coprocessor only / if it is known to be part of an ESC instruction. it will send out an interrupt request (which is normally sent to an 8259A). this byte is ignored. Last. ? The coprocessor should be designed so that when an error occurs during the decoding or execution of an ESC instruction. The coprocessor should also be designed so that it can steal bus cycles by making bus requests through one of the host’s pins when additional data must be read from or stored in memory. the coprocessor must be able to apply a high signal to the host’s pin while it is busy.