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group8_trafficlight

group8_trafficlight

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Published by Trang Pham
EE471
Trafficlight matlab code
EE471
Trafficlight matlab code

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Published by: Trang Pham on Feb 03, 2013
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11/22/2015

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DaNang university of technology

***************

EE 271 LAB 3 (trafficlight)

Group 8

Member Pham Thi Trang Ong Thi Hoang Anh Duong Viet Le Ngoc Tan

*************DaNang 2012************

Lab 3 Part 1: Traffic light
Block Diagram

Code:
//creates slowly clock signal module clock_design (clk, clk_out, clr); input clk, clr; output clk_out; parameter which_clock = 1; reg [31:0] divided_clocks = 0; always @(posedge clk or posedge clr) if (clr) divided_clocks=0; else divided_clocks = divided_clocks + 1; assign clk_out = divided_clocks[which_clock]; endmodule

// checking X and delayFlag. If delayFlag=1, set state for output module sensor(out,delayFlag,X,clr); output reg [5:0] out; input X,clr,delayFlag; reg [1:0] state; parameter [1:0] S0=2'd0, S1 = 2'd1, S2=2'd2, S3=2'd3; always@(posedge delayFlag or posedge clr) begin if(clr)

begin state = S0; out = 6'b100001; end else if(delayFlag) begin case(state) S0: if(X) begin state = S1; out = 6'b010001; end S1: begin state = S2; out = 6'b001100; end S2: if(X==0) begin state = S3; out = 6'b001010; end S3: begin state = S0; out = 6'b100001; end default: begin state = S0; out = 6'b100001; end endcase end end endmodule // sets the time for delaying among above states module set_time(out, delayTime, X, clr); output reg [3:0] delayTime; input [5:0] out; input X, clr; always@(out) begin if(clr) delayTime=0; else begin

case(out) 6'b100001: if (X==1) delayTime = 3; else delayTime = 0; 6'b010001: delayTime = 6; 6'b001100: delayTime = 9; 6'b001010: delayTime = 3; default: delayTime = 20; endcase end end endmodule /*takes the value of time from set_time for counting. When counter equal to needed value of time, setting delayFlag =1. Moreover, module delay will create input (led1, led 2) for led_counter*/ module delay(delayTime, delayFlag,clr,clock_out, Led_Out_1, Led_Out_2); output reg delayFlag; output [0:6] Led_Out_1, Led_Out_2; input clr, clock_out; reg[3:0] counter = 0; reg [3:0] led1, led2; input [3:0] delayTime; always@(posedge clock_out, posedge clr) begin if(clr) begin counter = 0; delayFlag = 0; led1 = 0; led2 = 0; end else begin if(counter < delayTime) begin counter = counter + 1'b1; delayFlag = 0; led1[3:0] = (delayTime -counter+1)/10; led2[3:0] = (delayTime -counter+1)%10; end else begin counter = 0; delayFlag = 1; led1[3:0] = 0; led2[3:0] = 0; end

end end led_counter leds1(led1, Led_Out_1); led_counter leds2(led2, Led_Out_2); endmodule // decode 4 -> 7 to perform state of 7 segments led . module led_counter(led,Led_Out); input [3:0]led; output reg [0:6] Led_Out; always@(led) case(led) 4'd0: Led_Out = 7'b0000001;//0 4'd1: Led_Out = 7'b1001111;//1 4'd2: Led_Out = 7'b0010010;//2 4'd3: Led_Out = 7'b0000110;//3 4'd4: Led_Out = 7'b1001100;//4 4'd5: Led_Out = 7'b0100100;//5 4'd6: Led_Out = 7'b0100000;//6 4'd7: Led_Out = 7'b0001111;//7 4'd8: Led_Out = 7'b0000000;//8 4'd9: Led_Out = 7'b0000100;//9 default: Led_Out = 7'b1111111; endcase endmodule // the combination of above modules module trafficlight (clk, clr, X, out, Led1,Led2); input clk, clr, X; output wire[5:0] out; wire delayFlag; wire [4:0] delayTime; output [0:6] Led1,Led2; clock_design dut1(clk, clk_out, clr); set_time dut2(out, delayTime, X, clr); delay dut3(delayTime, delayFlag,clr,clk_out, Led1,Led2); sensor dut4(out, delayFlag, X, clr);

endmodule

TestBench:
TestBench for delay module module testdelay; wire delayFlag; wire [0:6] Led_Out_1, Led_Out_2; reg clr, clock_out; reg [3:0] delayTime; delay testd(delayTime, delayFlag,clr,clock_out, Led_Out_1, Led_Out_2);

initial begin clr=1; clock_out=1;delayTime=1; #4 clr=0; delayTime=3; #8 delayTime=5; #12 delayTime=7; $finish; end always #1 clock_out = !clock_out; endmodule TestBench for clock_design module module clock_design_tb; reg clk_in_tb, clr; initial begin clr=1;clk_in_tb = 1; #3 clr=0; #300 clr=1; #5 clr=0; end always begin: CLOCK_GENERATOR #1 clk_in_tb = ~clk_in_tb; end clock_design myClock(clk_in_tb, clk_out_tb, clr); endmodule TestBench for ledcase module module testledcase; reg [3:0]a; wire [0:6]b; integer k; led_counter testled(a, b); initial begin a=0; for (k = 1; k <=9 ; k = k+1) #15 a = k; end endmodule TestBench for sensor module module testsensor; wire [5:0] out; reg X,clr,delayFlag; sensor tra2(out,delayFlag,X,clr); initial begin clr=1; X=0;delayFlag=0; #2 clr=0;

#3 X=1; #7 X=0; $finish; end always #1 delayFlag = !delayFlag; endmodule TestBench for time_set module module tsettime; wire [3:0] delayTime; reg [5:0] out; reg X, clr; set_time set(out, delayTime, X, clr); initial begin X=1;out=6'b100001;clr=0; #5 out=6'b010001; #5 out=6'b001100; clr=1; #5 out=6'b001010; clr=0; #5 X=0; #5 out=6'b100001; $finish; end endmodule TestBench for main module module TestBenchmain; reg clk, clr, X; wire[5:0] out; wire[0:6] Led1,Led2; wire delayFlag; wire [3:0] delayTime; wire clk_out; clock_design dut1(clk, clk_out, clr); set_time dut2(out, delayTime, X, clr); delay dut3(delayTime, delayFlag,clr,clk_out, Led1,Led2); sensor dut4(out, delayFlag, X, clr); initial begin clr=0;clk=1; X=1; #4 clr=0; #2 X=1; #220 clr=1; #10 clr=0; #180 X=0; #20 X=0; $finish; end

always #1 clk=!clk; endmodule

Simulation Report:
By writing TestBench on ModelSim: For clk_design(which_clock=4)

For led_counter

For delay module

For sensor module

For time_set module

For main module

First, when clr=0 and X=1, the seg-7-led begins counting from 03 to 00. At 00, the traffic changes to the next state S1 (010001) and the seg-7-led begins counting 05, …, 01, and 00. After finishing counting, the traffic changes to state S2 and starts counting 09, …, 00

In state S2, when it finishes counting, the sensor will check X. If X is 1, the traffic does not change state and start counting again.

Clr = 1, all led return to the initial state and stop counting

Finally, when X=0, the traffic changes to state S3 and then return to state S0.

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