# May 2012 Bachelor of Computer Application (BCA) – Semester 3 BC0046 – Microprocessor – 4 Credits (Book ID: B0807) Assignment Set – 1 (60 Marks

) Submitted by: Deepak Kumar

Q1. Convert the decimal number 231.23 to octal and hexadecimal. Answer: 231.23 ~= 11100111.001110 in binary. To get the hexadecimal or octal representation, group the bits by three or four, aligned at the decimal point: 231.23 ~= 11100111.001110 in binary 11 100 111. 001 110 = 347.16(+-0.01) in octal 1110 0111. 0011 10 = E7.38(+-0.04) in hexadecimal Q2. Draw and explain the internal architecture of 8085. System Bus Typical system uses a number of busses, collection of wires, which transmit binary numbers, one bit per wire. A typical microprocessor communicates with memory and other devices (input and output) using three busses: Address Bus, Data Bus and Control Bus.

Fig 2.1: Internal Architecture of 8085 Address Bus One wire for each bit, therefore 16 bits = 16 wires. Binary number carried alerts memory to „open‟ the designated box. Data (binary) can then be put in or taken out. The Address Bus consists of 16 wires, therefore 16 bits. Its “width” is 16 bits. A 16 bit binary number allows 216 different numbers, or 32000 different numbers, ie 0000000000000000 up to 1111111111111111. Because memory consists of boxes, each with a unique address, the size of the address bus determines the size of memory, which can be used. To communicate with memory the microprocessor sends an address on the address bus, eg 0000000000000011 (3 in decimal), to the memory. The memory selects box number 3 for reading or writing data. Address bus is unidirectional, i.e numbers only sent from microprocessor to memory, not other way. Data Bus

Data Bus: carries „data‟, in binary form, between microprocessor and other external units, such as memory. Typical size is 8 or 16 bits. The Data Bus typically consists of 8 wires. Therefore, 28 combinations of binary digits. Data bus used to transmit “data”, ie information, results of arithmetic, etc, between memory and the microprocessor. Bus is bi-directional. Size of the data bus determines what arithmetic can be done. If only 8 bits wide then largest number is 11111111 (255 in decimal). Therefore, larger number have to be broken down into chunks of 255. This slows microprocessor. Data Bus also carries instructions from memory to the microprocessor. Size of the bus therefore limits the number of possible instructions to 256, each specified by a separate number. Control Bus Control Bus are various lines which have specific functions for coordinating and controlling microprocessor operations. Eg: Read/NotWrite line, single binary digit. controls whether memory is being „written to‟ (data stored in mem) or „read from‟ (data taken out of mem) 1 = Read, 0 = Write. May also include clock line(s) for timing/synchronising, „interrupts‟, „reset‟ etc. Typically microprocessor has 10 control lines. Cannot function correctly without these vital control signals.

or the upper byte BH or the lower byte BL can be used by itself by specifying BH or BL. There is a data group. CX and DX registers play special addressing. and I/O roles: BX may be used as a base register in address calculations. Figure 3. CX is used as an implied counter by certain instructions. which includes base and index registers. These registers can be used to store both operands and results and each of them can be accessed as a whole. CX and DX registers. but also contains the program counter and stack pointer. The data group consists of the AX. which is a set of special purpose base registers. which is actually a 6-byte queue. and the segment group.Q3.1: Internal Architecture of 8086 In addition to serving as arithmetic registers. counting. Except for the instruction register. which is essentially the set of arithmetic registers.1 shows the internal architecture of the 8086. BX. the BX. or the upper and lower bytes can be accessed separately. For example. Fig 3. Draw and explain the internal architecture of 8086. the control unit and working registers are divided into three groups according to their functions. All of the registers are 16 bits wide. either the 2 bytes in BX can be used together. the pointer group. . respectively.

Allow the memory capacity to be 1 MB even though the addresses associated with the individual instructions are only 16 bits wide. and the segment address multiplied by 16 as the beginning physical segment address. We will hereafter refer to the contents of a segment register as the segment address." e. (IP) means the contents of IP. data.. Allows the instruction. data. its data. and the stack. boundary. 3.2 Generation of physical Address The utilization of the segment registers essentially divide the memory space into overlapping segments. or stack portion of a program to be more than 64K bytes long by using more than one code.] Fig.g.. 3.Permit a program and/or its data to be put into different areas of memory each time the program is executed. Also. An illustration of the example above is given in Fig. or paragraph. The advantages of using segment registers are that they: 1.3.[It is standard notation for parentheses around an entity to mean "contents of. . i. 3.e. or simply. Facilitate the use of separate memory areas for a program.3(b). the beginning segment address. 2. or stack segment. with each segment being 64K bytes long and beginning at a 16-byte. all addresses are given in hexadecimal. beginning at an address that is divisible by 16.3( a) and the overall segmentation of memory is shown in Fig.

4. 3. and a subtraction causes it to be set if a borrow is needed. Each bit in the PSW is called a flag. and the control flags. The 8086 flags are divided into the conditional flags. which control the execution of special functions. The condition flags are: SF (Sign FIag)-Is equal to the MSB of the result. . but 7 of them are not used.Fig Memory segmentation 3. PF (Parity Flag)-Is set to 1 if the low-order 8 bits of the result contains an even number of 1‟s. otherwise it is cleared. Other instructions also affect this flag and its value will be discussed when these instructions are defined. which reflect the result of the previous operation involving the ALU. this flag indicates whether the previous result was negative‟ or nonnegative. The flags are summarized in Fig.3 The 8086‟s PSW contains 16 bits. ZF (Zero Flag)-Is set to 1 if the result is zero and 0 if the result is nonzero. Since in 2‟s complement negative numbers have a 1 in the MSB and for nonnegative numbers this bit is 0. CF (Carry Flag)-An addition causes this flag to be set if there is a carry out of the MSB.

This flag is used exclusively for BCD arithmetic. OF (Overflow Flag)-Is set if an overflow occurs. i. a result is out of range. for addition this flag is set when there is a carry into the MSB and no carry out of the MSB or vice versa. if the previous instruction performed the addition 0010 0011 0100 1101 + 0011 0010 0001 0001 0101 0101 0101 1110 then following the instruction: SF=0 ZF=0 PF=0 CF=0 AF=0 OF=0 Fig 3. As an example. More specifically.AF (Auxiliary Carry Flag)-Is set if there is a carry out of bit 3 during an addition or a borrow by bit 3 during a subtraction..e. For subtraction.4: PSW register of 8086 If the previous instruction performed the addition 0101 0100 0011 1001 + 0100 0101 0110 1010 1001 1001 1010 0011 then the flags would be: SF = 1 ZF = 0 PF = 1 CF = 0 AF = 1 CF = 1 . it is set when the MSB needs a borrow and there is no borrow from the MSB or vice versa.

a certain type of interrupt (a maskable interrupt) can be recognized by the CPU.The control flags are: DF (Direction Flag)-Used by string manipulation instructions. Otherwise. . TF (Trap Flag)-If set. these interrupts are ignored. the string is processed from its beginning with the first element having the lowest address. IF (Interrupt Enable Flag)-If set. the string is processed from the high address towards the low address. otherwise. a trap is executed after each instruction. If zero.

15. 4.15: Shift and rotate instructions The shift and rotate instructions for the 8086 are defined in Fig. Write a sequence of instructions to reverse a two digit hexadecimal number available in the register AX using shift and rotate instructions? Fig 4. CNT. These instructions shift all of the bits in the operand to the left or right by the specified count.Q4. For the shift left instructions. zeroes are shifted into the right end of the operand and the MSBs are shifted out the left end and .

it extends the sign of the operand by repeatedly inserting the MSB. . The RCL and RCR instructions include the carry flag in the circle and the ROL and ROR do not. however. except that the least significant bit of these MSBs is retained in the CF flag. The rotate instructions differ from the shift instructions in that the operand is treated like a circle in which the bits shifted out of one end are shifted into the other end. although the carry flag is affected in all cases. The shift right instructions similarly shift bits to the right. SAR (shift arithmetic right) does not automatically insert zeroes from the left.lost.

then they are concatenated into a single segment in the load module.1: Creation and Execution of a program Segment Combination In addition to the linker commands. The ordering in the concatenation is specified by the linker command. Segments that have different names cannot be combined and segments with the same name but no combine-type will cause a linker error. the ASM-86 assembler provides a means of regulating the way segments in different object modules are organized by the linker. 5. The possible combine-types are: PUBLIC-If the segments in different object modules have the same name and the combine-type PUBLIC. . Just how the segments with the same name are joined together is determined by modifiers attached to the SEGMENT directives.Fig. A SEGMENT directive may have the form Segment name SEGMENT Combine-type where the combine-type indicates how the segment is to be located within the load module. Sometimes segments with the same name are concatenated and sometimes they are overlaid.

then it is said to be a local (or internal) identifier relative to the module. then they become one segment whose length is the sum of the lengths of the individually specified segments. If more than one segment with the MEMORY combine type is being linked. The length of the common segment is that of the longest segment being overlaid. then It is referred to as an external (or global) identifier relative to the module. there must be a way for a module to reference at least some of the variables and/or labels in the other modules. That is. It allows the user to specify the exact location of the segment in memory. These two lists are implemented by the EXTRN and PUBLIC directives. STACK-If segments in different object modules have the same name and the combine-type STACK.. MEMORY-This combine-type causes the segment to be placed at the last of the load module. which have the forms: . In effect. Access to External Identifiers Clearly. Therefore. and if it is not defined in the module but is defined in one of the other modules being linked. each module may contain two lists.COMMON-If the segments in different object modules have the same name and the combine-type is COMMON. the others will be overlaid as if they had COMMON combine types. they are combined to form one large stack. in order to permit other object modules to reference some of the identifiers in a given module. then they are overlaid so that they have the same beginning address. Also. the given module must include a list of the identifiers to which it will allow access. For multiple-module programs. one containing the external identifiers it references and one containing the locally defined identifiers that can be referred to by other modules. object modules that are being linked together must be able to refer to each other. For single-object module programs all identifiers that are referenced must be locally defined or an assembler error will occur. If an identifier is defined in an object module. AT-The AT combine-type is followed by an expression that evaluates to a constant which is to be the segment address. only the first one will be treated as having the MEMORY combine-type. the assembler must be informed in advance of any externally defined identifiers that appear in a module so that it will not treat them as being undefined.

Identifier where the identifiers are the variables and labels being declared as external or as being available to other modules. Fig. Because the assembler must know the type of all external identifiers before it can generate the proper machine code. a type specifier must be associated with each identifier in an EXTRN statement. . then the module containing the statement must also contain a directive such as EXTRN . If this is not the case. . . . One of the primary tasks of the linker is to verify that every identifier appearing in an EXTRN statement is matched by one in a PUBLIC statement. . Identifier:Type and PUBLIC Identifier... . .EXTRN Identifier:Type. .2 shows three modules and how the matching is done by the linker while joining them together. 5.. . For a variable the type may be BYTE.VAR1…. and the module in which VARl is defined must contain a statement of the form PUBLIC . VAR1 :WORD. then there will be an undefined external reference and a linker error will occur. or DWORD and for a label it may be NEAR or FAR. WORD. . In the statement INC VAR1 if VAR1 is external and is associated with a word. . ..

an offset and a segment address.Fig. The offsets associated with all external references can be assigned once all of the object modules have been found and their external symbol tables have been examined. but the offsets for the external identifiers and all segment addresses must be inserted by the linking process. The offsets for the local identifiers can be and are inserted by the assembler. . 5. The assignment of the segment addresses is called relocation and is done after the king process has determined exactly where each segment is to be put in memory. there are two parts to every address.2: Illustration of the matching verified by the linker As we have seen.

this is only applicable for the MASM . while the macro is a module with specific functions which can be used by different programs. We can say then that a procedure is an extension of a determined program. End of procedure declaration and an example of Macro: Position MACRO Row. At the moment the macro is executed each parameter is substituted by the name or value specified at the time of the call. The main difference between a macro and a procedure is that in the macro the passage of parameters is possible and in the procedure it is not. if we want a routine which adds two bytes stored in AH and AL each one. on the other hand the call of macros is done as if it were an assembler instruction. and keep the addition in the BX register: Adding Proc Near . Another difference between a macro and a procedure is the way of calling each one. 0 . A macro is a group of repetitive instructions in a program which are codified only once and can be used as many times as necessary. Ah Mov Ah. Differentiate macros and procedures.Q6. Declaration of the procedure Mov Bx. Return directive Add Endp . 00 Add Bx. to call a procedure the use of a directive is required. Content of the procedure Mov B1.there are other programming languages which do allow it. Ax Ret . Example of procedure: For example. Column PUSH AX PUSH BX PUSH DX .

Row MOV DL.MOV AH. Column MOV BH. 02H MOV DH. 0 INT 10H POP DX POP BX POP AX ENDM .

logic and data transfer One number must be in AL or AX Multiplication & Division Input & Output BX . 8086 CPU has 8 general purpose registers. Repetitive operations on strings with the REP command 3. CX . each register has its own name: AX . Describe about each flag of a 8086 flag register. Can be used for pointer addressing of data 2. DX:AX concatenated into 32-bit register for some MUL and DIV operations 2. Count (in CL) of bits to shift and rotate DX . 4. Iterative code segments using the LOOP instruction 2. Specifying ports in some IN and OUT operations SI . Used as destination in some string processing instructions 3. Offset address relative to ES . Offset address relative to DS DI .Q8. Used as source in some string processing instructions 3.source index register: 1.the count register (divided into CH / CL): 1.destination index register: 1. 3. 2.the accumulator register (divided into AH / AL): 1.the base address register (divided into BH / BL). Can be used for pointer addressing of data 2. Generates shortest machine code Arithmetic.the data register (divided into DH / DL): 1. 5.

SI and DI registers work with DS segment register. BP and SP work with SS segment register. 4. this is never a good idea. we could set the DS = 1230h and SI = 0045h.extra segment register.BP . For example if we would like to access memory at the physical address 12345h (hexadecimal).points at the segment containing the current program. This way we can access much more memory than with a single register. SS . 2. Segment registers work together with general purpose register to access any memory value. By default BX.points at the segment containing the stack. Offset address relative to SS SP . which is limited to 16 bit values. Primarily used to access parameters passed via the stack 2. . The segment registers have a very special purpose pointing at accessible blocks of memory. it's up to a coder to define its usage. The CPU makes a calculation of the physical address by multiplying the segment register by 10h and adding the general purpose register to it (1230h * 10h + 45h = 12345h): The address formed with 2 registers is called an effective address. 3.base pointer: 1. Although it is possible to store any data in the segment registers. Always points to top item on the stack Offset address relative to SS Always points to word (byte at even address) An empty stack will had SP = FFFEh SEGMENT REGISTERS CS . DS . ES .stack pointer: 1.generally points at segment where variables are defined.

set to 1 when result is zero.set to 1 when there is an unsigned overflow for low nibble (4 bits). When there is no overflow this flag is set to 0. and to 0 when there is odd number of one bits. 2. They are modified automatically by CPU after mathematical operations. For non-zero result this flag is set to 0. . although BX can form an effective address. this allows to determine the type of the result.determines the current state of the processor.255). FLAGS REGISTER Flags Register . SPECIAL PURPOSE REGISTERS IP . 1. Zero Flag (ZF) . Carry Flag (CF) . 4. Generally you cannot access these registers directly.the instruction pointer: 1. BH and BL cannot. Also. Offset address relative to CS IP register always works together with CS segment register and it points to currently executing instruction. Always points to next instruction to be executed 2. and to determine conditions to transfer control to other parts of the program... For example when you add bytes 255 + 1 (result is not in range 0. Parity Flag (PF) . Auxiliary Flag (AF) .Other general purpose registers cannot form an effective address. 3.this flag is set to 1 when there is an unsigned overflow.this flag is set to 1 when there is even number of one bits in result.

Overflow Flag (OF) . Trap Flag (TF) . When result is positive it is set to 0.127). For example..when this flag is set to 1 CPU reacts to interrupts from external devices.5. 9. (This flag takes the value of the most significant bit. Interrupt enable Flag (IF) .. when you add bytes 100 + 50 (result is not in range 128.) 6.set to 1 when there is a signed overflow. . Direction Flag (DF) .Used for on-chip debugging. 8.set to 1 when result is negative. Sign Flag (SF) . when this flag is set to 1 the processing is done backward. when this flag is set to 0 . 7.the processing is done forward.this flag is used by some instructions to process data chains.

Program MVI D. 8BH MVI C. C ADD D OUT PORT1 HLT . 6FH MOV A. Write an assembly program to add and display two numbers.Q9.

is shown in Fig. Both operands are memory operands. As an example consider the problem of moving the contents of a block of memory to another area in memory. 6. A solution that uses only the MOV instruction. Their auto-indexing obviates the need for separate incrementing or decrementing instructions. thus decreasing overall processing time. what are the advantages of the MOVS and CMPS instructions over the MOV and CMP instructions? When working with strings. 2.2(a). . the advantages of the MOVS and CMPS instructions over the MOV and CMP instructions are: 1. 3. They are only 1 byte long. which cannot perform a memory-to-memory transfer.BC0046 – Microprocessor Assignment Set – 2 Q2. When working with strings.

Note that the second program sequence may move either bytes or words. 6. 6.2(b). .2: Program sequences for moving a block of data A solution that employs the MOVS instruction is given in Fig.Fig. depending on the type of STRING1 and STRING2.

at which time the 8086 will drop the grant on the HLDA pin. The components capable of becoming masters are processors (and their bus control logic) and DMA controllers. not the CPU. The CPU with its bus control logic is normally the master. one of the system components connected to the system bus is given control of the bus. Taking control of the bus for a bus cycle is called cycle stealing. For a disk unit the data rate is determined by the speed with which data pass under the read/write head and quite often this rate exceeds 200. After the current bus cycle is completed the CPU will return a bus grant signal and the component sending the request will become the master. Data rates for I/O and mass storage devices are often determined by the devices. but other specially designed components can gain control of the bus by sending a bus request to the CPU. and the computer must be capable of executing I/O according to the maximum speed of the device. Thus. A request is made when a potential master sends a 1 to the HOLD pin. Just like the bus control logic. One exception to the normal sequence is that if a word which begins at an odd address is being accessed. then two bus cycles are required to complete the transfer and a grant will not be issued until after the second bus cycle. after the current bus cycle is complete the 8086 will respond by putting a 1 on the HLDA pin. This component is said to be the master during that cycle and the component it is communicating with is said to be the slave. which use DMA controllers to communicate directly with memory. For data rates of this magnitude.000 bytes per second. a master must be capable of placing addresses on the address bus and directing the bus activity during a bus cycle.Q3. Some devices. . such as magnetic tape and disk units and analog to-digital converters. then the communication can be performed using either programmed or interrupt I/O. The 8086 receives bus requests through its HOLD pin and issues grants from its hold acknowledge (HLDA) pin. It will remain master until it drops the signal to the HOLD pin. block transfers. During any given bus cycle. When the requesting device receives this grant signal it becomes the master. Sometimes a DMA controller is associated with a single interface. Explain the working of DMA. are required. Normally. there is less than 5 microseconds to transfer each byte to or from memory. may operate at data rates that are too high to be handled by byte or word transfers. If the data transfer rate to or from an I/O device is relatively low. but they are often designed to accommodate more than one interface.

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then approximately 99. it can waste a considerable amount of time while waiting for ready bits to become active. then a different approach is needed. a line feed is to be automatically appended to the carriage return Interrupt IO Even though programmed I/O is conceptually simple. A typical programmed input operation is flowcharted in Fig. suppose that a line of characters is to be input from a terminal to an 82-byte array beginning at BUFFER until a carriage return is encountered or more than 80 characters are input.3. otherwise.99% 100. As a more complete example. but if other processing is unnecessarily delayed. Interrupt is an event that causes the CPU to initiate a fixed sequence.990 x 100% = 99.000 of the time is not being utilized. if the person typing on the terminal could type 10 characters per second and only 10 μs is required for the computer to input each character. This is all right if no other processing could be done while the input is taking place. . Before an 8086 interrupt sequence can begin. the currently executing instruction must be completed unless the current instruction is a HLT or WAIT instruction. Write short notes on (i) programmed I/O and (ii) Interrupt I/O Programmed IO Programmed I/O consists of continually examining the status of an interface and performing an I/O operation with the interface when its status indicates that it has data to be input or its data-out buffer register is ready to receive data from the CPU.7.Q4. known as an interrupt sequence. If a carriage return is not found in the first 81 characters then the message “BUFFER OVERFLOW” is to be output to the terminal. In the above example.

. the interrupt request is recognized after the primitive operation following the REP is completed. Provided that the segment register is filled first. the interrupt request is not recognized between the prefix and the instruction. because the prefix is considered as part of the instruction. and the return address is the location of the REP prefix. . In the case of the REP instruction. this allows the contents of both a segment register and a pointer to be changed without interruption.For a prefixed instruction. an interrupt request is not recognized until after the instruction following the MOV or POP instruction is executed. For MOV and POP instructions in which the destination is a segment register.

If accessed sequentially. let us consider a personnel file that is shared by processes 1 and 2. the results would be unpredictable and almost certainly incorrect. and changes. A resource of this type. must be protected from being simultaneously accessed and modified by two or more processes. or tape drive). Semaphore Operations In multiprogramming systems. The solution to this problem is to allow only one process at a time to enter its critical section of code. In many situations. a common resource may be accessed and updated by only one process at a time and other processes must wait until the one currently using the shared resource is finished with it. or a shared memory area..Q5. if both processes were allowed to access the file at the same time.e. processes are allowed to share common software and data resources as well as hardware resources. A serially reusable resource may be a hardware resource (such as a printer. . For example. which is commonly referred to as a serially reusable resource. or vice versa. that section of code that accesses the serially reusable resource. However. this file would either be updated by process 1 and then sorted by process 2. Preventing two or more processes from simultaneously entering their critical sections for accessing a shared resource is called mutual exclusion. One way to attain mutual exclusion is to use flags to indicate when the shared resource is already in use. card reader. i. Suppose that process 1 performs insertions. deletions. To examine how this is done and some of the problems associated with this approach let us consider the possibility of using only one flag. a file of data. Explain about the semaphore operations. and process 2 puts the file in alphabetical order according to last names.

This address added to the offset L to form the physical address of the memory location. The number of bits representing the segment number governs the maximum number of segments allowed in a program. with each segment having a maximum size of 2n bytes. a program may have up to 2m segments. the program is divided into segments according to the logical structure of the program and the resulting memory management scheme is called segmentation. Fig. respectively. the segment number and the offset within the segment. Fig. For example. if the segment number and offset have m and n bits.7: Segmentation Scheme The segment number S in a logical address is used as an index into the segment table. With address translation hardware. 8. a user “virtually” has more memory to work with than actually exists. 8.7 illustrates the mapping of logical addresses into physical addresses. and the number of bits allocated to the offset specifies the maximum segment size. which returns the beginning physical address X of the referenced segment. thus providing each user with a virtual storage of 2m+n bytes. Because each job may be . When using segmentation.other words. each logical address consists of two fields.

assigned a separate area in the segment table. either the entire segment table or that portion of the table containing the beginning addresses of the segments that are currently in use must be stored in registers which are part of the memory management hardware.: Status Field-Indicates whether or not the referenced segment is in the memory. . Depending on . The index S is made relative to the segment table register. The most common of these additional attributes are the. the segment table register is updated to point to a new section of the segment table. Because the address translation must be performed for every memory reference. a segment descriptor may include attributes in addition to the beginning segment address. Change field : Indicates whether or not the segment has been modified since being brought into memory . writing. When the system switches from one job to another. Protection Field-Provides protection against unauthorized reading. Reference Field-Provides useful information in determining which segment is to be replaced. the base address of that section of the segment table that is associated with the currently executing job is stored in a register called the segment table register. Each entry in the segment table is referred to as a segment descriptor.the particular implementation. Segment Length Field-Indicates the size of the segment. or execution.

9. most microcomputers.13. request/grant) control signals. and P2 is an optional connector consisting of 60 auxiliary lines. only two devices may communicate with each other over the bus.13: Illustration of a module being plugged into MULTIBUS . flexibility. are built around a primary system bus which connects all of the major components in the system. The connector P1 consists of 86 pins which provide-the major bus signals. including those involving multiprocessor configurations. For reasons of simplicity. and low cost. The master/slave relationship is dynamic with bus allocation being accomplished through the bus allocation (i. denoted PI and P2. 9. In order to obtain a foundation while designing its products. these assumptions become formalized and constitute what is referred to as a bus standard The Intel MULTIBUS has gained wide industrial acceptance and several manufacturers offer MULTIBUS-compatible modules. I shown in Fig. At any point in time.. Fig. a microcomputer manufacturer makes assumptions about the bus that is to be used to connect its devices together Frequently.e. Explain the 8288 Bus controller.Q8. The MULTIBUS has been physically implemented on an etched backplane board which is connected to each module using two edge connectors. This bus is designed to support both 8-bit and 16-bit devices and can be used in multiprocessor systems in which several processors can be masters. primarily used for power failure detection and handling. one being the master and the other the slave.

Data transfers on the MULTIBUS bus are accomplished by handshaking signals in a manner similar to that described in the preceding sections. could be raised while remains low. (It should be pointed out that because an 8086 expects a byte to be put on the high-order byte of the bus when is active. 5. and could both be deactivated. labeled through . only eight of which are used in an 8-bit system. There are 16 bidirectional data lines ( ).. a bootstrap loader may be stored in an auxiliary ROM and a monitor in a ROM.Then. For example. ROM. any 16-bit interface must include a swap byte buffer so that only the lower data lines are used for all byte transfers. If control is passed to the user. 4. one may want to permit nonstandard MULTIBUS transfers between memory and an 8086. The MULTIBUS standard calls for all single bytes to be communicated over only the lower 8 bits of the bus. The memory read ( ). .The P1 lines can be divided into the following groups according to their functions: 1. Utility lines. memory write ( ). thus allowing the RAM to fill the entire memory space during normal operation. Bus access control lines. The address lines are driven by the bus master to specify the memory location or I/O port being accessed. when the monitor is in control. and auxiliary ROM in a common address space. Data lines. Because the loader is needed only after a reset.) The two inhibit signals are provided for overlaying RAM. 2. The MULTIBUS has 20 address lines. and could both be activated while the loader is executing. 3. where the numeric suffix represents the address bit in hexadecimal. therefore. Command and handshaking lines. Address lines.

and real types. i. If performed by the 8086 through emulation. decimal. the same operations would require approximately 2 ms and 20 ms. The 8087 Numeric Data Processor The 8087 numeric data processor (NDP) is specially designed to perform arithmetic operations efficiently. subtraction. respectively.3. As an example of its computing power. taking the tangent. A pin diagram of the 8087 is shown in Fig. Because a master must wait to be notified of the completion transfer. exponentiation. Draw the block diagram of 8087. The 8087 provides a simple and effective way to enhance the performance of an 8086 based system. to verify the end of a transfer. particular when an application is primarily computational in nature. In a general setting it may be received by bus master. This asynchronous nature enables the system to handle slow devices without penalizing fast devices Q9. It can operate on data of the integer. but also provides many useful functions. multiplication. with lengths ranging from 2 to 10 bytes. and division. the duration of a bus cycle varies depending on the speed of the bus master and the slave.. The instruction set not only includes various forms of addition. and I/O write ( ) lines are defined to be the same as they were in the discussion of the 8288 bus controller.e. There is an acknowledge ( ) signal which serves the same purpose as the READY signal in the discussion of the bus control logic. 10. such as taking the square root. . the 8087 can multiply two 64-bit real numbers in about 27 μs and calculate a square root in about 36 μs. and so on.I/O read ( ).

Fig. ground. clock. the INT pin to the interrupt management logic (assuming the 8087 is enabled for interrupts). the / pin to the host‟s / or / pin. Among the remaining eight pins. status ready. . and power pins of the NDP have the same pin positions as those assigned to the 8086/8088. This simple interface allows an existing maximum mode 8086-based system to be easily upgraded by replacing the original CPU with a piggyback module. 10. reset. four of them are not used. which consists of an 8086/8088 and an 8087. and the / could be connected to the bus request/grant pin of an independent processor such as an 8089. The other pins are connected as follows: the BUSY pin to the host‟s pin.3: 8087 pin diagram The address/data.

Explain why the processor utilization rate can be improved in a multiprocessor system by an instruction queue. . a coprocessor design does not require any extra logic other than that normally needed for a maximum mode system. an application that heavily involves floating point calculations can be readily satisfied. At this point the host may simply go on to the next instruction or it may fetch the first word of a memory operand for the coprocessor and then go on to the next instruction. For such applications. Although the 8086 is a powerful single-chip microprocessors. the coprocessor will capture the data word and its 20-bit physical address. Only the host CPU can fetch instructions. their instruction set is not sufficient to effectively satisfy some complex applications.1.10. If the CPU fetches the first word of an operand. but by using an Intel 8087 numeric data processor as a coprocessor. indicating what the coprocessor is to do and is simultaneously decoded by both the coprocessor and the host. An ESC instruction contains an external operation code. An instruction to be executed by the coprocessor is indicated when an escape (ESC) instruction appears in the program sequence. the CPU does not need to take any further action if the instruction is executed by the coprocessor. The interaction between the CPU and the coprocessor when an instruction is executed by the coprocessor is depicted in Fig. which is written in a superset of the 8086 instruction set. It will be seen that. For example.Q10. except for the coprocessor itself. the 8086 has no instructions for performing floating point arithmetic. Both the CPU and coprocessor execute their instructions from 1M same program. Other than possibly fetching an operand for the coprocessor. the 8086 must be supplemented with coprocessors that extend the instruction set in directions that will allow the necessary special computations to be accomplished more efficiently. but the coprocessor also receives all instructions and monitors the instruction sequencing of the host.

the 8086 will fetch a word from this . The first of two operands indicates the external opcode. then as explained above. If the second operand specifies a memory location. At that time the host should execute a WAIT instruction and wait until its pin is activated by the coprocessor. This parallel operation continues until the host needs the coprocessor to perform another operation or must have the results from the current operation.Fig.1: Synchronization between 8086 and its coprocessor For a source operand that is longer than one word. the coprocessor ignores the data word fetched by the host and later the coprocessor will store the result into the captured address. If the memory operand specified in the ESC instruction is a destination. the coprocessor can obtain the remaining words by stealing bus cycles. which determines the action to be taken by the coprocessor. the coprocessor will perform the operation indicated by the code in the ESC instruction. The WAIT instruction repeatedly checks the pin until it becomes activated and then executes the next instruction in sequence. In either case. as the host continues processing the instruction stream. 10. An ESC assembler language instruction has two operands. the coprocessor will send a busy (high) signal to the host‟s pin and.

possible to have two coprocessors connected to the same host CPU.location for the coprocessor and may pass the coprocessor an address for storing a result. 10. . In order for a coprocessor to determine when the host is executing an ESC instruction. it must monitor the host CPU‟s status on the . If the second operand is a register.lines and the ADl5-AD0 lines for fetched instructions. It is. one could use the / pin on the 8086 and the other could use the / pin.Both the host and the coprocessor share the same clock generator and bus control logic. the coprocessors must be assigned distinct subsets of the set of external opcodes and each coprocessor must be able to recognize and execute the members of its subset. if it is preceded by a branch instruction. The interfacing of a coprocessor to a host CPU is shown in Fig.2. it might not be executed at all. the register address is treated as part of the external op code and the CPU does nothing. For the most part parallel lines can be used to connect the host to its coprocessors. For two coprocessors. Because instructions are prefetched by the CPU. When this is done. an ESC instruction might not be executed immediately or. The two coprocessors would be connected to separate 8259A interrupt request pins.

The queue status 10 indicates that the queue in . If the queue‟s status is 00. this byte is ignored and is deleted from the queue.Fig. 10. but if it is 01. the coprocessor does nothing. it will perform the indicated operation.2: Coprocessor configurarion The coprocessor must track the instruction stream by monitoring the queue status bits QS1 and QS0 and maintaining an instruction queue identical to that of the host. it will compare the five MSBs of the first byte in the queue to 11011. If there is a match. assuming that the coprocessor recognizes the external opcode. then an ESC instruction is ready to be executed and. otherwise.

causes the queue in the coprocessor to also be emptied. Last.the host is being flushed and. therefore. it will send out an interrupt request (which is normally sent to an 8259A). The coprocessor should also be designed so that it can steal bus cycles by making bus requests through one of the host‟s pins when additional data must be read from or stored in memory. the coprocessor must be able to apply a high signal to the host‟s pin while it is busy. . If not part of an ESC instruction. this byte is ignored. � The coprocessor should be designed so that when an error occurs during the decoding or execution of an ESC instruction. The 11 status combination indicates that the first byte in the queue is not the first byte of an instruction and this byte is looked at by the coprocessor only / if it is known to be part of an ESC instruction.