P. 1
xr2211

xr2211

|Views: 36|Likes:
Published by abdulmajeed_cet

More info:

Published by: abdulmajeed_cet on Feb 14, 2013
Copyright:Attribution Non-commercial

Availability:

Read on Scribd mobile: iPhone, iPad and Android.
download as PDF, TXT or read online from Scribd
See more
See less

06/05/2014

pdf

text

original

XR-2211

...the analog plus company TM

FSK Demodulator/ Tone Decoder
June 1997-3

FEATURES D Wide Frequency Range, 0.01Hz to 300kHz D Wide Supply Voltage Range, 4.5V to 20V D HCMOS/TTL/Logic Compatibility D FSK Demodulation, with Carrier Detection D Wide Dynamic Range, 10mV to 3V rms D Adjustable Tracking Range, +1% to 80% D Excellent Temp. Stability, +50ppm/°C, max.

APPLICATIONS D Caller Identification Delivery D FSK Demodulation D Data Synchronization D Tone Decoding D FM Detection D Carrier Detection

GENERAL DESCRIPTION The XR-2211 is a monolithic phase-locked loop (PLL) system especially designed for data communications applications. It is particularly suited for FSK modem applications. It operates over a wide supply voltage range of 4.5 to 20V and a wide frequency range of 0.01Hz to 300kHz. It can accommodate analog signals between 10mV and 3V, and can interface with conventional DTL, TTL, and ECL logic families. The circuit consists of a basic PLL for tracking an input signal within the pass band, a quadrature phase detector which provides carrier detection, and an FSK voltage comparator which provides FSK demodulation. External components are used to independently set center frequency, bandwidth, and output delay. An internal voltage reference proportional to the power supply is provided at an output pin. The XR-2211 is available in 14 pin packages specified for military and industrial temperature ranges.

ORDERING INFORMATION
Part No. XR-2211M XR-2211N XR-2211P XR-2211ID Package 14 Pin CDIP (0.300”) 14 Pin CDIP (0.300”) 14 Pin PDIP (0.300”) 14 Lead SOIC (Jedec, 0.150”) Operating Temperature Range -55°C to +125°C -40°C to +85°C -40°C to +85°C -40°C to +85°C

Rev. 3.01
E1992

EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017 1

XR-2211
BLOCK DIAGRAM
VCC 1 GND 4 NC 9

Pre Amplifier INP 2 Loop q-Det Lock Detect Comparator

11 3

LDO LDF

TIM C1

14

VCO TIM C2 TIM R VREF COMP I 13 12 Internal 10 8 VREF Reference FSK Comp Quad q-Det

6

LDOQ

5

LDOQN

7

DO

Figure 1. XR-2211 Block Diagram

Rev. 3.01 2

The value of VREF is VCC/2 . Rev. Timing Resistor Input.01 3 . This output will be low if the VCO is in the capture range. Lock Detect Output Not. Lock Detect Filter. Data Output. Receive Analog Input. 0. The timing capacitor connects between this pin and pin 13. Not Connected. Timing Capacitor Input. FSK Comparator Input. Timing Capacitor Input. This pin connects to the timing resistor of the VCO. 3. This output will be high if the VCO is in the capture range. Internal Voltage Reference. Lock Detect Output. Loop Detect Output.XR-2211 PIN CONFIGURATION VCC INP LDF GND LDOQN LDOQ DO 1 2 3 4 5 6 7 14 13 12 11 10 9 8 TIM C1 TIM C2 TIM R LDO VREF NC COMP I VCC INP LDF GND LDOQN LDOQ DO 1 2 3 4 5 6 7 14 13 12 11 10 9 8 TIM C1 TIM C2 TIM R LDO VREF NC COMP I 14 Lead CDIP. Ground Pin.150”) PIN DESCRIPTION Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol VCC INP LDF GND LDOQN LDOQ DO COMP I NC VREF LDO TIM R TIM C2 TIM C1 O O I I I O O O I I O Type Description Positive Power Supply. Decoded FSK output. This output provides the result of the quadrature phase detection. The timing capacitor connects between this pin and pin 14.300”) 14 Lead SOIC (Jedec.650mV. PDIP (0.

Unit Conditions Notes Parameters are guaranteed over the recommended operating conditions. Parameter General Supply Voltage Supply Current Oscillator Section Frequency Accuracy Frequency Stability Temperature Power Supply Upper Frequency Limit Lowest Practical Operating Frequency Timing Resistor. Max. See Figure 7.01 +50 0. TA = +25°C. unless otherwise specified. C0 = 50mF +1 +3 % Deviation from fO = 1/R0 C0 4. See Figure 4.See Figure 5 Operating Range Recommended Range Loop Phase Dectector Section Peak Output Current Output Offset Current Output Impedance Maximum Swing Quadrature Phase Detector Peak Output Current Output Impedance Maximum Swing Input Preampt Section Input Impedance Input Signal Voltage Required to Cause Limiting 2 10 mV rms 20 KW 100 300 1 11 mA MW VPP Measured at Pin 2 +4 +150 +200 1 1 +5 +300 mA mA MW V Referenced to Pin 10 Measured at Pin 3 Measured at Pin 11 5 5 2000 KW KW See Figure 7 and Figure 8. Rev. Bold face parameters are covered by production test and guaranteed over operating temperature range.033mF. See Figure 7. VCC = + 5V. 100 +20 0.05 0. Min. 3. R0 = 8.XR-2211 ELECTRICAL CHARACTERISTICS Test Conditions: VCC = 12V. CO = 0. C0 = 400pF R0 = 2MW.01 4 . VCC = 12 +1V. Typ.5 4 20 7 V mA R0 > 10KW. R0 .2 300 0. RO = 30KW.2KW.5 ppm/°C %/V %/V kHz Hz See Figure 8. but are not 100% tested in production.

. . . . . The preamplifier is used as a limiter such that input signals above typically 10mV rms are amplified to a constant high level signal. . . . . . . . . . . . . . . . . . . . 8mW/°C PDIP . . . . . . 5mW/°C SYSTEM DESCRIPTION The main PLL within the XR-2211 is constructed from an input preamplifier. . . . . 750mW Derate Above TA = 25°C . . . . . . . Parameter Voltage Comparator Section Input Impedance Input Bias Current Voltage Gain Output Voltage Low Output Leakage Current Internal Reference Voltage Level Output Impedance Maximum Source Current 4. . . . . these frequencies are fIN+ fVCO (2 times fIN when in lock) and fIN . . . . 60mW/°C SOIC . . . . . 390mW Derate Above TA = 25°C . . . . . . . . . . . . . . 3V rms Power Dissipation . . . . . . . . . TA = +25°C. . By adding a capacitor to the phase detector output. . . . . . . . . 900mW Package Power Dissipation Ratings CDIP . . 3. . .01 500 10 MW nA dB mV mA RL = 5. . . . . . . . Bold face parameters are covered by production test and guaranteed over operating temperature range. . .9 5. . . . . . . . . 800mW Derate Above TA = 25°C . . . . . . . The FSK comparator is used to determine if the VCO is driven above or below the center frequency (FSK comparator). . When in lock. . . . . . . . . . . . . . . . . leaving a DC voltage that represents the phase difference between the two frequencies. .3 100 80 5. . . . . . . . . . . . . . . unless otherwise specified. CO = 0. . . Max. This closes the loop and allows the VCO to track the input frequency. . analog multiplier used as a phase detector and a precision voltage controlled oscillator (VCO). . . . . . . . . . . . . . . . . . . . . . . . Unit Conditions Notes Parameters are guaranteed over the recommended operating conditions. . . .fVCO (0Hz when lock). . . RO = 30KW. . . . . .033mF. . Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS Power Supply . but are not 100% tested in production. . . . . .01 5 (internally connected). 20V Input Signal Level . . . This will produce both active high and active low outputs to indicate when the main PLL is in lock (quadrature phase detector and lock detector comparator). .XR-2211 DC ELECTRICAL CHARACTERISTICS (CONT’D) Test Conditions: VCC = 12V. The VCO is actually a current controlled oscillator with its normal input current (fO) set by a resistor (R0) to ground and its driving current with a resistor (R1) from the phase detector. . . . . . the 2 times fIN component is reduced. . . . .7 V W mA Measured at Pin 10 AC Small Signal 55 2 100 70 300 0. . . . . . . .1KW IC = 3mA VO = 20V Measured at Pins 3 and 8 Min. . . . . . . . . . Its output (unfiltered) produces sum and difference frequencies of the input and the VCO output. . Typ. . . The multiplying-type phase detector acts as a digital exclusive or gate. . The output of the phase detector produces sum and difference of the input and the VCO frequencies Rev. . . .

it can sink up to 5mA of load current. the VCO outputs are internally connected to the phase detector sections of the circuit. Loop Phase Detector Output (Pin 11): This terminal provides a high impedance output for the loop phase detector. pin 3 can be left open. Instead. Q (Pin 6): The output at pin 6 is at “low” state when the PLL is out of lock and goes to “high” state when the PLL is locked. Lock Detect Output. The VCO free-running frequency. VREF. The maximum timing current drawn from pin 12 must be limited to < 3mA for proper operation of the circuit. Reference Voltage. an FSK post-detection or data filter is connected between this terminal and the PLL phase detector output (pin 11). The PLL loop filter is formed by R1 and C1 connected to pin 11 (see Figure 3. the DC level at pin 11 is very nearly equal to VREF. When decoding FSK signals. and at “low” or “on” state for high input frequency. Quadrature Phase Detector Output (Pin 3): This is the high impedance output of quadrature phase detector and is internally connected to the input of lock detect voltage comparator. RX. connected from this terminal to ground. (Pin 5): The output at pin 5 is the logic complement of the lock detect output at pin 6. It is an open collector type output and requires a pull-up resistor. For set-up or adjustment purposes. fO: XR-2211 does not have a separate VCO output terminal. VREF (Pin 10): This pin is internally biased at the reference voltage level. The peak to peak voltage swing available at the phase detector output is equal to 2 x VREF. FSK data output is at “high” or “off” state for low input frequency.) C0 must be non-polar. and is internally biased at a DC level equal to VREF. VCO Frequency Adjustment: VCO can be fine-tuned by connecting a potentiometer. available at pin 10. C0.650mV. It can sink 5mA of load current. Normally. the VCO can then be tuned to obtain a 50% duty cycle on the FSK output (pin 7). 3. and applying an alternating bit pattern of O’s and 1’s at the known mark and space frequencies. In tone detection applications. If the tone detect section is not used. fO. VCO Timing Capacitor (Pins 13 and 14): VCO frequency is inversely proportional to the external timing capacitor.) With no input signal. or with no phase error within the PLL. and in the range of 200pF to 10mF. to VCC for proper operation. For optimum temperature stability. VREF: VREF = VCC /2 . RL.) The threshold voltage of the comparator is set by the internal reference voltage. Lock Detect Complement.XR-2211 PRINCIPLES OF OPERATION Signal Input (Pin 2): Signal is AC coupled to this terminal.) This terminal is a low impedance point. pin 3 is connected to ground through a parallel combination of RD and CD (see Figure 3) to eliminate the chatter at lock detect outputs. Pin Rev. . R0 must be in the range of 10KW to 100KW (see Figure 9. connected across these terminals (see Figure 6. Recommended input signal level is in the range of 10mV rms to 3V rms. At “low” state. This will ensure that the VCO fO value is accurately referenced to the mark and space frequencies. in series with R0 at pin 12 (see Figure 10. This data filter is formed by RF and CF (see Figure 3. RL. The internal impedance at pin 2 is 20KW. If no input signal is present. By adjusting R0. This output is also an open collector type stage which can sink 5mA of load current at low or “on” state. FSK Data Output (Pin 7): This output is an open collector logic stage which requires a pull-up resistor.1mF capacitor for proper operation of the circuit.01 6 10 must be bypassed to ground with a 0. the VCO free-running frequency can be tuned by using the generalized circuit in Figure 3. The DC voltage level at this pin forms an internal reference for the voltage levels at pins 5. the logic state at pin 7 is indeterminate. is: fO + 1 Hz R 0·C 0 where C0 is the timing capacitor across pins 13 and 14. 11 and 12. VCO Control Input (Pin 12): VCO free-running frequency is determined by external timing resistor.) VCO Free-Running Frequency. to VCC for proper operation. R0. 8. FSK Comparator Input (Pin 8): This is the high impedance input to the FSK voltage comparator.

Functional Block Diagram of a Tone and FSK Decoding System Using XR-2211 VCC RB Rl + 7 FSK Comp.1mF 2 Rev.01 7 ÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎ φ Det φ VCO Preamp φ φ Det Lock Detect Filter Lock Detect Comp Loop Phase Detect 11 C1 RF 8 CF 10 0. 5 LDOQ LDOQN Figure 3. 3.XR-2211 Input Input Signal 0. Internal Reference 6 + Lock Detect Comp.1mF 14 C0 Quad Phase Detect 13 R0 VCO 12 R1 3 RD CD Loop Filter Data Filter FSK Output FSK Comp Lock Detect Outputs Figure 2. Generalized Circuit Connection for FSK and Tone Detection .

please see TAN-011.XR-2211 DESIGN EQUATIONS (All resistance in W. Internal Reference Voltage. "+ f 0 Df + R 0 R1 f0 Tracking Bandwidth Df Df fLL f1 fO f2 fLH Rev. 3. 5. Loop-tracking Df bandwidth. Loop Damping. VCO Center Frequency. t: t + C 1·R PP (seconds) where: R PP + R 1·R F R1 ) RF if RF is 1 or CF reactance is 1. fO: fO + 1 R 0·C 0 2. unless otherwise specified) (See Figure 3 for definition of components) 1. VREF (measured at pin 10): V REF + V CC 2 –650mV in volts 3. j: z+ 1250·C 0 R 1·C 1 Note: For derivation/explanation of this equation. Loop Low-Pass Filter Time Constant. then RPP = R1 4. all frequency in Hz and all capacitance in farads.01 8 .

Rev. please see TAN-011. Total loop gain. VCO conversion gain. tF: tF + RB · RF ·C (seconds) ( R B ) R F) F 7. 000 Note: For derivation/explanation of this equation. 8.01 9 . KT: K T + K O·K d·F(s) + 11. per unit of phase error at phase detector input): Kd + V REF · R 1 volt 10. Kd: (Kd is the differential DC voltage across pin 10 and pin11. FSK Data filter time constant. The filter transfer function: F(s) + 1 at 0 Hz. 1 ) SR 1·C 1 S = Jw and w = 0 10. Peak detector current IA: RF 5. Ko: (Ko is the amount of change in VCO frequency. 3. 000·p radian Note: For derivation/explanation of this equation.XR-2211 6. Loop phase detector conversion gain. 000·C 0·(R 1 ) R F) 1 seconds IA + V REF (V REF in volts and I A in amps) 20. per unit of DC voltage change at pin 11): K0 + –2p + V REF ·C 0 · R 1 radian second volt 9. please see TAN-011.

fO: f O + F 1·F 2 b) Choose value of timing resistor R0. RO + RO ) RX 2 c) Calculate value of C0 from design equation (1) or from Figure 7: CO + 1 R0 · f0 d) Calculate R1 to give the desired tracking bandwidth (See design equation 5). CF and RF form a one-pole post-detection filter for the FSK data output. For a given set of FSK mark and space frequencies.01 10 . RX. fO and f1. The final value of R0 is normally fine-tuned with the series potentiometer. all frequency in Hz and all capacitance in farads. and C1 sets the loop filter time constant and the loop damping factor. This choice is arbitrary. With reference to Figure 3 and Figure 10. R1 sets the system bandwidth. R1. R1 + R 0·f 0 ·2 (f 1–f 2) e) Calculate C1 to set loop damping. j = 0.XR-2211 APPLICATIONS INFORMATION FSK Decoding Figure 10 shows the basic circuit connection for FSK decoding. Design Instructions: The circuit of Figure 10 can be tailored for any FSK decoding application by the choice of five key circuit components: R0.5 is recommended. unless otherwise specified) a) Calculate PLL center frequency. C0. the functions of external components are defined as follows: R0 and C0 set the PLL center frequency. 3. (See design equation 4): Normally. The resistor RB from pin 7 to pin 8 introduces positive feedback across the FSK comparator to facilitate rapid transition between output logic states. these parameters can be calculated as follows: (All resistance in W’s. C1 + 1250·C 0 R1 · j2 Rev. to be in the range of 10KW to 100KW. The recommended value is R0 = 20KW. C1 and CF.

Rx. 3. Figure 4 illustrates a method of de-sensitizing the XR-2211 from such noisy line conditions by the use of a resistor. 000 or R X + 20. 000 REF –1 (20. CF: R sum + (R F ) R 1)·R B ( R 1 ) R F ) R B) 1 seconds CF + 0.XR-2211 f) The input to the XR-2211 may sometimes be too sensitive to noise conditions on the input line. Desensitizing Input Stage g) Calculate Data Filter Capacitance.25 (R sum·Baud Rate) Note: All values except R0 can be rounded to nearest standard value. The value of Rx is chosen by the equation and the desired minimum signal threshold level. connected from pin 2 to ground. Rev.8mV offset + V REF V 20. V IN minimum (peak) + V a–V b + DV " 2.01 11 ÎÎ ÎÎ ÎÎ 2 20K 20K Baud rate in . 000 ) R X) DV VIN minimum (peak) input voltage must exceed this value to be detected (equivalent to adjusting V threshold) VCC To Phase Detector Input Va Vb Rx VREF 10 Figure 4.

01 1.0 R0=10K +0.99 0.98 0.02 Normalized Frequency 1. Timing Resistor C0=0. Typical Supply Current vs.01mF C0=0. Typical fO vs.5 0 R0=50K 50K R0=500K 10K V+ = 12V R1 = 10 R0 fO = 1 kHz 0 25 50 75 100 125 -0.0033mF R0(KW ) 100 C0=0.000 Figure 6. V+ (Volts) 0. Typical Center Frequency Drift vs.00 0.5 R0=1MΩ -1. 3.001mF 1. Timing Capacitor Normalized Frequency Drift (% of f O) +1.01 100 Figure 5. Current (mA) 1.0 -50 -25 Temperature (°C) Figure 9.97 4 1 6 8 10 3 2 5 4 C0=0. V+ (Logic Outputs Open Circuited) 1. Temperature Rev.XR-2211 20 Supply vs.1mF C0=0.0331mF 10 C0=0.1 0.33mF 0 1000 10000 fO(Hz) Figure 7.01 12 ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ R0=5KW R0=10KW R0=20KW R0=40KW R0=80KW R0=160KW 1000 fO(HZ) 10000 fO = 1kHz RF = 10R0 2 4 R0 Curve 1 5K 2 10K 3 30K 4 100K 300K 5 16 18 20 22 3 1 5 12 14 24 V+ (Volts) C0( mF) ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ Figure 8.0 15 R0=5KΩ 10 R0=10KΩ 5 R0>100K 0 4 6 8 10 12 14 16 18 20 22 24 Supply Voltage. VCO Frequency vs. VCO Frequency vs. Power Supply Characteristics 1MΩ 500K .

25 R SUM·Baud Rate + 1nF Note: All values except R0 can be rounded to nearest standard value. Step 1: Calculate fO: from design instructions (a) f O + 1200·2200 =1624 Step 2: Calculate R0 : R0 =10K with a potentiometer of 10K.5 2 Step 6: Calculate RF : RF should be at least five times R1.9nF 51000·0.000⋅5 = 255 KW Step 7: Calculate RB : RB should be at least five times RF.000⋅5 = 1. RF = 51.2 MW Step 8: Calculate RSUM : (R F ) R 1)·R B + 240KW (R F ) R 1 ) R B ) R SUM + Step 9: Calculate CF : CF + 0. Rev. 3. (See design instructions (b)) (b) R T + 10 ) 10 + 15K 2 Step 3: Calculate C0 from design instructions (c) C O + 1 + 39nF 15000·1624 Step 4: Calculate R1 : from design instructions (d) R 1 + 20000·1624·2 + 51.XR-2211 Design Example: 1200 Baud FSK demodulator with mark and space frequencies of 1200/2200.01 13 . RB = 255. 000 (2200–1200) Step 5: Calculate C1 : from design instructions (e) C 1 + 1250·39nF + 3.

7nF 5% VCO 14 27nF 13 CO 5% Rx 20K Quad Phase Detect 12 RF 178K 5% 1nF 8 1.1K 5% Data Output CF 10% Input Signal 2 0. 3. Internal Reference RL 5.1µF R0 20K 1% VCO Fine Tune 6 + LDOQ LDOQN 5 Lock Detect Comp.1µF 2 14 VCO 12 3 CD Lock Detect Comp. 5 LDOQN Figure 11. Figure 10. Internal Reference RL 5. External Connectors for FSK Demodulation with Carrier Detect Capability Rev.1k CF 10 Input Signal 0.XR-2211 VCC RB Loop Phase Detect 11 C1 2.8m 5% 7 FSK Comp.1µF R1 35.2K 10 1% 0. Circuit Connection for FSK Decoding of Caller Identification Signals (Bell 202 Format) VCC RB Loop Phase Detect 11 C1 R1 0.01 14 .1µF 13 C0 Rx 6 LDOQ Quad Phase Detect RD Between 400K and 600K R0 RF 8 + 7 FSK Comp.

With reference to Figure 3 and Figure 12. C1 sets the low pass-loop filter time constant and the loop damping factor.1µF R0 20K 1% Rx 5K VCO Fine Tune 6 LDOQ Quad Phase Detect + 3 RD 470K CD 80nF 5 LDOQN Lock Detect Comp. Tone Detection The minimum value of the lock detect filter capacitance CD is inversely proportional to the capture range.1K Logic Output Figure 12. and require external pull-up resistors RL2 and RL3.XR-2211 VCC Loop Phase Detect 11 C1 220pF 5% 12 VCO 14 13 C0 5% 50nF 8 + R1 200K 10 1% 0. LDOQN and LDOQ at pins 5 and 6 are normally at “high” and “low” logic states. the logic state at these outputs become reversed for the duration of the input tone. Each logic output can sink 5mA of load current. is shorted to data output (pin 7). pin 6. +Dfc. 3. It is further limited by C1. R1 sets the detection bandwidth. Note: Data Output is “Low” When No Carrier is Present. applications choose CD = 0. Df C in mF and f in Hz. until there is a carrier within the detection band of the PLL and the pin 6 output goes “high” to enable the data output. Excessively large values of CD will slow the response time of the lock detect output. Thus. With values of CD that are too small. Internal Reference VCC 2 0. respectively.1µF Tone Input RL2 5. chatter can be observed on the lock detect output as an incoming signal Rev. This is the range of incoming frequencies over which the loop can acquire lock and is always less than the tracking range. data output will be disabled at “low” state. Dfc > Df/2. frequency approaches the capture bandwidth. The logic outputs. Both outputs at pins 5 and 6 are open collector type stages.01 15 . When a tone is present within the detection band of the PLL. as shown in Figure 12. For RD = 470KW. For most applications.1mF.1K RL3 5. The recommended circuit connection for this application is shown in Figure 11. 7 FSK Comp.D. the functions of the external circuit components can be explained as follows: R0 and C0 set VCO center frequency. Circuit Connection for Tone Detection FSK Decoding with Carrier Detect The lock detect section of XR-2211 can be used as a carrier detect option for FSK decoding. For Caller I. The open collector lock detect output. C D § 16 C in mF and f in Hz. the approximate minimum value of CD can be determined by: Figure 12 shows the generalized circuit connection for tone detection.

The recommended value is R0 = 20 KW. Design Examples: Tone detector with a detection band of + 100Hz: a) Choose value of timing resistor R0 to be in the range of 10KW to 50KW. The final value of R0 is normally fine-tuned with the series potentiometer. fS. 000 R 0·f S Rev. 3. the tone frequency. 000·1. e) Calculate value of the filter capacitor CD .5 is recommended. C1 + 1250·C 0 R 1·j 2 Increasing C1 improves the out-of-band signal rejection. unless otherwise specified) a) Choose value of timing resistor R0 to be in the range of 10KW to 50KW. these parameters are calculated as follows: (All resistance in W’s. but increases the PLL capture time./min. with RD = 470KW. all frequency in Hz and all capacitance in farads. The recommended value is R0 = 20KW.01 16 . This choice is dictated by the max. current that the internal voltage reference can deliver. CD must be: C D § 16 Df C in mF Increasing CD slows down the logic output response time. RX. RX. The final value of R0 is normally fine-tuned with the series potentiometer. R1. j = 0. C0. This choice is dictated by the max. b) Calculate value of C0 from design equation (1) or from Figure 6 fS = fO: C0 + 1 + 1 + 50nF 20. For a given input.XR-2211 Design Instructions: The circuit of Figure 12 can be optimized for any tone detection application by the choice of the 5 key circuit components: R0. C1 and CD./min. To avoid chatter at the logic output. b) Calculate value of C0 from design equation (1) or from Figure 7 fS = fO: CO + 1 R 0·fs c) Calculate R1 to set the bandwidth +Df (See design equation 5): R1 + R 0·f 0·2 Df Note: The total detection bandwidth covers the frequency range of fO +Df d) Calculate value of C1 for a given loop damping factor: Normally. current that the internal voltage reference can deliver.

000·2 + + 400K 100 Df Note: The total detection bandwidth covers the frequency range of fO +Df d) Calculate value of C0 for a given loop damping factor: Normally.1µF FM Input 14 VCO 13 C0 Quad Phase Detect 12 Figure 13.XR-2211 c) Calculate R1 to set the bandwidth +Df (See design equation 5): R1 + R 0·f O·2 20. 000·1. VCC VCC RF 100K Loop Phase Detect 11 C1 R1 0. j = 0. 3. f) Fine tune center frequency with 5KW potentiometer.25pF 400. To avoid chatter at the logic output.1µF R0 6 + 5 LDOQ LDOQN Lock Detect Comp.) Rev.5 is recommended. e) Calculate value of the filter capacitor CD .01 17 . but increases the PLL capture time. 10 8 + 3 7 FSK Comp . 000·0.1µF 2 0.5 R 1·j 2 Increasing C1 improves the out-of-band signal rejection. CD must be: C D + 16 w 16 w 80nF 200 Df Increasing CD slows down the logic output response time. (See Section on Design Equation for Component Values. Linear FM Detector Using XR-2211 and an External Op Amp. Internal Reference CF 2 1 1 + 4 1 LM324 Demodulated Output 0. RX. C1 + –9 1250·C 0 + 1250·50·10 2 + 6. with RD = 470KW.

650mV). The demodulated output is taken from the loop phase detector output (pin 11). through a post-detection filter made up of RF and CF. Equivalent Schematic Diagram Rev. 3. CD. R0. This buffer amplifier is necessary because of the high impedance output at pin 11. i.XR-2211 Linear FM Detection XR-2211 can be used as a linear FM detector for a wide range of analog communications and telemetry applications.. the output voltage change per unit of FM deviation can be given as: V OUT + R 1·V REF 100·R 0 where VR is the internal reference voltage (VREF = VCC /2 . V+ 1 20K REF Voltage Output 10 Input 2 B 10K 10K From VCO B’ Lock Detect Filter 3 6 Lock Detect Outputs 5 20K Internal Voltage Reference Input Preamplifier and Limiter Quadrature Phase Detector Lock Detect Comparator 2K 2K 8 A Timing Capacitor 13 C0 14 B’ B A’ A From VCO A’ 11 FSK Comparator Loop Input Detector Output 7 FSK Data Output 4 Ground 12 R0 Timing Resistor Voltage Controlled Oscillator 8K Loop Phase Detector FSK Comparator Figure 14. For the choice of external components R1. Normally. The recommended circuit connection for this application is shown in Figure 13.01 18 . a non-inverting unity gain op amp can be used as a buffer amplifier. see the section on design equations. C1 and CF. and an external buffer amplifier. as shown in Figure 13. The FM detector gain.e.

785 0.35 MAX 5.65 0.015 0.40 6.014 0.08 1. 1.54 0. 3.018 0.310 MILLIMETERS MIN 2.100 BSC 0.46 19.54 BSC 3.200 0.XR-2211 14 LEAD CERAMIC DUAL-IN-LINE (300 MIL CDIP) Rev.87 0.94 7.300 BSC 0.026 0.62 BSC 2.66 1.250 MAX 0.065 0.200 7.125 0.685 0.52 0.18 5.045 0.01 19 .36 1.060 0.00 14 8 1 7 E D Base Plane Seating Plane L e B B1 c A1 A E1 α INCHES SYMBOL A A1 B B1 c D E1 E e L MIN 0.38 0.20 17.100 0.08 15° α 0° 15° 0° Note: The control dimension is the inch column Rev.008 0.14 0.

070 0.00 14 1 D 8 7 E1 E A2 Seating Plane A L A1 B e B1 α eA eB C INCHES SYMBOL A A1 A2 B B1 C D E E1 e eA eB L MIN 0.115 0.42 7.008 0.100 BSC 0.38 20. 3.014 0.54 BSC 7.725 0.78 0.62 6.06 15° α Note: The control dimension is the inch column Rev.795 0.36 0.92 0.070 0.280 MILLIMETERS MIN 3.030 0.430 0.62 BSC 7.310 0.76 0.014 0.78 4.300 BSC 0.10 MAX 5.20 18.145 0.210 0.38 2.95 0.325 0.XR-2211 14 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) Rev.92 0° 10.015 0.33 1.68 0.115 0° 0.26 7.024 0.160 15° 2. 1.300 0.87 2.56 1.92 4.19 8.11 0.01 20 .195 0.240 MAX 0.

016 0.01 21 .228 0.00 D 14 8 E 1 7 H C Seating Plane e B A1 L A α INCHES SYMBOL A A1 B C D E e H L MIN 0.244 0.013 0.004 0.40 6.157 MILLIMETERS MIN 1.00 0.19 8.25 8.007 0.053 0. 1.75 4.27 8° α 0° 8° 0° Note: The control dimension is the millimeter column Rev.10 0.75 0.35 0.25 0.51 0.020 0.050 BSC 0.069 0.20 1.337 0.344 0.33 0.80 MAX 1. 3.010 0.150 MAX 0.27 BSC 5.55 3.XR-2211 14 LEAD SMALL OUTLINE (150 MIL JEDEC SOIC) Rev.010 0.80 0.050 1.

XR-2211 Notes Rev.01 22 . 3.

3.XR-2211 Notes Rev.01 23 .

Copyright 1995 EXAR Corporation Datasheet June 1997 Reproduction. is assumed for inaccuracies. Rev. and makes no representation that the circuits are free of patent infringement. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives.XR-2211 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design. EXAR Corporation assumes no responsibility for the use of any circuits described herein. without the prior written consent of EXAR Corporation is prohibited. in writing. assurances to its satisfaction that: (a) the risk of injury or damage has been minimized. conveys no license under any patent or other right. (c) potential liability of EXAR Corporation is adequately protected under the circumstances. in part or whole. While the information in this publication has been carefully checked.01 24 . Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. no responsibility. (b) the user assumes all such risks. however. 3. performance or reliability.

You're Reading a Free Preview

Download
scribd
/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->