VLSI Design Lab Manual

Revision 1.2 IC615 Assura 410 Incisive Unified Simulator 92

Developed By University Support Team Cadence Design Systems, Bangalore
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Objective
Objective of this lab is to learn the Virtuoso tool as well learn the flow of the Full Custom IC design cycle. You will finish the lab by running DRC, LVS and Parasitic Extraction on the various designs. In the process you will create various components like inverter, differential amplifier but we won’t be designing every cell, as the time will not be sufficient, instead we will be using some ready made cells in the process. You will start the lab by creating a library called ―myDesignLib‖ and you will attach the library to a technology library called ―gpdk180‖. Attaching a technology library will ensure that you can do front to back design. You will create a new cell called ―Inverter‖ with schematic view and hence build the inverter schematic by instantiating various components. Once inverter schematic is done, symbol for ―Inverter‖ is generated. Now you will create a new cell view called ―Inverter_Test‖, where you will instantiate ―Inverter‖ symbol. This circuit is verified by doing various simulations using spectre. In the process, you will learn to use spectre, waveform window options, waveform calculator, etc... You will learn the Layout Editor basics by concentrating on designing an ―Inverter‖ through automatic layout generation. Then you will go ahead with completing the other layouts. After that, you will run DRC, LVS checks on the layout, Extract parasitics and back-annotate them to the simulation environment. After completing the parasitic back- annotation flow, design is ready for generating GDSII.

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Table of Contents
General Notes ........................................................................................ 5

Lab 1: AN INVERTER............................................................................. 9 Schematic Entry ................................................................. 10 Building the Inverter_Test Design ....................................... 19 Analog Simulation .............................................................. 21 Creating Layout View of Inverter ......................................... 29 Parasitic Extraction ............................................................ 32 Creating the Configuration View ......................................... 37 Generating Stream Data ..................................................... 43 Lab 2: MOS DIFFERENTIAL AMPLIFIER…………………………………………...45 Schematic Entry ................................................................. 46 Analog Simulation….. ......................................................... 51 Creating a Layout View of Diff_ Amplifier ..... Error! Bookmark not defined. Physical Verification ............... Error! Bookmark not defined. Lab 3: COMMON SOURCE AMPLIFIER ............................................... 62 Schematic Entry ................................................................. 63 Symbol Creation ..................... Error! Bookmark not defined. Building the Common Source Amplifier Test Design ........... 64 Analog Simulation with Spectre ............ Error! Bookmark not defined. Creating a layout view of Common Source Amplifier ...... Error! Bookmark not defined. Lab 4: COMMON DRAIN AMPLIFIER ...... Error! Bookmark not defined. Schematic Entry ..................... Error! Bookmark not defined. Symbol Creation ..................... Error! Bookmark not defined. Building the Common Drain Amplifier Test Design ........ Error! Bookmark not defined. Analog Simulation with Spectre .......................................... 70 Creating a layout view of Common Drain Amplifier ............. 71 Lab 5: OPERATIONAL AMPLIFIER ...................................................... 72 Schematic Entry ................................................................. 73 Symbol Creation ................................................................. 73

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.... Analog Simulation with Spectre .. 80 Creating a layout view of R-2R DAC ................................................................................................................. Error! Bookmark not defined.......................... Error! Bookmark not defined.... 81 Lab 7: SAR BASED ADC ....... Creating a layout view of Operational Amplifier ......................................................................... Error! Bookmark not defined........ Building the R-2R DAC Test Design ................... Error! Bookmark not defined.. Symbol Creation .......................... 82 Design Information .............. Mixed Signal Simulation Using AMS in ADE ......... Schematic Entry . Error! Bookmark not defined.... Error! Bookmark not defined...... 74 Analog Simulation with Spectre . 83 Schematic Entry .......... 83 Import the Verilog Module into ADE Using Verilog In ...Building the Operational Amplifier Test Design ........ Error! Bookmark not defined..... 4 . Error! Bookmark not defined.......... Lab 6: R-2R DAC ...

MMSIM101 and Assura41 correctly: %> %> %> %> setenv setenv setenv setenv CDSHOME <IC615-installation-home> MMSIMHOME <MMSIM101-installation-home> PVHOME <Assura41-installation-home> AMSHOME <IUS92-installation-home> You will also need to ensure that the IUS92 is setup correctly for Mixed Signal Simulation. ensure that you’ve set up IUS92. Ensure the software mentioned above is correctly setup. Lab Getting Started 1. These labs were designed for use with Incisive Unified Simulator92. To setup the lab environment. Please read through this section completely. These labs were designed to be run using Cadence Virtuoso tool and Assura tool.General Notes There are a number of things to consider before beginning these lab exercises. Source the C-Shell related commands file i. 2. 5 . IC615 and Assura41. Log in to your workstation using the username and password. (cshrc file). Before running any of these labs. and perform any needed steps in order to ensure a successful workshop. please perform the following steps: 1.e. IC615.

Change to the course directory by entering this command: > cd ~/Database/cadence_ms_labs_614 You will start the Cadence Design Framework II environment from this directory because it contains cds. type csh at the command prompt to invoke the C shell. which is the local initialization file. >csh >source cshrc 3. >which spectre It gives the complete path of MMSIM101 tool Installation. >which ncsim It gives the complete path of IUS92 tool Installation. In a terminal window. The library search paths are defined in this file. type the below command in the terminal window and enter: >which virtuoso It gives the complete path of IC615 tool Installation.lib. To verify that the path to the software is properly set in the cshrc file. >which assura It gives the complete path of Assura41 tool Installation. 2.The home directory has a cshrc file with paths to the Cadence installation. Inside Work folder you can create new cell / 6 . Starting the Cadence Software Use the installed database to do your work and the steps are as follows: 1. The Cadence_ms_labs_614 directory contains Solutions folder and also Work folder.

/dig_source Contains verilog codes for SAR register and clock .var . 2.modifications of the cell locally without affecting your Source cell present inside Solutions directory. Contains layer map file for GDSII format Containing the Assura and Diva verification files Contains ASCII versions of the oa22 techfiles . /hdl. File defines the work library for AMS simulation Reference manual & user manual for gpdk180nm technology. In the same terminal window. contains a technology library for the design (gpdk180nm).lib . /models . /docs File containing pointer to the Cadence OA22 initialization file. /techfiles . /Solutions Contains a local copy of all the lab experiments including test circuit for simulation. /pv . /stream .cdb . 7 . enter: > virtuoso & The virtuoso or Command Interpreter Window (CIW) appears at the bottom of the screen. /libs. Contains spectre models of components for simulation in gpdk180nm technology. Lab directory details: . /cds.

End of General Notes 8 . Keep opened CIW window for the labs.‖ window appears.Close command..3. 4.. close it with the File . If the ―What’s New .

Lab 1: AN INVERTER Schematic Capture 9 .

Schematic Entry Objective: To create a library and build a schematic of an Inverter Below steps explain the creation of new library ―myDesignLib‖ and we will use the same throughout this course for building various cells that 10 .

4. 11 . Creating a New library 1.we going to create in the next labs.New – Library. select option Attach to an existing techfile and click OK. The new library form appears. In the next ―Technology File for New library‖ form. verify that the path to the library is set to ~/Database/cadence_ms_labs_614 and click OK. Note: A technology file is not required if you are not interested to do the layouts for the design 5. In the field of Directory section. 2. execute File . Execute Tools – Library Manager in the CIW or Virtuoso window to open Library Manager. In the ―New Library‖ form. type ―myDesignLib‖ in the Name section. In the Library Manager.

After creating a new library you can verify it from the library manager. If you right click on the ―myDesignLib‖ and select properties. 7. In the ―Attach Design Library to Technology File‖ form. Creating a Schematic Cellview In this section we will learn how to open new schematic window in the new ―myDesignLib‖ library and build the inverter schematic as shown in the figure at the start of this lab. you will find that gpdk180 library is attached as techlib to ―myDesignLib‖. select gpdk180 from the cyclic field and click OK. 12 . 8.6.

3. Click OK when done the above settings. Tip: You can also execute Create — Instance or press i. execute File – New – Cellview. click the Instance fixed menu icon to display the Add Instance form. 2. 13 .1. 2. A blank schematic window for the Inverter design appears. and the property values given in the table on the next page as you place each component. Click on the Browse button. Set up the New file form as follows: Do not edit the Library path file and the one above might be different from the path shown in your form. This opens up a Library browser from which you can select components and the symbol view . You will update the Library Name. Cell Name. In the CIW or Library manager. Adding Components to schematic 1. In the Inverter schematic window.

This is a table of components for building the Inverter schematic. Library name gpdk180 gpdk180 Cell Name pmos nmos Properties/Comments For M0: Model name = pmos1. Click the Pin fixed menu icon in the schematic window. use the Edit— Properties— Objects command to change the parameters. click Cancel in the Add Instance form or press Esc with your cursor in the schematic window. The Add pin form appears. L=180n If you place a component with the wrong parameter values. or use the Edit— Rotate command after they are placed. After you complete the Add Instance form. Use the Edit— Move command if you place components in the wrong location. 2. Pin Names Direction vin vout Input Output 14 . You can also execute Create — Pin or press p. L=180n For M1: Model name = nmos1. move your cursor to the schematic window and click left to place a component. You can rotate components at the time you place them. 4. W= 2u. Type the following in the Add pin form in the exact order leaving space Between the pin names. After entering components.3. W= wp. Adding pins to Schematic 1.

2. execute Window— Fit or press the f bindkey. 3. 4. 3. A diamond shape appears over the starting point of this wire. Follow the prompts at the bottom of the design window and click left on the destination point for your wire. Click the Check and Save icon in the schematic editor window.Make sure that the direction field is set to input/output/inputOutput when placing the input/output/inout pins respectively and the Usage field is set to schematic. click on a pin of one of your components as the first point for your wiring. Saving the Design 1. In the schematic window. Symbol Creation Objective: To create a symbol for the Inverter 15 . A wire is routed between the source and destination points. Complete the wiring as shown in figure and when done wiring press ESC key in the schematic window to cancel wiring. 1. In the schematic window. 3. Click the Wire (narrow) icon in the schematic window. Adding Wires to a Schematic Add wires to connect components and pins in the design. or execute Create — Wire (narrow). Select Cancel from the Add – pin form after placing the pins. You can also press the w key. Observe the CIW output area for any errors.

execute Create — Cellview— From Cellview. A symbol view is extremely important step in the design process. With the Edit Options function active. Verify that the From View Name field is set to schematic. you can control the appearance of the symbol to generate. In the Inverter schematic window. The symbol view must exist for the schematic to be used in a hierarchy. Click OK in the Cellview From Cellview form. In addition. 2. with the Tool/Data Type set as SchematicSymbol. 1. The Symbol Generation Form appears. Modify the Pin Specifications as follows: 16 . and the To View Name field is set to symbol. 3. the symbol has attached properties (cdsParam) that facilitate the simulation and the design of the circuit.In this section. you will create a symbol for your inverter design so you can place it in a test circuit for simulation. 4. The Cellview From Cellview form appears.

6. A new window displays an automatically created Inverter symbol as shown here.5. Click OK in the Symbol Generation Options form. Editing a Symbol 17 .

6. until the green rectangle is highlighted. 2. execute File — Close to close the symbol view window. Move the cursor over the automatically generated symbol. 4. 18 . click Automatic. click left to select it. 3. After creating symbol. 5. Execute Create — Selection Box.In this section we will modify the inverter symbol to look like a Inverter gate symbol. 8. Execute Create – Shape – polygon. After creating the triangle press ESC key. In the symbol editor. and draw a shape similar to triangle. similarly select the red rectangle and delete that. 1. Click Delete icon in the symbol window. In the Add Selection Box form. 7. You can move the pin names according to the location. A new red selection box is automatically added. Execute Create – Shape – Circle to make a circle at the end of triangle. click on the save icon in the symbol editor window to save the symbol.

execute File— New— Cellview. ton=10n. Building the Inverter_Test Circuit 1. 19 . you will run simulation on this design 1. Otherwise. Library name myDesignLib analogLib analogLib Note: Cellview name Inverter vpulse vdc. 2. Using the component list and Properties/Comments in this table. gnd Properties/Comments Symbol v1=0. Set up the New File form as follows: 3. your circuit will have no power.td=0 tr=tf=1ns. build the Inverter_Test schematic.Building the Inverter_Test Design Objective: To build an Inverter Test circuit using your Inverter You will create the Inverter_Test cellview that will contain an instance of the Inverter cellview. v2=1.8.8 Remember to set the values for VDD and VSS. In the CIW or Library Manager. Click OK when done. T=20n vdc=1. A blank schematic window for the Inverter_Test design appears. In the next section.

2. Leave your Inverter_Test schematic window open for the next section. 4. The schematic should look like this. or execute Create— Wire (narrow). 5. 3. Add the above components using Create — Instance or by pressing I. Click the Wire (narrow) icon and wire your schematic. 4. Click on the Check and Save icon to save the design. 20 . 6. Tip: You can also press the w key. Click Create — Wire Name or press L to name the input (Vin) and output (Vout) wires as in the below schematic.

a high speed. 1. Click the browse button to add gpdk. set the Simulator field to spectre (Not spectreS) and click OK. 1. Starting the Simulation Environment Start the Simulation Environment to run a simulation. In the Choosing Simulator form. DC characteristics and we will do Parametric Analysis after the initial simulation. Setting the Model Libraries The Model Library file contains the model files that describe the nmos and pmos devicesduring simulation. 1. execute Setup – Simulator /Directory /Host. The Model Library Setup form appears. highly accurate analog simulator.scs file. Use this simulator with the Inverter_Test design. execute Launch – ADE L The Virtuoso Analog Design Environment (ADE) simulation window appears. In the simulation window (ADE).Analog Simulation with Spectre Objective: To set up and run simulations on the Inverter_Test design In this section. In the Inverter_Test schematic window. Remember to select the section type as stat in front of the gpdk. 21 . 2.scs if not added by default as shown in the Model Library Setup form. we will run the simulation for Inverter and plot the transient. Choosing a Simulator Set the environment to use the Spectre® tool.Execute Setup . which is made-up of analog components. In the simulation window (ADE).Model Libraries.

click the Choose . 1. This is a dynamic form. To view the model file. move the cursor and click OK. Choosing Analyses This section demonstrates how to view and select the different types of analyses to complete the circuit when running the simulation.Choose.Analyses icon. the bottom of the form changes based on the selection above. In the Simulation window (ADE). highlight the expression in the Model Library File field and Click Edit File. To complete the Model Library Setup. It also allows you to use the Edit button to view the model file. You can also execute Analyses . The Model Library Setup allows you to include multiple model files. 2. 22 . The Choosing Analysis form appears.Your Model Library Setup window should now looks like the below figure.

turn on Save DC Operating Point. Double click the Select Component. In the DC Analyses section.8 respectively. e. In the Analysis section select tran b. c. Turn on the Component Parameter. Select ―DC Voltage‖ in the Select Component Parameter form and click OK. g. Which takes you to the schematic window. select dc. To set up for DC Analyses: a. b.2. and then click Apply. In the Analyses section. In the analysis form type start and stop voltages as 0 to 1. 23 . Select input signal vpulse source in the test schematic window. f. f. d. Set the stop time as 200n c. Check the enable button and then click Apply. Click at the moderate or Enabled button at the bottom. 3. To setup for transient analysis a.

Set the value of the wp variable: With the wp variable highlighted in the Table of Design Variables. The Editing Design Variables form appears. 3. click the Edit Variables icon. 24 .4. 1. Click OK or Cancel in the Editing Design Variables window. In a few moments. 2. click on the variable name wp and enter the following: Value(Expr) 2u Click Change and notice the update in the Table of Design Variables. In the Simulation window. Click Copy From at the bottom of the form. The design is scanned and all variables found in the design are listed. the simulation will not run. the wp variable appears in the Table of Design variables section. Setting Design Variables Set the values of any design variables in the circuit before simulating. Otherwise. 3. Click OK in the Choosing Analyses Form.

this will create the netlist as well as run the simulation. Follow the prompt at the bottom of the schematic window. When simulation finishes. Click on output net Vout. Execute Simulation – Netlist and Run in the simulation window to start the Simulation or the icon. 2.Selecting Outputs for Plotting 1. DC plots automatically will be popped up along with log file. the Transient. Execute Outputs – To be plotted – Select on Schematic in the simulation window. 2. 25 . Does the simulation window look like this? Running the Simulation 1. Press ESC with the cursor in the schematic after selecting it. input net Vin of the Inverter.

2. The Simulator state is saved. variable etc. execute Session – Save State. This information restores the simulation environment without having to type in all of setting again. which stores information such as model library file. The Saving State form appears. analysis. Set the Save as field to state1_inv and make sure all options are selected under what to save field.Saving the Simulator State We can save the simulator state. Click OK in the saving state form. outputs. 1. 3. Loading the Simulator State 26 . In the Simulation window.

except the data is for a full range of sweeps for each parametric step. of the PMOS device of the Inverter design by sweeping the value of wp. 27 . Run a simulation before starting the parametric tool. From the ADE window execute Session – Load State.1. set the State name to state1_inv as shown 3. You will run a parametric DC analysis on the wp variable. The Spectre sweep feature provides sweep data at only one specified condition. Click OK in the Loading State window. You will start by loading the state from the previous simulation run. 2. In the Loading State window. Parametric Analysis Parametric Analysis yields information similar to that provided by the Spectre® sweep feature.

In the Simulation window.Run the simulation and check for errors. 3. A selection window appears with a list of all variables in the design that you can sweep. execute Tools—Parametric Analysis. Execute Analysis—Start. Starting the Parametric Analysis Tool 1. This list includes the variables that appear in the Design Variables section of the Simulation window. In the Parametric Analysis form. double click left on wp. a single waveform in the waveform window displays the DC Response at the Vout node. execute Setup—Pick Name For Variable—Sweep 1. 5. 4. The Variable Name field for Sweep 1 in the Parametric Analysis form is set to wp. 28 . When the simulation ends. The Parametric Analysis form appears. In the selection window. Change the Range Type and Step Control fields in the Parametric Analysis form as shown below: Range Type Step Control From/To Auto From Total Steps 1u 10 To 10u These numbers vary the value of the wp of the pmos between 1um and 10um at ten evenly spaced intervals. 2.

To do this use edits property option. Once the runs are completed the wavescan window comes up with the plots for different runs. Look in the upper right corner of the window. Note: Change the wp value of pmos device back to 2u and save the Schematic before proceeding to the next section of the lab. Creating Layout View of Inverter Objective : to Create the layout of the inverter 29 .The Parametric Analysis window displays the number of runs remaining in the analysis and the current value of the swept variable(s).

Check the Cellname (Inverter). This gives a New Cell View Form 3.1. From the Inverter schematic window menu execute Launch – Layout XL. To Move a component. 4. Viewname (layout). Select the component and execute Edit – Properties. Generate Layout form appears. 2. Execute Connectivity – Generate – All from Source or click the icon in the layout editor window. A Startup Option form appears. Adding Components to Layout 1. 3. Click OK from the New Cellview form. 2. To rotate a component. Now select the degree of rotation from the property edit form. Select Create New option. 4. Making interconnection 30 . Click OK which imports the schematic components in to the Layout window automatically. Select the component and execute Edit -Move command. Re arrange the components with in PR-Boundary as shown in the next page. LSW and a blank layout window appear along with schematic window.

Psubstrate Connection For Metal1. as given in below table Connection For Metal1. Execute Connectivity –Nets – Show/Hide selected Incomplete Nets or click the icon in the Layout Menu. Save your design by selecting File — Save or click layout.1. and layout should appear as below.Poly Connection For Metal1. From the layout window execute Create – Shape – Path/ Create wire or Create – Shape – Rectangle (for vdd and gnd bar) and select the appropriate Layers from the LSW window and Vias for making the inter connections Creating Contacts/Vias You will use the contacts or vias to make connections between two different layers. 3.Nwell Connection Contact Type Metal1-Poly Metal1-Psub Metal1-Nwell Saving the design 1. which shows the guide lines (or flight lines) for the inter connections of the components. Move the mouse pointer over the device and click LMB to get the connectivity information. Execute Create — Via or select command to place different Contacts. to save the 31 . 1. 2.

The DRC form appears. but rule file may be missing. Select the Technology as gpdk180. Press shift – f in the layout window to display all the levels. Open the Inverter layout form the CIW or library manger if you have closed that.Physical Verification Running a DRC 1. 2. Select Assura . Your DRC form should appear like this 32 . This automatically loads the rule file. The Library and Cellname are taken from the current design window.Run DRC from layout window.

Click View – Summary in the ELW to find the details of errors. 6. correct all the DRC errors and Re – run the DRC. 4. You can click on the watch log file to see the log file.3. click on close to terminate the DRC run. 9. 5. Click OK to start DRC. If there are no errors in the layout then a dialog box appears with No DRC errors found written in it. A Progress form will appears. 7. When DRC finishes. 8. You can refer to rule file also for more information. Also the errors highlight in the design itself. If there any DRC error exists in the design View Layer Window (VLW) and Error Layer Window (ELW) appears. and then click Yes to view the results of this run. a dialog box appears asking you if you want to view your DRC results. 33 .

The Assura Run LVS form appears. 34 . If the schematic and layout matches completely. Select Assura – Run LVS from the layout window. you will get the form displaying Schematic and Layout Match. 2. 4.ASSURA LVS In this section we will perform the LVS check that will compare the schematic netlist and the layout netlist. 3. It will automatically load both the schematic and layout view of the cell. The LVS begins and a Progress form appears. Running LVS 1. Change the following in the form and click OK.

In the LVS debug form you can find the details of mismatches and you need to correct all those mismatches and Re – run the LVS till you will be able to match the schematic with layout. LVS debug form appears. Select output type under Setup tab of the form. the layout should match with schematic completely to ensure that all parasites will be backannoted to the correct schematic nets. Assura RCX Before using RCX to extract parasitic devices for simulation. 35 . and you are directed into LVS debug environment. 6. 7. From the layout window execute Assura – Run RCX. Running RCX 1. a form informs that the LVS completed successfully and asks if you want to see the results of this run. 2.5. Change the following in the Assura parasitic extraction form. Click Yes in the form. If the schematic and layout do not matches.

5. In the Extraction tab of the form. In the Filtering tab of the form. 36 . Click OK in the Assura parasitic extraction form when done. a dialog box appears. You can open the av_extracted view from the library manager and view the parasitic. Enter Power Nets as vdd!. vss! and Enter Ground Nets as gnd! 5. The RCX progress form appears. 6. choose Extraction type. Cap Coupling Mode and specify the Reference node for extraction.3. When RCX completes. informs you that Assura RCX run Completed successfully. 4. in the progress form click Watch log file to see the output log file.

1. execute File – New – Cellview 2. Click OK in create New File form.Creating the Configuration View In this section we will create a config view and with this config view we will run the simulation with and without parasitic. In the Create New file form. In the CIW or Library Manager. 37 . The Hierarchy Editor form opens and a New Configuration form opens in front of it. set the following: 3.

The Global Bindings lists are loaded from the template. Click Use template at the bottom of the New Configuration form and select Spectre in the cyclic field and click OK. The hierarchy editor displays the hierarchy for this design using table format.4. Change the Top Cell View to schematic and remove the default entry from the Library List field. 38 . 5. 6. Click OK in the New Configuration form.

Close the Hierarchy Editor window. The design hierarchy changes to tree format. 9. Save the current configuration. Click the Tree View tab. Execute File – Close Window. The form should look like this: 8.7. 39 .

Open Configuration or Top cellview form appears. Executing Session– Load state. The Inverter_Test schematic and Inverter_Test config window appears. Notice the window banner of schematic also states Config: myDesignLib Inverter_Test config. Click Netlist and Run icon to start the simulation. source and loads. 6. In the CIW. There are no parasitic components. From the Library Manager open Inverter_Test Config view. In the form. In the waveform window execute Tools – Calculator. the Analog Design Environment window loads the previous state. 3. The simulation takes a few seconds and then waveform window appears. 40 . Now you need to follow the same procedure for running the Simulation. Execute Launch – ADE L from the schematic window. The calculator window appears. turn on the both cyclic buttons to Yes and click OK. note the netlisting statistics in the Circuit inventory section.To run the Circuit without Parasites 1. 5. This list includes all nets. 4. designed devices. 2. Also note down the circuit inventory section. Measuring the Propagation Delay 1.

3. Execute OK and observe the expression created in the calculator buffer.2. 7. 41 . and select the output waveform. we will change the configuration to direct simulation of the av_extracted view which contains the parasites. Close the calculator window.9 volts.9. Click on Evaluate the buffer icon to perform the calculation. select the wave button and select the input waveform from the waveform window. 1. this will open the delay data panel. Open the same Hierarchy Editor form. 8. at 0. 6. Repeat the same for Signal2. Place the cursor in the text box for Signal1. 5. From the functions select delay. note down the value returned after execution. this directs the calculator to calculate delay at 50% i.e. which is already set for Inverter_Test config. 4. To run the Circuit with Parasites In this exercise. Set the Threshold value 1 and Threshold value 2 to 0.

2. Select the Tree View icon: this will show the design hierarchy in the tree format. 3. Click right mouse on the Inverter schematic. A pull down menu appears. Select av_extracted view from the Set Instance view menu, the View to use column now shows av_extracted view.

4. Click on the Recompute the hierarchy icon, is now updated from schematic to av_extracted view.

the configuration

5. From the Analog Design Environment window click Netlist and Run to start the simulation again.

7. When simulation completes, note the Circuit inventory conditions, this time the list shows all nets, designed devices, sources and parasitic devices as well. 8. Calculate the delay again and match with the previous one. Now you can conclude how much delay is introduced by these parasites, now our main aim should to minimize the delay due to these parasites so number of iteration takes place for making an optimize layout.

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Generating Stream Data
Streaming Out the Design
1. Select File – Export – Stream from the CIW menu and Virtuoso Xstream out form appears change the following in the form.

2. Click on the Options button. 3. In the StreamOut-Options form select Layers tab and click OK. under

4. In the Virtuoso XStream Out form, click Translate button to start the stream translator. 5. The stream file Inverter.gds is stored in the specified location.

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Streaming In the Design
1. Select File – Import – Stream from the CIW menu and change the followingin the form.

You need to specify the gpdk180_oa22.tf file. This is the entire Technology file that has been dumped from the design library. 2. Click on the Options button. 3. In the StreamOut-Options form select Layers tab and click OK. under

4. In the Virtuoso XStream Out form, click Translate button to start the stream translator. 5. From the Library Manager open the Inverter cellview from the GDS_LIBlibrary and notice the design. 6. Close all the windows except CIW window, which is needed for the next lab.

END OF LAB 1
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Lab 2: DIFFERENTIAL AMPLIFIER Schematic Capture 45 .

1. A blank schematic window for the design appears. After you complete the Add Instance form. This opens up a Library browser from which you can select components and the Symbol view. move your cursor to the schematic window and click left to place a component. execute Create— Instance to display the Add Instance form. execute File – New – Cellview. You will update the Library Name. 46 . Click OK when done. and the property values given in the table on the next page as you place each component. 2.Schematic Entry Objective: To create a new cell view and build Differential Amplifier Creating a Schematic cellview Open a new schematic window in the myDesignLib library and build the Differntial_Amplifier design. 3. Adding Components to schematic 1. Click on the Browse button. In the Differential Amplifier schematic window. In the CIW or Library manager. Set up the Create New file form as follows: 3. Cell Name.

W= 4. W= 3u . Type the following in the Add pin form in the exact order leaving space between the pin names. NM1) . L= 1u Adding Wires to a Schematic 47 .V1.V2 Vout vdd. You can also execute Create – Pin or press p. W= 15u . NM3) . The Add pin form appears. L= 1u Model Name =pmos1 (PM0. L= 1u Model Name =nmos1 (NM2. 1.This is a table of components for building the Differential Amplifier schematic. vss. Select Cancel from the Add pin form after placing the pins. Pin Names Idc. Library name gpdk180 gpdk180 gpdk180 Cell Name nmos nmos pmos Properties/Comments Model Name = nmos1 (NM0. 4. In the schematic window. Click the Pin fixed menu icon in the schematic window. Direction Input Output InputOutput Make sure that the direction field is set to input/ouput/inputoutput when placing the input/output/inout pins respectively and the Usage field is set to schematic. 3. 2. execute View— Fit or press the f bindkey.5u . After entering components. PM1). click Cancel in the Add Instance form or press Esc with your cursor in the schematic window Adding pins to Schematic Use Create – Pin or the menu icon to place the pins on the schematic window.

Wire (narrow). 48 . and the To View Name field is set to symbol. Observe the CIW output area for any errors. 5. The Symbol Generation Form appears. In the Differential Amplifier schematic window. 4. Complete the wiring as shown in figure and when done wiring press ESC key in the schematic window to cancel wiring. You can also press the w key. Click the Check and Save icon in the schematic editor window. Click OK in the Symbol Generation Options form. or execute Create . Saving the Design 1. Symbol Creation Objective: To create a symbol for the Differential Amplifier 1. Click OK in the Cellview from Cellview form. you can control the appearance of the symbol to generate. With the Edit Options function active. 2. Modify the Pin Specifications as in the below symbol. 2. 2. 1. 3. Click the Wire (narrow) icon in the schematic window. execute Create — Cellview— From Cellview.Add wires to connect components and pins in the design. The Cellview from Cellview form appears. with the Tool/Data Type set as Schematic Symbol. Verify that the From View Name field is set to schematic.

7. execute File— Close to close the symbol view window. A new red selection box is automatically added. Modifying automatically generated symbol so that it looks like below Differential Amplifier symbol. click on the save icon in the symbol editor window to save the symbol. 8. In the symbol editor. Execute Create— Selection Box. 9.6. A new window displays an automatically created Differential Amplifier symbol. click Automatic. In the Add Selection Box form. Building the Diff_amplifier_test Design 49 . After creating symbol.

Frequency= 1K Vdd=2. Amplitude= 5m. A blank schematic window for the Diff_ amplifier_test design appears. build the Diff_amplifier_test schematic. Using the component list and Properties/Comments in this table.5 Dc current = 30u analogLib analogLib Note: vdd. Otherwise your circuit will have no power. execute File— New— Cellview. or execute Create— Wire (narrow). Click the Wire (narrow) icon and wire your schematic. Tip: You can also press the w key. Building the Diff_amplifier_test Circuit 1. Vss= -2.Objective: To build Differential Amplifier Test circuit using your Differential Amplifier 1. 3. 2. Library name myDesignLib analogLib Cellview name Diff_amplifier vsin Properties/Comments Symbol Define specification as AC Magnitude= 1. Click OK when done.5 . 50 . vss. Set up the Create New File form as follows: 3. gnd Idc Remember to set the values for VDD and VSS. In the CIW or Library Manager.

Analog Simulation with Spectre Objective: To set up and run simulations on the Differential Amplifier Test design. Leave your Diff_amplifier_test schematic window open for the next section.4. 51 . The schematic should look like this. 5. Click on the Check and save icon to save the design. 6.

click Add and click OK. Select stat in Section field. Setting the Model Libraries 1. execute Setup — Simulator /Directory/Host.Model Libraries.In this section. Starting the Simulation Environment 1. we will run the simulation for Differential Amplifier and plot the transient. Click Setup . In the Model Library Setup form. 2. 52 . Choosing a Simulator 1. 2./models/spectre directory. In the Diff_amplifier_test schematic window. execute Launch – ADE L. set the Simulator field to spectre (Not spectreS) and click OK. DC and AC characteristics. The Analog Design Environment simulation window appears.scs file in the . In the simulation window or ADE. click Browse and find the gpdk180. Note: Step 2 should be executed only if the model file not loaded by default. In the Choosing Simulator form.

select start and stop voltages as -5 to 5 respectively. Which takes you to the schematic window. In the Simulation window. The Choosing Analysis form appears. select dc. Set the stop time as 5m c. e.Choosing Analyses 1. Click at the moderate or Enabled button at the bottom. c. f. In the analysis form.Analyses icon. Select input signal Vsin for dc analysis. 2. g. and then click Apply. To set up for DC Analyses: a. turn on Save DC Operating Point. To setup for transient analysis a.Choose. In the Analysis section select tran b. Double click the Select Component. This is a dynamic form. Turn on the Component Parameter d. In the DC Analyses section. Check the enable button and then click Apply. b. You can also execute Analyses . In the Analyses section. 53 . 3. the bottom of the form changes based on the selection above. click the Choose .

54 . To set up for AC Analyses form is shown in the previous page.4.

Press ESC with the cursor in the schematic after selecting node. 1. In the Sweep Range section select start and stop frequencies as 150 to 100M d. 2. Check the enable button and then click Apply. Click OK in the Choosing Analyses Form. select ac. b. Does the simulation window look like this? 55 . Select Points per Decade as 20. c. In the Analyses section. In the AC Analyses section.a. 5. Follow the prompt at the bottom of the schematic window. Selecting Outputs for Plotting Select the nodes to plot when simulation is finished. turn on Frequency. e. Click on outputnet Vo. Execute Outputs – To be plotted – Select on Schematic in the simulation window. input net Vin of the Diff_amplifier.

When simulation finishes. this will create the netlist as well as run the simulation. 2. the Transient.Running the Simulation 1. Execute Simulation – Netlist and Run in the simulation window to start the simulation. 56 . DC and AC plots automatically will be popped up along with netlist.

To calculate the gain of Differential pair: Configure the Differential pair schematic as shown below – 57 .

open the ADE L.Now. The following waveform appears as shown below – To Calculate the BW of the Differential pair : Open the calculator and select the bandwidth option. select the waveform of the gain in dB and press Evaluate the buffer - 58 . Next go to ResultsDirect plot select AC dB20 and output from the schematic and press escape. from LAUNCH ADE L . choose the analysis set the ac response and run the simulation. from Simulation Run.

Measure the gain at 100hz and at 100Mhz.note down the value of the gain in dB.To Calculate the CMRR of the Differential pair : Configure the Differential pair schematic to calculate the differential gain as shown below – In the ADE L. as shown below – 59 . plot the ac response with gain in dB.

Configure the Differential pair schematic to calculate the common-mode gain as shown below – In the ADE L. note down the value of the gain in dB. Measure the gain at 100hz and at 100Mhz. as shown below – 60 . plot the ac response with gain in dB.

outputs. Ad – (-Ac). variable etc. Set the Save as field to state1_diff_amp and make sure all options are selected underwhat to save field. 2. 61 . 1.. The Simulator state is saved. Click OK in the saving state form. and use the necessary equation like r01|| r02 .e. Saving the Simulator State We can save the simulator state. This information restores the simulation environment without having to type in all of setting again.Calculate the CMRR = | | . execute Session – Save State. analysis. For the output impedance note down the output resistance of the pmos and nmos transistors at the ouput side. In the Simulation window. add the gains in dB i. The Saving State form appears. which stores information such as model library file.

v testbench. The NCO directory contains rclabs folder. You will Perform this lab in the Simulation directory.v –access +rwc –mess –gui 1. work In this lab.v testbench. and perform any needed steps in order to ensure a successful workshop.v mux_2to1. change the directory to Simulation and for Synthesis and P&R select work directory Lab directory details: Simulation Contains the lab experiments including Testbences for simulating the codes. Please read through this section completely. It’s a place to run Synthesis and P&R for NCO.6: NCO(10 Bit number controlled oscillator) There are a number of things to consider before beginning the lab exercises. Now the Console & Design Browser window opens 62 . Inside rclabs folder you will see many other directories but for IUS. you will simulate the design using the Incisive simulator.v mux_2to1. This directory contains the following files (which you should briefly examine) describing the NCO and its testbenches: File(s) Description: mem.v phase_inc.v Compile .v top.v phase_inc. Elaborate and Simulate using Irun Utility: Run the below command irun mem.v top.

Examine the Design Browser window. interrupt. Browser menu item or the Design Browser button. reset. You can use the Tool Bar to run. Tour the Graphical Interface 1. 63 . and start other graphical tools. 2. show the value of objects. b. Display the objects of a scope and their value in the Objects List pane (Select any displayed scope in the Scope Tree pane). c. or next the simulation. You can use the Menu Bar to run or step the simulation. or disconnect the simulation. and shut down the interface or the simulation. a. set scopes and stops.2. Before proceeding to the next step analyze the messages in the terminal window The -gui option opens the Console and Design Browser windows. step. Open an existing Design Browser window or select the Windows— new— Design. You can use the command line interface to the simulation in the I/O Region. Examine the Console window. a.

b. Add the selected signal(s) to the Waveform window (select the Waveform button or the Add Selected button or drag and drop the signals into the Waveform window).New Waveform menu item or the Waveform button. a. 64 . Tour the Waveform window. b. Open an existing Waveform window or select the Windows . 3. Display the component instances of the scope (double-click the scope in the Scope Tree pane). In the Design Browser window select all signals at the testbench scope.Note: To add additional signals simply select them in any window and click the Waveform button again. The simulator creates a default SHM database and sets a probe on any selected signals and opens a Waveform window displaying the selected signals.

or for the duration entered in the time field (i. As no such window yet exists. and select the fill Module button. and makes it the default Source Browser target window.Current Time range. Schematic Tracer and Waveform window. to display the testbench content. this opens a Source Browser window displaying the source of the Top-level unit. a. and again select the fill Module button. In the Source Browser window ensure that just the top-level scope is selected (navigate up as needed and Select—This Scope) and send it to the target Schematic Tracer window.e 40ns). 2. this opens a Schematic Tracer window displaying the top-level unit. Select the Edit . In the Design Browser window select the top-level (mem_test) scope and select the Source Browser button to send it to the target Source Browser window.Run the simulation until the next breakpoint. Select the Zoom Full button to fit all displayed elements.Examine the Design and Testbench Hierarchy In this section of the lab you visit the Source Browser.All menus item. In the left sidebar. select the Design Browser tab toexpand the sidebar area and display the embedded Design Browser. in which you: a. c. and makes it the default Waveform target window.Select . b. to Expand the second level content. and makes it the default Schematic Tracer target window. 3. In the Source Browser window ensure that just the top-level scope is selected and send it tothe target Waveform window. As no such window yet exists. As no such window yet exists. this opens a Waveform window displaying the signals of the top-level unit. 65 . --. --. Ensure that the top-level scope is still selected. 1.

Reset the simulation back to time ― 0 ―.--. Further follow the following steps: 1. Once the simulation is done you can see the following waveform window and console window with the outputs. Highlight the output pin(data_out[5:0]) and right click on it 66 . --.Move primary cursor to previous edge of select signal.

2. Click on Trace and select Analog/Sample+Hold 3. Now we can see based on the numerical value (hexadecimal) corresponding output wave form can be seen. Now select the symbol which is highlighted by red circle 3 . 67 .

4. Drag and observe the waveform for different numerical values 68 .

Go to directory /NCO/rclabs/work. The tool window look like the below image: 69 .Lab7: Automatic layout generation followed by post layout extraction and simulation of the circuit studied in Lab 6 In this lab we will do the Synthsesis and Physical Design of NCO Design for which simulation is done in Lab6. The below picture can be seen after typing the above command. Lets do the Synthesis first. Invoke RTL Compiler by typing ―rc -gui‖ on your terminal window. 1. Synthesis will be done using RTL Compiler and Physical Design will be done using Encounter Digital Implementation System.

r.. Give the path of the library w. 2.t to the directory you are in using the command: ―set_attribute lib_search_path .The terminal will look like the below image after the tool is invoked./library‖ 3 Give the path of the RTL files with respect to the directory you are in 70 .

lib‖ ―slow_normal.v phase_inc. Give the standard delay constraints using: 71 . The RTL files are in the directory name ―rtl‖: ―read_hdl {mem.v top.. There is another library there in that directory with name ―slow_highvt.using the below command: ―set_attribute hdl_search_path .lib‖ is the name of the library file in the directory ―library‖./rtl‖ 4 Read the library from the directory specified in giving the path for the library files in step 2 using the command: ―set_attribute library slow_normal.v mux_2to1. 7 Give the command to see the circuit in Tool window: The terminal window after the step 7 will look like The Tool window looks like image on next page 8.lib‖.v}. Any one of these two libraries could be used at a time. 5 Read the RTL files from the directory specified in the path in step 3. 6 Now Elaborate the design using ―elaborate‖command.

―read_sdc . Synthesize the circuit using the command: ―synthesize -to_mapped effort medium‖. The terminal window and the synthesized circuit in tool window will appear to be as on next page: 72 ./constraints_top. 9. The terminal window looks like the image on next page.g‖.

Similarly for Gates ―report gates‖. Check Power dissipation using ―report power‖.10. After the Synthesis Physical Design can be done by invoking the tool ―Encounter Digital implementation‖. 73 .hdl‖ ―nco. Similarly write the constraint file using ―write_sdc > nco. Go to Directory /NCO/rclabs/work. Write the hdl code in terms of library components for the synthesized circuit using the command: ―write_hdl > nco. Invoke the tool using ―encounter‖ or ―velocity‖. 14. Check area using ―report area‖. 15. 12. 11. 13. 16. Timing could be check using ―report timing‖.sdc‖.hdl‖ is the name of file in which the code gets write. 17.

The tool starts as below image: The terminal window and tool window can be seens as similar to images on next page 74 .

75 .

A new window ―Netlist 76 . Select the verilog files using browse button. 19. Go the Tool window and click on the File and select Import Design.18. A new window will open.

.. For maximum timing libraries select all libraries with ―slow‖ in their name and for minimum timing libraries select all libraries with fast in their names.lef‖ in the lef directory.lib‖ in space in front of Maximum Timing Libraries. 20. 77 . 23.v‖ and click the Add button and then click the close button. Similarly select the lef file by clicking the browse button and then add the lef file with name ―all. Similarly in front of Minimum Timing Libraries write ―. Select the timing libraries. Click on the arrow button and select the verilog File ―NCO_gatelevel_uniq.lib‖./lib/*slow*. This will select all the slow libraries. Alternatively. 21. instead of selecting all the libraries for Maximum timing libraries./lib/*fast*. 22. Click on Auto assign after top cell.files‖ will open. type ―.

26.sdc‖ for timing constraint file. Similarly select ―NCO. Select Power out of the list on the left side of window.24. 78 . In the Design Import window click on Advanced Tab. Enter the power nets as VDD and Ground nets as VSS. Select OK. The tool window will look like image on next page. The Design Import window will look like the image on next page: 25.

79 . Click on Floorplan and select ―Specify Floorplan‖.The pink colour blocks are the standard cells. 27. This is floorplan view of the design.

―Core to bottom‖. This is to create the space for Power rings which will be created in power planning. 28. 29. ―Core to top‖. give 30 to each. This will automatically put the Macros if there are any in the design. The core dimensions are changed. 80 . Next step is to do power planning. Click on Floorplan and select Automatic Floorplan and select Plan Design.g.Select the Aspect Ratio as per the requirement. Click Ok. Click OK and the Tool window will be look like as below. e. Click on power. select power planning and click on Add Rings. Give some dimension in ―Core to left‖. ―Core to right‖.

Left and Right as Metal6. The image on the next page is showing the power ring created. Select the top and bottom layer as Metal5. The power ring will get created in between the channel. 81 . Select the option for offset as ―center in channel‖ and click OK.30. Set the width as per the requirement and taking the space between core boundary and I/O pad considerations.

The next step in power planning is to create power strips. select metal layer as Metal 6 and chose direction as vertical(if direction chosen is horizontal. Click OK and the design will get the vertical thin strips of type Metal 6. click Power Planning and click Add Stripe.31. For adding the stripes. 82 . 32. Select Power. chose metal layer as Metal 5).

83 . This is done to provide power to standard cells. 34.33. Click on Special Route option. The horizontal blue coloured metal1 stripes created as a result of Special Route. Click on Route Tab in main menu. Click OK with all default settings.

36. 84 . For placement. click on place and select place and click on Place Standard Cell. Click OK on Place window and in physical view the blue coloured standard cells can be seen as a result of placement of standard cells.35.

37. and select Report Timing. Before CTS. 85 . Click on Timing. In the window select the ―Pre-CTS‖ as Design Stage and select the ―Setup‖ as Analysis Type. timing analysis has to be done for any setup violations. A Timing analysis window will get open.

check for any negative value under WNS(Worst Negative Slack) and TNS(Total Negative Slack). The terminal will look as the image below and Tool window as on next page. In the table displayed on the terminal under ―timeDesign Summary‖. 86 .38. Click OK to complete the Timing analysis. The timing information will get display on terminal in tabular form.

If any part of this design is Zoom-in. 87 . metal layers can be viewed easily.Different colours show different metal layers.The multi-coloured lines visible in the tool window are the connections between standard cells using metal layers.

39. If there is any of the negative slack value under WNS or TNS, click Optimize in Tool window and Select Optimize Design. A new window ―Optimization‖ will get open. Select ―Pre-CTS‖ as Design Stage and ―Setup‖ as optimization type and click OK. The tool will optimize the design and the optimized timing results will be displayed over terminal again.

In this case we did not get any negative slack, so this step is skipped here. 40. Go to Clock, click ―Synthesize Clock Tree‖, a new window ―Synthesize Clock Tree‖ will get open.

88

41. Click on Gen Spec and a new window ―Generate Clock Spec‖ will open.

42. From Cells List, Select all clocks starting with ―CLK‖ and click on Add button to add them to the Selected Cells. Select a name for Output specification.

89

43. Click OK. Then specify a name for Results Directory. and click OK. The tool window looks like the image below.

44. Again Perform the Timing by clicking on Timing and selecting Report Timing. Select ―Post-CTS‖ under Design Stage and do the select ―Set-up‖ as Analysis Type.

90

The timing information will be displayed over the terminal window. Repeat Step 27 for performing timing for ―Post CTS‖ as Design Stage and ―Hold‖ as Analysis Type. 47. 46. 91 . Click Ok to perform the timing. Again check for any negative slacks under WNS or TNS.45. The tool will show the timing results in the terminal window. If there is any negative value found for either of WNS or TNS then perform the Optimization Technique to reduce the negative slack. No negative slack is found in the terminal image on previous page so this step is skipped here. Timing Analysis for ―Setup‖ as Analysis Type is done.

Select ―Post-CTS‖ as and ―HOLD‖ as the Optimization Type 92 .48. After Timing Analysis is performed. Go to Optimize and click on Optimize Design. the timeDesign Summary is showing the negative slack values for both TNS and WNS. Perform the Optimization.

the design has been optimized and tabular results shows that all slack values are now positive values and no more negative values for slack.49. As compare to the Timng Results performed for Hold mode in Step 30. Click OK to perform the Optimization and Tool will perform the optimization and displays the optimized results in the terminal window under timeDesign Summary. 93 . The results of Optimization can be seen on the next page in tabular form for both Setup and Hold mode.

A window NanoRoute will open. 94 . and select NanoRoute and then click Route. Perform Routing by clicking Route. The tool will Perform the Routing and the Routing statistics can be seen on terminal window including DRC violations. Click Ok to Perform Routing.50. 51.

Since there is no negative value of slack so design does not require optimization for Set-up mode in Post-Route stage. 95 . After routing tool window looks like the below image. seelct Report Timing and a Timing Analysis window will get open. 53.52. Perform the timing again. Select ―Post-Route‖ as the Design Stage and ―Setup‖ as Analysis Type. The timing results will be displayed in terminal window for Set up mode. Go to Timing. Click Ok.

the optimization is not require to perform. Click OK. As there is no negative value of slack. Repeat Step 36 for ―Post-Route‖ as Design Stage and ―Hold‖ as the Analysis Type. The final view of the circuit is as below: 96 . The timing results can be seen in the terminal window for hold mode.54.

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