/*

* MSM architecture clock driver
*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2007-2011, Code Aurora Forum. All rights reserved.
* Author: San Mehat <san@android.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include

<linux/version.h>
<linux/kernel.h>
<linux/init.h>
<linux/errno.h>
<linux/string.h>
<linux/delay.h>
<linux/clk.h>
<linux/cpufreq.h>
<linux/mutex.h>
<linux/io.h>
<linux/sort.h>
<linux/remote_spinlock.h>
<mach/board.h>
<mach/msm_iomap.h>
<asm/mach-types.h>
<mach/socinfo.h>

#include "proc_comm.h"
#include "smd_private.h"
#include "acpuclock.h"
#define
#define
#define
#define
#define

A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100)
A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104)
A11S_VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124)
PLLn_MODE(n)
(MSM_CLK_CTL_BASE + 0x300 + 28 * (n))
PLLn_L_VAL(n) (MSM_CLK_CTL_BASE + 0x304 + 28 * (n))

#define PLL4_MODE
#define PLL4_L_VAL

(MSM_CLK_CTL_BASE + 0x374)
(MSM_CLK_CTL_BASE + 0x378)

#define POWER_COLLAPSE_KHZ 19200
/* Max CPU frequency allowed by hardware while in standby waiting for an irq. */
#define MAX_WAIT_FOR_IRQ_KHZ 128000
enum {
ACPU_PLL_TCXO
ACPU_PLL_0
ACPU_PLL_1,
ACPU_PLL_2,
ACPU_PLL_3,
ACPU_PLL_4,

= -1,
= 0,

ACPU_PLL_END,
};
static const struct pll {
void __iomem *mod_reg;
const uint32_t l_val_mask;
} soc_pll[ACPU_PLL_END] = {
[ACPU_PLL_0] = {PLLn_MODE(ACPU_PLL_0),
[ACPU_PLL_1] = {PLLn_MODE(ACPU_PLL_1),
[ACPU_PLL_2] = {PLLn_MODE(ACPU_PLL_2),
[ACPU_PLL_3] = {PLLn_MODE(ACPU_PLL_3),
[ACPU_PLL_4] = {PLL4_MODE, 0x3ff},
};
struct clock_state {
struct clkctl_acpu_speed
struct mutex
uint32_t
unsigned long
struct clk
};
#define PLL_BASE

0x3f},
0x3f},
0x3f},
0x3f},

*current_speed;
lock;
max_speed_delta_khz;
max_axi_khz;
*ebi1_clk;

7

struct shared_pll_control {
uint32_t
version;
struct {
/* Denotes if the PLL is ON. Technically, this can be read
* directly from the PLL registers, but this feild is here,
* so let's use it.
*/
uint32_t
on;
/* One bit for each processor core. The application processor
* is allocated bit position 1. All other bits should be
* considered as votes from other processors.
*/
uint32_t
votes;
} pll[PLL_BASE + ACPU_PLL_END];
};
struct clkctl_acpu_speed {
unsigned int
use_for_scaling;
unsigned int
a11clk_khz;
int
pll;
unsigned int
a11clk_src_sel;
unsigned int
a11clk_src_div;
unsigned int
ahbclk_khz;
unsigned int
ahbclk_div;
int
vdd;
unsigned int
axiclk_khz;
unsigned long lpj; /* loops_per_jiffy */
/* Pointers in acpu_freq_tbl[] for max up/down steppings. */
struct clkctl_acpu_speed *down[ACPU_PLL_END];
struct clkctl_acpu_speed *up[ACPU_PLL_END];
};
static
static
static
static

remote_spinlock_t pll_lock;
struct shared_pll_control *pll_control;
struct clock_state drv_state = { 0 };
struct clkctl_acpu_speed *acpu_freq_tbl;

6. 2. ACPU_PLL_1. { 0. 65536. 61440 }. 0. 1. 1. 0. 384000. 61440 }. 176000. 5. ACPU_PLL_2. 81920. 0}. ACPU_PLL_TCXO. 0. 24576 }. 3. 24576 }. 24576 }. 6. 60000. * * Table stepping up/down entries are calculated during boot to choose the * largest frequency jump that's less than max_speed_delta_khz on each PLL. 1. 196608. {0. 1. 120000 }. 120000 }. 128000. 107000. 88000. 2. 0. 2. 2. 1. 3. { 0. 0. 64000. 0. 1. 3. 0. 7. 0. 0. 3. 0. 2. 0. 3. 61440. 1. 88000. 5. { 1. 49152. 176000. 0. 528000. ACPU_PLL_TCXO. 88000. 19200. 3. ACPU_PLL_0. { 1. {0. 2. 30720 }. 120000. 0. 88000. 24576 }. 0. { 1. ACPU_PLL_1. 1. #endif /* * ACPU freq tables used for different PLLs frequency combinations. 0. 3. 64000. 0}. 0. 98304. 0. 0. { 1. 1. 0. 528000. ACPU_PLL_1. { 0. 120000. 61440 }. 0. { 1. 4. 120000 }. 3. { 1. 128000. 24576 }. 1. 98304. 0. 0. 19200. ACPU_PLL_2. 3. 3. 0. { 1. 256000. 0. 128000 }. { 1. 0} } }. { 0. 122880. ACPU_PLL_0. 60000. 4. 120000. 128000 }. 5. 0} } }. 2. ACPU_PLL_0. 2. 5. The * correct table is selected during init. 19200. {0. 1. 3. { 0. 5. 1. 352000. 1. 122880. 1. 3. ACPU_PLL_2. 128000. 4. 0. 128000 }. 3. 2. /* 7x01/7x25 normal with CDMA-only modem */ static struct clkctl_acpu_speed pll0_196_pll1_768_pll2_1056_pll4_0[] = { { 0. 0. 1. 2. 24576 }.#ifdef CONFIG_MACH_PRIMODD unsigned int vdd_pa=10. { 1. 1. 0. 0}. 7. 4. 2. 1. 1. 88000. 0. 1. 0. 61440 }. 0. 5. 81920. 6. 19200. 2. 30720 }. 0. 61440 }. 128000 }. 7. 0. 1. 0. 2. 3. 0. 196608. ACPU_PLL_2. 2. 0. 5. 61440 }. 3. ACPU_PLL_TCXO. 19200. 0. { 0. ACPU_PLL_1. 0. 128000. {0. 19200. 0. 0. ACPU_PLL_1. 61440 }. { 0. 4. ACPU_PLL_0. 88000. ACPU_PLL_0. 0. { 0. { 0. { 0. 4. { 1. 1. 128000 }. 176000. ACPU_PLL_1. 1. 1. 49152. ACPU_PLL_2. 5. 0. 3. 24576 }. 128000. ACPU_PLL_1. 0. 5. 132000. 1. 0. 0. 1. 0. 528000. 1. 1. 2. 0. { 1. ACPU_PLL_2. 24576 }. 65536. ACPU_PLL_TCXO. 0. 4. ACPU_PLL_0. 7. { 1. { 1. { 0. 3. 2. { 1. 2. 1. . {0. ACPU_PLL_0. 122880 }. 0. /* 7x01/7x25 turbo with CDMA-only modem */ static struct clkctl_acpu_speed pll0_196_pll1_960_pll2_1056_pll4_0[] = { { 0. 1. 2. ACPU_PLL_1. 5. ACPU_PLL_1. 19200. 132000. 2. 24576 }. 0. 245760. 1. 0. */ /* 7x01/7x25 normal with GSM capable modem */ static struct clkctl_acpu_speed pll0_245_pll1_768_pll2_1056_pll4_0[] = { { 0. ACPU_PLL_1. { 1. 128000. { 0. 4. 4. 3. 7. 256000. 128000 }. 4. 61440 }. 19200. 1. 352000. 132000. 2. 245760. 0. ACPU_PLL_2. 2. 5. 0. 176000. 128000 }. {0. ACPU_PLL_0. 352000. 0} } }. 4. 5. /* 7x01/7x25 turbo with GSM capable modem */ static struct clkctl_acpu_speed pll0_245_pll1_960_pll2_1056_pll4_0[] = { { 0. 61440. 0. ACPU_PLL_2. { 1. 2. ACPU_PLL_2. 3. 88000. 1. 4. 384000. 128000 }. { 0. 320000. 0. { 1. 0. 0. 0. 0. 24576 }. 2. 1. { 0. 1. 0. ACPU_PLL_2. 480000.

122880 }. 98304. 5. 2. { 0. ACPU_PLL_2. {0. 120000 }. 7. 0. 200000. 122880. { 0. 122880 }. 1. 1. 600000. 0. 24576 }. { 0. 1. 200000. 0. 2. 1. ACPU_PLL_0. ACPU_PLL_1. 196608. ACPU_PLL_0. 0. 0. 400000. 0. 0. 5. ACPU_PLL_2. 0. ACPU_PLL_0. { 0. 0. { 1. ACPU_PLL_2. 98304 }. ACPU_PLL_TCXO. 5. ACPU_PLL_2. 480000. ACPU_PLL_2. ACPU_PLL_0. 0. 4. 2. 4. /* 7x27 normal with GSM capable modem . ACPU_PLL_2. 1. 3. 120000 }. 5. ACPU_PLL_0. 2. { 1. { 1. 1. 0. { 0. 4. 528000. 132000. 122880 }. 0. 0. 3. 320000. ACPU_PLL_1. 61440. 2. 120000 }. 120000 }. 0. 196608. { 0. 61440 }. ACPU_PLL_TCXO. 2. 0. 4. 133333. 0. 1. 0. 1. 60000. 1. { 1. 0. 0. 1. 1. 7. { 1. 2. 3. 5. ACPU_PLL_1. 2. 133333. 2. /* 7x27 normal with CDMA-only modem */ static struct clkctl_acpu_speed pll0_196_pll1_960_pll2_1200_pll4_0[] = { { 0. 120000 }. 1. {0. 120000. { 1. 133333. 4. 7. 120000 }. 61440 }. 0. 0. 600000. 60000. 0}. ACPU_PLL_1. ACPU_PLL_1. 30720 }. 0.PLL0 and PLL1 swapped */ static struct clkctl_acpu_speed pll0_960_pll1_196_pll2_1200_pll4_0[] = { { 0. 1. 0. ACPU_PLL_1. /* 7x27 normal with CDMA-only modem . { 0. 3. ACPU_PLL_2. 0. 0. ACPU_PLL_TCXO. 245760. 19200. { 1. 98304 }. 49152 }. 160000. 320000. ACPU_PLL_0. 65536. 320000. 122880 }. 160000. 2. 0. ACPU_PLL_TCXO. 120000 }. 2. 98304 }.{ { { { { 1. 122880 }. ACPU_PLL_1. 1. 4. 0} } }. 2. 3. 7. 0. 600000. 133333. 0. 5. 1. 66667. 0. 3. { 1. ACPU_PLL_1. 0. 0. 0. 7. 1. /* 7x27 normal with GSM capable modem */ static struct clkctl_acpu_speed pll0_245_pll1_960_pll2_1200_pll4_0[] = { { 0. 1. 200000. 1. 6. 0. 120000. 1. 61440 }. 19200. 5. 19200. 1. 0. { 1. 2. 98304. 0. 480000. 2. 0. 122880 }. 0. 61440 }. 4. 200000. 1. 2. 0. 0. 98304. 2. 1. 0. 120000 }. ACPU_PLL_2. 49152 }. 0. 3. 0. 3. 122880 }. 4. 61440 }. 0. 2. 1. 1. 4. 2. {0. 0. { 1. 2. 120000 }. 1. 4. 6. ACPU_PLL_1. 0} } }. 60000. 320000. 320000. 1. 66667. 61440. 0. 122880. 4. 0. 1. 122880. 2. ACPU_PLL_0. 2. 0. {0. 1. 2. 160000. 0. 160000. 0. 400000. 19200. 98304 }. 0. 6. { 0. 2. 0. 0. 0}. 0. 5. 5. 352000. 6. 160000. ACPU_PLL_2. ACPU_PLL_2. ACPU_PLL_2. 3. 480000. { 1. 19200. 0. ACPU_PLL_2. 160000. 480000. { 0. 2. 5. 2. ACPU_PLL_0. 0. { 0. 0. 0. 6.PLL0 and PLL1 swapped */ static struct clkctl_acpu_speed pll0_960_pll1_245_pll2_1200_pll4_0[] = { { 0. 2. 4. { 0. ACPU_PLL_1. 60000. ACPU_PLL_1. 1. { 0. 200000. 0. 3. 2. 0. 7. 160000. 2. 19200. 0. { 1. 0}. ACPU_PLL_1. { 1. 160000. 4. 1. {0. 122880 }. 49152 }. { 0. 120000. { 1. 0. 120000. 0. 0. 2. 0. 1. ACPU_PLL_2. 49152 }. 66667. {0. ACPU_PLL_0. 2. 1. 2. 2. 2. 5. 2. 0. { 1. 19200. 7. { 1. 2. 0. 2. 200000. 400000. 120000 }. 4. 122880. 0. 0. 88000. 0. 2. 5. 2. 1. 0. 61440 }. 4. 5. 1. 0} } }. 400000. 0} } }. 4. 120000 }. 2. 120000. 4. 1. 19200. 4. 24576 }. { 1. 1. 0. 480000. {0. ACPU_PLL_2. 2. 0. 245760. 0}. { 0. { 1. 0. 0. {0. { 0. 3. 120000 }. 61440 }. 200000. 7. 61440 }. 5. . 0. { 1. 1. 2. 2. 66667. 98304. 600000. 65536. { 1. 1. 107000. 1. 2. 7. 0. 200000. 30720 }. ACPU_PLL_0. 1.

19200. 480000. 0. 3. 0}. 0. 0. 245760. 3. 61440. 0. /* 7x27a pll2 at 1200mhz with CDMA only modem */ static struct clkctl_acpu_speed pll0_960_pll1_196_pll2_1200_pll4_800[] = { { 0. 0. 7. 0. 3. 3. 30720 }. 2400. 0. /* 7x27 normal with CDMA-only modem . 1. 3. 3. ACPU_PLL_1. 3. 2. { 0. ACPU_PLL_2. ACPU_PLL_2. 4. 0. 2. ACPU_PLL_2. 0. 2. ACPU_PLL_4. 3. 320000. ACPU_PLL_0. 1. {0. 6. 1. 4. 2. 0. 0. 3. 0} } }. 200000 }. 400000. { 1. 800000. ACPU_PLL_2. { 0. 1. 0. 0}. 50000. { 0. 200000 }. 0. 2. 2. 60000. ACPU_PLL_1. { 1. 0. 600000. 30720. { 1. 4. 0. 400000. { 1. 3. 120000. 800000. 2. 19200. 3. 120000 }. 1. 150000 }. 2. {0. 0. 0} } }. 0. 0. 200000. 0. 19200. 98304. 61440 }.PLL0 and PLL1 swapped and pll2 @ 800 */ static struct clkctl_acpu_speed pll0_960_pll1_245_pll2_800_pll4_0[] = { { 0. 1. 122880 }. 3. ACPU_PLL_2. 0. { 1. 4. {0. 120000 }. 120000 }. {0. 0. 800000. ACPU_PLL_1. 0}. 0. 0. 3. 7. 600000. 480000. 1. 61440 }. 4. ACPU_PLL_4. 1. { 1. 66667. 3. 3. ACPU_PLL_1. {0. 120000 }. 0. { 0. 480000. 1. 1. 0. 7. 19200. /* 7x27 normal with GSM capable modem . 320000. 1. 12288. 4. 2. { 0. 200000 }. 1. 5. 3. 320000. 5. 2. 120000 }. 196608. ACPU_PLL_4. 0. 37500. 100000. 2. ACPU_PLL_2. ACPU_PLL_4. 60000. { 1. 65536. ACPU_PLL_2. 49152 }. 0. 0. 0} } }. 0. 4. 1. 0. 300000. 200000. 0. 2. 0. 0. 4. 0. 4. 0}. {0. { 0. 6. 4. 0. 0. 0. 1. 1. 0. { 1. 800000. 0. 3. ACPU_PLL_0. 3. 0. ACPU_PLL_2. 30720 }. 2. 1. 0. 0} } }. { 1. 200000 }. 4. ACPU_PLL_TCXO. 0. 0. 122880 }. 19200. 3. { 1. 7680. 1. 0. 4. 2. 3. 50000. { 1. 24576. { 0. 37500. 2. 3. 98304 }. ACPU_PLL_1. 0. 480000. 98304. 300000. 0. 0. { 0. 0. 100000. 3. 75000. 0. 3. { 0. { 1. 61440 }. 49152 }. 0. 320000. 61440 }. ACPU_PLL_1. 0. { 0. 0. ACPU_PLL_2. 4. 400000. ACPU_PLL_1. { 0. 15360. 0. ACPU_PLL_0. 0. 3. 0. {0. 122880. 0. { 1. { 1. { 0. 4. 1. 49152 }. 60000. 122880. 98304. 2. 2. /* 7x27a pll2 at 1200mhz with GSM capable modem */ static struct clkctl_acpu_speed pll0_960_pll1_245_pll2_1200_pll4_800[] = { { 0. 122880 }. 19200. { 1. {0. 0. 61440. { 1. ACPU_PLL_0. 0. 3. ACPU_PLL_0. ACPU_PLL_0. 1. 122880 }. { 1. 122880 }. 0. 3. 6. 120000 }. { 1. 0. 5. 160000. 120000 }. 1. 120000. 61440 }. 0}. 200000. 0. 0. 245760. 1. 1. 0. 3. 0. 0. 3. 3. 160000. 24576 }. 0. 4. 5. 0. 0. 0. 122880 }. 2400. 61440 }. 2. 6. 6. 0. 0. 160000. { 1. 66667. 0. 120000 }. 133333. 2. 0. 1. {0. 98304 }. ACPU_PLL_0. 0. ACPU_PLL_0. ACPU_PLL_1. { 1. 1. 0. 2. 6. 4. 2. 1. 4. 5. ACPU_PLL_0. 4. 65536. 6. ACPU_PLL_TCXO. { 0. 3. 1. 1. 98304 }. 1. . 1. 7. { 1. 3.{ 0. ACPU_PLL_TCXO. 49152 }. 0. 160000. 8192. 0. 75000. 61440 }. 0. 0. 2. {0.PLL0 and PLL1 swapped and pll2 @ 800 */ static struct clkctl_acpu_speed pll0_960_pll1_196_pll2_800_pll4_0[] = { { 0. ACPU_PLL_2. 7. 0. 196608. 0. ACPU_PLL_1. 40000. 0. 0. { 0. { 1. 133333. 3. 0. 6. 0. 2. ACPU_PLL_TCXO. 40000. 122880. ACPU_PLL_0. 400000. ACPU_PLL_1. 3. 0. 200000. 0. 7. 3. 0. 1. 4. 4. 1. 24576 }. 122880 }. 0} } }. 5. 60000. 1. { 0. { 0.

63000. ACPU_PLL_0. 30720 }. 49152 }. { 1. 200000 }. ACPU_PLL_1. ACPU_PLL_4. 37500. 2. 0. 0. ACPU_PLL_1. 30720. 3. 24576. 480000. 2400. 3. ACPU_PLL_0. 0. 98304. 3. 98304 }. 1. . ACPU_PLL_0. 37500. ACPU_PLL_1. ACPU_PLL_2. 480000. ACPU_PLL_1. 12288. { 0. { 0. 300000. ACPU_PLL_2. 8192. 150000 }. 200000 }. 200000}. /* 7x25a pll2 at 1200mhz with GSM capable modem */ static struct clkctl_acpu_speed pll0_960_pll1_245_pll2_1200_pll4_800_25a[] = { { 0. { 1. 37500. 63000. { 1. 3. 3. 98304. 200000 }. 4. 160000 }. 3. 4. 24567 }. 3. 6. 0. 2. 0. 1008000. 2. 1. 2400. 40000. { 1. 4. 504000. { 0. 3. 24576. ACPU_PLL_2. 200000}. 6. 1. 63000. 49152 }. 2. 3. 40000. 504000. 75000. 61440 }. { 1. 6. 0. { 1. 0. { 1. ACPU_PLL_0. 6. 0. 3. 49152 }. 4. 1. 2400. 3. ACPU_PLL_1. ACPU_PLL_0. 1. 0} } }. 1008000. 126000. 126000. 200000}. 1. 2. 150000 }. ACPU_PLL_4. 2. {0. { 1. 504000. 1. ACPU_PLL_TCXO. 61440 }. 37500. 0. 3. 320000. 6. { 0. 1. 19200. 1. 480000. 3. ACPU_PLL_1. 6. 3. 4. 1. 0. { 1. { 1. { 1. ACPU_PLL_0. 0. 3. 3. 7680. 6. 3. ACPU_PLL_4. 2. 1. 320000. 1. 300000. 200000 }. 5. 6. 126000. 2. 75000. 65536. 6. 4. 0. 0}. { 1. 0. #else { 0. 3. 2. 75000. 6. 0. 2. 300000. 122880 }. 3. 6. 40000. { 0. { 1. 3. 245760. 60000. 61440 }. 200000 }. 504000. { 0. 1. 3. 4. 5. ACPU_PLL_2. 3. 2400. 160000 }. #else { 0. 3. { 1. ACPU_PLL_4. 3. 4. 0. 3. #endif { 0. 0. 3. 3. 0. { 0. 1. ACPU_PLL_2. 126000. ACPU_PLL_1. 2. 3. 6. 0. { 1. 0. 3. 8192. 3. 3. 49152 }. 196608. ACPU_PLL_1. 30720 }. 122880 }. ACPU_PLL_4. 0. 12288. {0. 2400. 3. 6. 0. 2. 0. 320000. 200000 }. 60000. { 1. 0. 4. 3. 3. 1. 0. 61440. 15360. 0. 7680. /* 7x27aa pll4 at 1008mhz with CDMA capable modem */ static struct clkctl_acpu_speed pll0_960_pll1_196_pll2_1200_pll4_1008[] = { #ifdef CONFIG_MACH_PRIMODD { 0. 3. {0. 0. 1. 3. 3. 3. { 0. { 0. 1. 1. 2. #endif { 0. 1. 98304 }. 4. 122880 }. 0. 0. 3. 4. 1. 0}. 1. 1. 3. 19200. { 1. { 1. 7. { 1. 2. 3. 300000. 2. 0. 61440. ACPU_PLL_0. 1. 122880 }. 1. 600000. 1. 0. 40000. { 0. ACPU_PLL_TCXO. 600000. ACPU_PLL_TCXO. 0. 3. { 0. 61440 }. 0. {0. ACPU_PLL_4. 1. 0. 0. 19200. 3. 7. 0. 30720 }. 2. 3. 5. 3. 4. 480000. 0. 0. 0. 60000. ACPU_PLL_TCXO. 160000 }. 3. 122880./* 7x27aa pll4 at 1008mhz with GSM capable modem */ static struct clkctl_acpu_speed pll0_960_pll1_245_pll2_1200_pll4_1008[] = { #ifdef CONFIG_MACH_PRIMODD { 0. ACPU_PLL_2. 4. 4. 1. 3. { 1. 122880. 0. 4. ACPU_PLL_4. 24576 }. 0. 3. 196608. 320000. 7. ACPU_PLL_1. 30720. 3. 75000. { 1. 200000}. 245760. 0. 0. 1. 1. 19200. 3. 61440 }. ACPU_PLL_1. 60000. 1008000. 65536. 1. 6. 150000 }. 3. { 1. 0. 0. { 1. 0} } }. 0. ACPU_PLL_TCXO. 3. 1. 0. { 0. 63000. 122880 }. 2. 1. 7. 0. ACPU_PLL_2. 15360. ACPU_PLL_1. 600000. 1008000. 150000 }. ACPU_PLL_4. ACPU_PLL_0. 200000 }. { 1. 6. 5. ACPU_PLL_2. 4. 0. 160000 }. 19200. 600000. 6. 200000 }. 0. ACPU_PLL_1.

19200. 0. 2400. 3. 7. 480000. 1. 40000. 0. 40000. { 0. 6. 1. 0. 0. 61440 }. { 1. 3. 0} } }. 5. 2. 0. ACPU_PLL_2. 3. 30720. 0. { 0. 200000}. 0. 0. { 0. 320000. ACPU_PLL_1. 60000. 3. {0. 150000 }. 1. 120000 }. 0. 61440 }. 0. 98304. 4. 0. ACPU_PLL_1. 1. 120000 }. 0}. ACPU_PLL_4. 0. 1. 3. 100000. 3. { 0. 4. 1. { 0. 200000 }. 0. 0. 2. 3. 3. { 1. 0. 1. 6. ACPU_PLL_4. 19200. 3. 4. 0. 120000 }. 245760. 400000. 480000. 0. 122880 }. 600000. 37500. 0. 4. 0} } }. 0. 0. 1. 1. { 1. 3. ACPU_PLL_2. 1008000. 40000. 4. 1. ACPU_PLL_1. 0. { 1. 3. 245760. { 1. 7. 480000. 122880 }. 0. 98304 }. 0. 3. 6. 0. 0. 2. ACPU_PLL_0. 0. 196608. 0. 0. 4. 6. 6. { 1. 245760. {0. 60000. 600000. 4. 50000. 1. { 0. 122880. 2. 800000. ACPU_PLL_1. 0. 75000. 1. 0. 2400. 3. 7680. 3. 1. 6. 400000. 61440 }. 200000 }. 0. 65536. 3. 6. ACPU_PLL_1. 75000. 2400. ACPU_PLL_1. 800000. 0. 3. 3. 2. 63000. 4. 19200. /* 7x27aa pll4 at 1008mhz with CDMA capable modem */ static struct clkctl_acpu_speed pll0_960_pll1_589_pll2_1200_pll4_1008[] = { #ifdef CONFIG_MACH_PRIMODD { 1. { 1. 0. ACPU_PLL_4. 0. 61440. 7680. 61440 }. ACPU_PLL_0. 61440. 200000 }. { 1. 3. 3. { 1. 1. 3. 4. 1. 6. /* 7x27a pll2 at 1200mhz with CDMA only modem */ static struct clkctl_acpu_speed pll0_960_pll1_589_pll2_1200_pll4_800[] = { { 0. 3. 37500. 4. ACPU_PLL_2. ACPU_PLL_0. ACPU_PLL_4. 3. 0. 300000. 4. 3. 3. 75000. ACPU_PLL_1. 60000. 0. { 1. ACPU_PLL_0. ACPU_PLL_TCXO. 1. 480000. 3. 49152 }. 0. 3. ACPU_PLL_4. 3. 600000. 300000. ACPU_PLL_4. 320000. 15360. 3. 200000 }. 1. 5. 0. 49152 }. 2. 2.{ { { { { { { { { 0. 6. {0. 5. 0. 1. 3. 320000. 50000. 4. 30720 }. 3. 1. 30720. { 0. 122880 }. 30720 }. ACPU_PLL_0. 122880. 50000. 3. 3. 61440. 0. 122880 }. 3. ACPU_PLL_2. 0. { 0. 30720 }. ACPU_PLL_2. 61440 }. 3. 122880. 24576 }. . { 1. 320000. 1. 0. 61440 }. 5. 0. ACPU_PLL_TCXO. 0. 150000 }. 1. 60000. 0. 2. 150000 }. 6. 11. 0} } }. 3. 0. { 0. 1. 5. 15360. 0. 30720. 400000. /* 7x27aa pll4 at 1008mhz with GSM capable modem */ static struct clkctl_acpu_speed pll0_960_pll1_737_pll2_1200_pll4_1008[] = { { 0. 0. 4. 1. 600000. 2. 504000. 2. 2. 19200. 40000. 0. 1. { 1. 122880 }. 2. {0. 0}. 0. 1. 0. ACPU_PLL_0. 0. 122880 }. 0. 37500. 37500. { 1. 2. 8192. 0. 200000 }. 200000 }. ACPU_PLL_0. 3. 2. 3. 1. 1. 3. 1. { 0. /* 7x27a pll2 at 1200mhz with GSM capable modem */ static struct clkctl_acpu_speed pll0_960_pll1_737_pll2_1200_pll4_800[] = { { 0. ACPU_PLL_1. 100000. 8. { 1. {0. 2. 0} } }. 2. {0. 4. 0}. 1. 126000. 0. {0. 3. 7680. 122880 }. 0. 0. 1. 1. 11. 0. 3. 5. 300000. 61440 }. 3. { 1. 75000. 0. 2. 3. 200000 }. 4. 0. 0. 122880 }. 120000 }. { 1. 4. ACPU_PLL_1. 0. 0. { 1. 2400. 0. 0. 0. 1. 2. { 1. ACPU_PLL_1. 12288. 1. 4. ACPU_PLL_2. 0. 4. 61440 }. ACPU_PLL_TCXO. 5. 300000. 0. 0. ACPU_PLL_1. 6. 4. 0. { 0. ACPU_PLL_0. { 0. 3. 3. 1. 6. ACPU_PLL_2. 3. 3. ACPU_PLL_2. 3. 61440 }. 3. 7. 0}. 0. 15360. ACPU_PLL_1. {0. 2. ACPU_PLL_4. ACPU_PLL_TCXO. 24576.

3. { 1. 49152 }. 0. 1. 19200. { 0. 1. 61440 }. 0. 2. /* 7x25a pll2 at 1200mhz with GSM capable modem */ static struct clkctl_acpu_speed pll0_960_pll1_737_pll2_1200_pll4_800_25a[] = { { 0. ACPU_PLL_1. #define #define #define #define #define #define #define #define #define #define #define #define PLL_0_MHZ PLL_196_MHZ PLL_245_MHZ PLL_491_MHZ PLL_589_MHZ PLL_737_MHZ PLL_768_MHZ PLL_800_MHZ PLL_960_MHZ PLL_1008_MHZ PLL_1056_MHZ PLL_1200_MHZ 0 10 12 25 30 38 40 41 50 52 55 62 #define PLL_CONFIG(m0. { 1. 0. 0} } }. 60000. 0. 3. 320000. 3. 320000. 3. ACPU_PLL_2. 1. pll2_l. 0. 98304. 2. ACPU_PLL_4. ACPU_PLL_1. 6. 1. 0. { 0. 3. ACPU_PLL_1. PLL_##m1##_MHZ. 50000. 4. 75000. { 1. #else #endif { 0. 3. 0. 3. 1. 504000. 150000 }. ACPU_PLL_4. 7. PLL_##m2##_MHZ. 3. 63000. 65536. 63000. 30720 }. ACPU_PLL_2. 0. 0. 98304 }. ACPU_PLL_2. 0. 7680. 6. PLL_##m4##_MHZ. 3. 40000. 200000}. 0. 37500. 11. 2. 2. 1. 160000 }. 600000. 0. 480000. 2. 126000. 0. 245760. 8. 1. 122880 }. 1. 2. m2. 1. 504000. 3. 5. 3. 0. 0. 0. 126000. 75000. 3. 1. 0. 0. m4) { \ PLL_##m0##_MHZ. 4. 0. 2. 1. 0}. 4. 5. 75000. 61440 }. 24576. ACPU_PLL_1. 3. 1. 0. 2. 0. 3. 0. ACPU_PLL_1. 0. 1. 3. 245760. 1. 196608. 2. 6. ACPU_PLL_2. 0. 6. 7. 3. 1. 200000}. 61440. 1. 2400. 160000 }. 1. 4. ACPU_PLL_0. { { { { { { { { { { 0. 3. 4.{ { { { { { { { 1. ACPU_PLL_4. 15360. 320000. 30720. 3. . 3. 98304 }. 60000. 1008000. 0. ACPU_PLL_TCXO. 6. 3. 3. 4. \ pll0_##m0##_pll1_##m1##_pll2_##m2##_pll4_##m4 \ } struct pll_freq_tbl_map unsigned int unsigned int unsigned int unsigned int { pll0_l. 1. 15360. 3. ACPU_PLL_2. 122880 }. 4. ACPU_PLL_1. pll4_l. 19200. 0. 40000. 1. 122880 }. 7680. 1. 2400. 1. 4. 49152 }. 1. ACPU_PLL_1. 1. 8192. 0. 1. 0. 122880. 2. 1. {0. 37500. 3. {0. 0. 61440 }. 1. 61440. 3. { 1. 400000. {0. 61440 }. ACPU_PLL_0. 3. ACPU_PLL_TCXO. 600000. m1. 0. 480000. 300000. 0. ACPU_PLL_1. 1. 4. 6. 200000 }. 3. ACPU_PLL_0. 2. 0. 122880. {0. ACPU_PLL_0. 1. 3. 1. ACPU_PLL_4. 0. ACPU_PLL_0. { 0. 2. 0} } }. 4. 122880 }. 0. 6. 1. 6. pll1_l. 1. 1. 24576 }. { 0. 0. 1. 150000 }. { 1. 40000. 1008000. 6. 3. 6. 60000. 1. 3. 61440 }. 5. 600000. 200000 }. ACPU_PLL_4. 4. 200000 }. ACPU_PLL_1. 0. 3. 200000 }. 12288. 0}. 0. 300000. 200000 }. 5. 2. 3. 5. 122880 }. 4. ACPU_PLL_0. 480000. 3. 0. 1. 30720. 3.

0 } }. 0). PLL_CONFIG(196. */ for (i = 0. PLL_CONFIG(960.index = freq_cnt. 0). PLL_CONFIG(960. 1056. 800). 1200. 0). 0). 196. unsigned int freq_cnt = 0. 0. PLL_CONFIG(960. #ifdef CONFIG_CPU_FREQ_MSM static struct cpufreq_frequency_table freq_table[20]. 1056. unsigned on) { if (on) { . } #endif static void pll_enable(void __iomem *addr. PLL_CONFIG(960. 245. PLL_CONFIG(245.a11clk_khz != 0 && freq_cnt < ARRAY_SIZE(freq_table)-1. PLL_CONFIG(960. 1200. 960. PLL_CONFIG(960. 1008). PLL_CONFIG(960. 1008). acpu_freq_tbl[i]. 800. }. freq_cnt++. 960. 1200. PLL_CONFIG(960. 1200. freq_table[freq_cnt]. 737. 737.index = freq_cnt. PLL_CONFIG(196. 1008). 960. { 0. PLL_CONFIG(960. 1056. 1008). 196. 1200. 196. PLL_CONFIG(960. 800. PLL_CONFIG(960. 0). 1200.struct clkctl_acpu_speed *tbl.frequency = CPUFREQ_TABLE_END. 1200. PLL_CONFIG(245. 0). 1200. freq_cnt). 245. 800). 768. pr_info("%d scaling frequencies supported. 0). static struct pll_freq_tbl_map acpu_freq_tbl_list[] = { PLL_CONFIG(196. 245. } } /* freq_table not big enough to store all usable freqs. 0. 589. 800). i++) { if (acpu_freq_tbl[i]. 1200.use_for_scaling) { freq_table[freq_cnt]. 1056. 1200. 245. /* Construct the freq_table table from acpu_freq_tbl since the * freq_table values need to match frequencies specified in * acpu_freq_tbl and acpu_freq_tbl needs to be fixed up during init. 960. 1200. 0).\n". 0.a11clk_khz. PLL_CONFIG(245. static void __init cpufreq_table_init(void) { unsigned int i. freq_table[freq_cnt]. 196. freq_table[freq_cnt].frequency = acpu_freq_tbl[i]. 0). 0).a11clk_khz != 0). 768. 1200. PLL_CONFIG(960. */ BUG_ON(acpu_freq_tbl[i]. 800). 589.

writel_relaxed(7. id). unsigned long flags. } else { writel_relaxed(0. 1). pll_control->pll[PLL_BASE + id]. udelay(5).on) { pll_enable(soc_pll[id]. else pr_debug("PLL disabled\n"). writel_relaxed(6. } } static int pc_pll_request(unsigned id. &id. addr).mod_reg. 0).mod_reg. if (on) { pll_control->pll[PLL_BASE + id]. flags). mb().votes &= ~2. return res. if (res < 0) return res. if (!pll_control->pll[PLL_BASE + id].on = 0. pll_control->pll[PLL_BASE + id]. flags). } if (on) pr_debug("PLL enabled\n"). id). if (id >= ACPU_PLL_END) return -EINVAL.on && !pll_control->pll[PLL_BASE + id]. if (pll_control->pll[PLL_BASE + id]. } } else { pll_control->pll[PLL_BASE + id]. addr). on = !!on. if (pll_control) { remote_spin_lock_irqsave(&pll_lock. unsigned on) { int res = 0. mb().writel_relaxed(2. &on). addr).on = 1. else pr_debug("Disabling PLL %d\n". } } wmb().votes) { pll_enable(soc_pll[id]. } . addr). if (on) pr_debug("Enabling PLL %d\n". else if ((int) id < 0) return -EINVAL. udelay(50). remote_spin_unlock_irqrestore(&pll_lock. } else { res = msm_proc_comm(PCOM_CLKCTL_RPC_PLL_REQUEST.votes |= 2.

mb(). reg_clksel. writel_relaxed(reg_clksel. udelay(62). vdd). } pr_debug("VDD switched\n"). */ if ((cpu_is_msm7x27a() || cpu_is_msm7x25a()) && (SOCINFO_VERSION_MINOR(socinfo_get_version()) < 1)) return 0. A11S_CLK_SEL_ADDR). /* * If the new clock divider is higher than the previous. current_vdd = readl_relaxed(A11S_VDD_SVS_PLEVEL_ADDR) & 0x07. } /* Program clock source and divider */ reg_clkctl = readl_relaxed(A11S_CLK_CNTL_ADDR). return -EIO. reg_clksel |= (hunt_s->ahbclk_div << 1). then * program the divider before switching the clock */ if (hunt_s->ahbclk_div > clk_div) { reg_clksel &= ~(0x3 << 1)./*---------------------------------------------------------------------------* ARM11 'owned' clock control *---------------------------------------------------------------------------*/ static int acpuclk_set_vdd_level(int vdd) { uint32_t current_vdd. /* AHB_CLK_DIV */ clk_div = (reg_clksel >> 1) & 0x03. */ static void acpuclk_set_div(const struct clkctl_acpu_speed *hunt_s) { uint32_t reg_clkctl. /* CLK_SEL_SRC1NO */ src_sel = reg_clksel & 1. A11S_VDD_SVS_PLEVEL_ADDR). reg_clkctl &= ~(0xFF << (8 * src_sel)). clk_div. return 0. /* * NOTE: v1. writel_relaxed((1 << 7) | (vdd << 3). current_vdd. pr_debug("Switching VDD from %u mV -> %d mV\n". reg_clksel = readl_relaxed(A11S_CLK_SEL_ADDR). src_sel. . } /* Set proper dividers for the given clock speed. if ((readl_relaxed(A11S_VDD_SVS_PLEVEL_ADDR) & 0x7) != vdd) { pr_err("VDD set failed\n").0 of 7x27a/7x25a chip doesn't have working * VDD switching support.

reg_clksel |= (hunt_s->ahbclk_div << 1). strt_s = cur_s = drv_state. tgt_s->a11clk_khz != 0. writel_relaxed(reg_clksel. writel_relaxed(reg_clkctl. /* Program clock source selection */ reg_clksel ^= 1. A11S_CLK_CNTL_ADDR). A11S_CLK_SEL_ADDR). reg_clkctl |= hunt_s->a11clk_src_div << (0 + 8 * src_sel). pll. int res. */ if (reason != SETRATE_CPUFREQ && tgt_s->a11clk_khz < cur_s->a11clk_khz) { while (tgt_s->pll != ACPU_PLL_TCXO && tgt_s->pll != cur_s->pll) tgt_s--. A11S_CLK_SEL_ADDR). then * program the divider after switching the clock */ if (hunt_s->ahbclk_div < clk_div) { reg_clksel &= ~(0x3 << 1). WARN_ONCE(cur_s == NULL. goto out. } if (strt_s->pll != ACPU_PLL_TCXO) plls_enabled |= 1 << strt_s->pll. goto out. writel_relaxed(reg_clksel. } } static int acpuclk_7201_set_rate(int cpu. enum setrate_reason reason) { uint32_t reg_clkctl. } if (rate == cur_s->a11clk_khz) goto out. unsigned long rate. if (reason == SETRATE_CPUFREQ) mutex_lock(&drv_state. *tgt_s. } /* Choose the highest speed at or below 'rate' with same PLL. if (cur_s == NULL) { rc = -ENOENT. . "%s: not initialized\n". for (tgt_s = acpu_freq_tbl. *strt_s.reg_clkctl |= hunt_s->a11clk_src_sel << (4 + 8 * src_sel). /* * If the new clock divider is lower than the previous. struct clkctl_acpu_speed *cur_s. tgt_s++) { if (tgt_s->a11clk_khz == rate) break. rc = 0. __func__).lock).current_speed. } if (tgt_s->a11clk_khz == 0) { rc = -EINVAL. unsigned int plls_enabled = 0.

use the predefinied * steppings in the table. */ int d = abs((int)(cur_s->a11clk_khz . goto out.tgt_s->a11clk_khz)). */ if (tgt_s->vdd > cur_s->vdd) { #ifdef CONFIG_MACH_PRIMODD if(10!=vdd_pa) rc = acpuclk_set_vdd_level(vdd_pa). */ . If differnece is greater. if (rc < 0) { pr_err("Unable to switch ACPU vdd (%d)\n". if (rc < 0) { pr_err("PLL%d enable failed (%d)\n". } } /* Need to do this when coming out of power collapse since some modem * firmwares reset the VDD when the application processor enters power * collapse. rc). 1).if (reason == SETRATE_CPUFREQ) { if (strt_s->pll != tgt_s->pll && tgt_s->pll != ACPU_PLL_TCXO) { rc = pc_pll_request(tgt_s->pll. regulardless of * PLL. else #endif rc = acpuclk_set_vdd_level(tgt_s->vdd). } else { /* Step down: stay on current PLL as long as * possible so indexing using TCXO (down[-1]) * never occurs. tgt_s->pll. goto out. tgt_s->a11clk_khz). */ if (likely(cur_s->up[tgt_s->pll])) cur_s = cur_s->up[tgt_s->pll]. strt_s->a11clk_khz. rc). } plls_enabled |= 1 << tgt_s->pll. } } } /* Set wait states for CPU inbetween frequency changes */ reg_clkctl = readl_relaxed(A11S_CLK_CNTL_ADDR). else cur_s = cur_s->up[cur_s->pll]. reg_clkctl |= (100 << 16).max_speed_delta_khz) { if (tgt_s->a11clk_khz > cur_s->a11clk_khz) { /* Step up: jump to target PLL as early as * possible so indexing using TCXO (up[-1]) * never occurs. pr_debug("Switching from ACPU rate %u KHz -> %u KHz\n". /* set WT_ST_CNT */ writel_relaxed(reg_clkctl. while (cur_s != tgt_s) { /* * Always jump to target freq if within 256mhz. A11S_CLK_CNTL_ADDR). */ if (reason == SETRATE_CPUFREQ || reason == SETRATE_PC) { /* Increase VDD if needed. if (d > drv_state.

*/ if (reason == SETRATE_SWFI) goto out.ebi1_clk.if (likely(cur_s->down[cur_s->pll])) cur_s = cur_s->down[cur_s->pll]. 0). } } else { cur_s = tgt_s. } if (cur_s == NULL) { /* This should not happen. */ if (tgt_s->pll != ACPU_PLL_TCXO) plls_enabled &= ~(1 << tgt_s->pll). /* Change the AXI bus frequency if we can. */ loops_per_jiffy = cur_s->lpj. tgt_s->axiclk_khz * 1000). 1). } pr_debug("STEP khz = %u. } /* Disable PLLs we are not using anymore. */ if (strt_s->axiclk_khz != tgt_s->axiclk_khz) { res = clk_set_rate(drv_state. udelay(50). } acpuclk_set_div(cur_s). goto out. cur_s->pll). if (res < 0) pr_warning("[K] Setting AXI min rate failed (%d)\n". pll < ACPU_PLL_END. if (rc < 0) { pr_err("PLL%d enable failed (%d)\n". tgt_s->a11clk_khz). */ pr_err("No stepping frequencies found. cur_s->a11clk_khz.current_speed = cur_s. pll = %d\n". } plls_enabled |= 1 << cur_s->pll. rc = -EINVAL. if (res < 0) . for (pll = ACPU_PLL_0. pll++) if (plls_enabled & (1 << pll)) { res = pc_pll_request(pll. else cur_s = cur_s->down[tgt_s->pll]. /* Re-adjust lpj for the new clock speed. goto out. } /* Nothing else to do for SWFI. strt_s->a11clk_khz. cur_s->pll. if (cur_s->pll != ACPU_PLL_TCXO && !(plls_enabled & (1 << cur_s->pll))) { rc = pc_pll_request(cur_s->pll. " "strt_s:%u tgt_s:%u\n". drv_state. mb(). res ). rc).

for (speed = acpu_freq_tbl. */ if (tgt_s->vdd < strt_s->vdd) { #ifdef CONFIG_MACH_PRIMODD if(10!=vdd_pa) res = acpuclk_set_vdd_level(vdd_pa). speed->a11clk_khz != 0. return rc.lock). out: if (reason == SETRATE_CPUFREQ) mutex_unlock(&drv_state. } /* Nothing else to do for power collapse. speed++) { if (speed->a11clk_src_sel == sel && (speed->a11clk_src_div == div)) break. res). int res. /* * Determine the rate of ACPU clock */ if (!(readl_relaxed(A11S_CLK_SEL_ADDR) & 0x01)) { /* CLK_SEL_SRC1N0 */ /* CLK_SRC0_SEL */ sel = (readl_relaxed(A11S_CLK_CNTL_ADDR) >> 12) & 0x7. } /* Accomodate bootloaders that might not be implementing the * workaround for the h/w bug in 7x25. sel. } pr_debug("ACPU speed change complete\n"). /* Drop VDD level if we can. */ if (cpu_is_msm7x25() && sel == 2) sel = 3. if (res < 0) pr_warning("[K] Unable to drop ACPU vdd (%d)\n".pr_warning("[K] PLL%d disable failed (%d)\n". res). /* CLK_SRC0_DIV */ div = (readl_relaxed(A11S_CLK_CNTL_ADDR) >> 8) & 0x0f. uint32_t div. pll. } else { /* CLK_SRC1_SEL */ sel = (readl_relaxed(A11S_CLK_CNTL_ADDR) >> 4) & 0x07. else #endif res = acpuclk_set_vdd_level(tgt_s->vdd). } static void __init acpuclk_hw_init(void) { struct clkctl_acpu_speed *speed. /* CLK_SRC1_DIV */ div = readl_relaxed(A11S_CLK_CNTL_ADDR) & 0x0f. } if (speed->a11clk_khz == 0) { . reg_clksel. */ if (reason == SETRATE_PC) goto out.

speed->a11clk_khz).current_speed = speed. else return 0. speed->axiclk_khz * 1000). res = clk_enable(drv_state. unsigned int pll0_needs_fixup = 0. } res = clk_set_rate(drv_state. struct pll_freq_tbl_map *lst. } /*---------------------------------------------------------------------------* Clock driver initialization *---------------------------------------------------------------------------*/ #define DIV2REG(n) ((n)-1) #define REG2DIV(n) ((n)+1) #define SLOWER_BY(div. struct clkctl_acpu_speed *t. int axi_160mhz = 0. /* Wait for the PLLs to be initialized and then read their frequency.current_speed == NULL. if (drv_state. */ do { pll0_l = readl_relaxed(PLLn_L_VAL(0)) & soc_pll[ACPU_PLL_0].ebi1_clk). writel_relaxed(reg_clksel. return.ebi1_clk. axi_200mhz = 0. /* Fix div2 to 2 for 7x27/5a(aa) targets */ if (!cpu_is_msm7x27()) { reg_clksel = readl_relaxed(A11S_CLK_SEL_ADDR). pr_info("ACPU running at %d KHz\n".ACPU clock reports invalid speed\n"). } drv_state. "%s: not initialized\n". udelay(50). reg_clksel |= (0x1 << 14).current_speed) return drv_state.pr_err("[K] Error . res). .l_val_mask. factor) div = DIV2REG(REG2DIV(div) * factor) static void __init acpu_freq_tbl_fixup(void) { unsigned long pll0_l. pll2_l. reg_clksel &= ~(0x3 << 14). 1)) pr_warning("[K] Failed to vote for boot PLL\n"). cpu_relax(). pll4_l. A11S_CLK_SEL_ADDR). if (speed->pll != ACPU_PLL_TCXO) if (pc_pll_request(speed->pll. if (res < 0) pr_warning("[K] Enabling AXI clock failed (%d)\n". pll1_l. res). __func__). } static unsigned long acpuclk_7201_get_rate(int cpu) { WARN_ONCE(drv_state. if (res < 0) pr_warning("[K] Setting AXI min rate failed (%d)\n".current_speed->a11clk_khz.

} } else { /* Select the right table to use. pr_info("L val: PLL0: %d. } /* Fix the tables for 7x25a variant to not conflict with 7x27 ones */ if (cpu_is_msm7x25a()) { if (pll1_l == PLL_245_MHZ) { acpu_freq_tbl = pll0_960_pll1_245_pll2_1200_pll4_800_25a.l_val_mask. udelay(50). break. PLL2: %d\n". } while (pll2_l == 0). lst->tbl != 0. cpu_relax(). (int)pll0_l. PLL1: %d. (int)pll1_l. } /* Some configurations run PLL0 twice as fast. */ if (pll0_l == PLL_491_MHZ) { pll0_l = PLL_245_MHZ. udelay(50).l_val_mask.l_val_mask. (int)pll2_l). } while (pll1_l == 0). */ for (lst = acpu_freq_tbl_list. cpu_relax(). udelay(50).} while (pll0_l == 0). if (!cpu_is_msm7x27() && !cpu_is_msm7x25a()) { do { pll4_l = readl_relaxed(PLL4_L_VAL) & soc_pll[ACPU_PLL_4]. } else if (pll1_l == PLL_737_MHZ) { acpu_freq_tbl = pll0_960_pll1_737_pll2_1200_pll4_800_25a. } else { pll4_l = 0. we simply fix up the ACPU clock * source divider since it's a simple fix up. } } } if (acpu_freq_tbl == NULL) { . pll0_needs_fixup = 1. do { pll1_l = readl_relaxed(PLLn_L_VAL(1)) & soc_pll[ACPU_PLL_1]. Instead of having * separate tables for this case. (int)pll4_l). lst++) { if (lst->pll0_l == pll0_l && lst->pll1_l == pll1_l && lst->pll2_l == pll2_l && lst->pll4_l == pll4_l) { acpu_freq_tbl = lst->tbl. } while (pll4_l == 0). pr_info("L val: PLL4: %d\n". cpu_relax(). do { pll2_l = readl_relaxed(PLLn_L_VAL(2)) & soc_pll[ACPU_PLL_2].

t->a11clk_khz != 0.a11clk_khz. if (axi_160mhz && drv_state. for (t = &acpu_freq_tbl[0]. } /* Fix up PLL0 source divider if necessary.a11clk_khz.\n").a11clk_khz <= MAX_WAIT_FOR_IRQ_KHZ. */ if (cpu_is_msm7x27()) return. acpu_freq_tbl[i].max_axi_khz = t->axiclk_khz. */ static unsigned long __init find_wait_for_irq_khz(void) { unsigned long found_khz = 0. i++) found_khz = acpu_freq_tbl[i]. if (axi_200mhz && drv_state. BUG(). */ axi_160mhz = (pll0_l == PLL_960_MHZ || pll1_l == PLL_960_MHZ). i++) { . So we don't classify it as Turbo mode. } /* * Hardware requires the CPU to be dropped to less than MAX_WAIT_FOR_IRQ_KHZ * before entering a wait for irq low-power mode. axi_200mhz = (pll2_l == PLL_1200_MHZ || pll2_l == PLL_800_MHZ).max_axi_khz >= 160000 && t->ahbclk_khz > 128000) t->axiclk_khz = 160000. Find a suitable rate. int i.a11clk_khz && acpu_freq_tbl[i]. for (i = 0.max_axi_khz >= 200000 && t->ahbclk_khz > 160000) t->axiclk_khz = 200000. t++) { if (pll0_needs_fixup && t->pll == ACPU_PLL_0) SLOWER_BY(t->a11clk_src_div. */ static void __init lpj_init(void) { int i.current_speed. for (i = 0. return found_khz.pr_crit("Unknown PLL configuration!\n"). acpu_freq_tbl[i]. } /* Initalize the lpj field in the acpu_freq_tbl. Also. == 160000) mode supported and enabled. if (!axi_160mhz) pr_info("Turbo else if (t->axiclk_khz pr_info("Turbo else pr_info("Turbo mode not supported. const struct clkctl_acpu_speed *base_clk = drv_state.\n"). } t--. 2).\n"). /* The default 7x27 ACPU clock plan supports running the AXI bus at * 200 MHz. fix up the AXI to * the max that's supported by the board (RAM used in board). mode supported but not enabled. drv_state.

pll for (i = 0.1) && i > 0) { pr_crit("Delta between freqs %u KHz and %u KHz is" " too high!\n".max_speed_delta_khz) { acpu_freq_tbl[i]. step_freq).a11clk_khz). } if (step_idx == (i + 1) && step_freq) { pr_crit("Delta between freqs %u KHz and %u KHz is" " too high!\n".a11clk_khz step_freq acpu_freq_tbl[step_idx].up[step_pll] = &acpu_freq_tbl[step_idx].lpj = cpufreq_scale(loops_per_jiffy. step_idx--. step_idx++. cur_freq. i++) { /* Calculate max "up" step for each destination PLL */ step_idx = i + 1.a11clk_khz cur_pll acpu_freq_tbl[i].pll step_pll acpu_freq_tbl[step_idx].acpu_freq_tbl) pr_info("Id CPU-KHz PLL DIV AHB-KHz ADIV AXI-KHz " "D0 D1 D2 D4 U0 U1 U2 U4\n"). cur_freq.a11clk_khz. } /* Calculate max "down" step for each destination PLL */ step_idx = i . } } static void __init precompute_stepping(void) { int i. int i. } if (step_idx == (i . #define #define #define #define cur_freq acpu_freq_tbl[i]. #define FREQ_IDX(freq_ptr) (freq_ptr .max_speed_delta_khz) { acpu_freq_tbl[i].down[step_pll] = &acpu_freq_tbl[step_idx].acpu_freq_tbl[i]. t = &acpu_freq_tbl[0]. for (i = 0. BUG(). t->a11clk_khz != 0. while (step_freq && (step_freq .step_freq) <= drv_state. short down_idx[ACPU_PLL_END]. j. BUG(). } } } static void __init print_acpu_freq_tbl(void) { struct clkctl_acpu_speed *t. base_clk->a11clk_khz.cur_freq) <= drv_state. acpu_freq_tbl[i]. step_idx. i++) { . while (step_idx >= 0 && (cur_freq . step_freq). short up_idx[ACPU_PLL_END].1. acpu_freq_tbl[i].

acpu_freq_tbl[n].a11clk_src_sel = 3. t->pll.for (j = 0.\n"). }. &smem_size). */ else if (smem_size < sizeof(struct shared_pll_control)) pr_warning("Shared PLL control data structure too small!\n"). t->a11clk_khz. else if (pll_control->version != 0xCCEE0001) pr_warning("Shared PLL control version mismatch!\n"). /* The 7625 has a hardware bug and in order to select PLL2 we * must program PLL3. .pll == ACPU_PLL_2) acpu_freq_tbl[n]. . down_idx[0]. up_idx[1].set_rate = acpuclk_7201_set_rate. But the index used for each PLL is guaranteed to remain the * same. down_idx[2]. down_idx[1]. } static void shared_pll_control_init(void) { #define PLL_REMOTE_SPINLOCK_ID "S:7" unsigned smem_size. Use the same table. PLL_REMOTE_SPINLOCK_ID). } pll_control = NULL. up_idx[2]. else { pr_info("Shared PLL control available. } } static void msm7x25_acpu_pll_hw_bug_fix(void) { unsigned int n. } pr_info("%2d %7d %3d %3d %7d %4d %7d " "%2d %2d %2d %2d %2d %2d %2d %2d\n".get_rate = acpuclk_7201_get_rate. t->ahbclk_khz.\n"). t->ahbclk_div + 1. return. */ for (n = 0. remote_spin_lock_init(&pll_lock. } static struct acpuclk_data acpuclk_7201_data = { .power_collapse_khz = POWER_COLLAPSE_KHZ. up_idx[4]). pll_control = smem_get_entry(SMEM_CLKREGIM_SOURCES. pr_warning("Falling back to proc_comm PLL control. t->axiclk_khz. up_idx[j] = t->up[j] ? FREQ_IDX(t->up[j]) : -1. i. down_idx[4]. j < ACPU_PLL_END.a11clk_khz != 0. . t++.switch_time_us = 50. . if (!pll_control) pr_warning("Can't find shared PLL control data structure!\n"). /* There might be more PLLs than what the application processor knows * about. t->a11clk_src_div + 1. up_idx[0]. j++) { down_idx[j] = t->down[j] ? FREQ_IDX(t->down[j]) : -1. n++) if (acpu_freq_tbl[n]. and just fix up the * numbers on this target.

__func__). return n. if((val<11)&&(val>=0)) { vdd_pa=val. drv_state. sscanf(buf. BUG_ON(IS_ERR(drv_state. struct kobj_attribute *attr.buf.attr.ebi1_clk = clk_get(NULL. .ebi1_clk)). .attrs = g }.val). printk("set_vdd4patest_show=%d\r\n". . char *buf) { char *s = buf. s += sprintf(buf. "ebi1_acpu_clk"). } \ \ \ \ \ \ \ power_ro_attr(set_vdd4patest). static struct attribute_group attr_group = { . NULL. #endif static int __init acpuclk_7201_init(struct acpuclk_soc_data *soc_data) { #ifdef CONFIG_MACH_PRIMODD int ret. .mode = S_IRWXUGO. static struct attribute *g[] = { &set_vdd4patest_attr. struct kobj_attribute *attr. } static ssize_t set_vdd4patest_show (struct kobject *kobj.#ifdef CONFIG_MACH_PRIMODD static ssize_t set_vdd4patest_store(struct kobject *kobj.show = _name##_show.vdd_pa). size_t n) { unsigned int val=7.attr = { . &val). printk("set_vdd4patest_store=%d\r\n". return s .vdd_pa). "%u". "%u\r\n". const char *buf. } #define power_ro_attr(_name) \ static struct kobj_attribute _name##_attr = { .store = _name##_store. #endif pr_info("%s()\n".name = __stringify(_name). }. }. } else return -EINVAL.

#ifdef CONFIG_CPU_FREQ_MSM cpufreq_table_init(). &attr_group).max_axi_khz = 200000. }. smp_processor_id()).max_speed_delta_khz = soc_data->max_speed_delta_khz. .init = acpuclk_7201_init. }. drv_state. #endif return 0.init = acpuclk_7201_init. acpuclk_7201_data.init = acpuclk_7201_init.init = acpuclk_7201_init.mutex_init(&drv_state. .lock). . precompute_stepping().max_speed_delta_khz = 400000. struct acpuclk_soc_data acpuclk_7x27aa_soc_data __initdata = { . print_acpu_freq_tbl(). } struct acpuclk_soc_data acpuclk_7201_soc_data __initdata = { . shared_pll_control_init(). }. struct acpuclk_soc_data acpuclk_7x27a_soc_data __initdata = { . . if(ret) pr_warning("Create sysfs for PA test fail!\n"). . . }.max_axi_khz = 160000. cpufreq_frequency_table_get_attr(freq_table.max_axi_khz = 200000. if (cpu_is_msm7x25()) msm7x25_acpu_pll_hw_bug_fix(). lpj_init().max_speed_delta_khz = 400000.max_speed_delta_khz = 504000. .wait_for_irq_khz = find_wait_for_irq_khz().max_speed_delta_khz = 400000. acpu_freq_tbl_fixup(). #endif #ifdef CONFIG_MACH_PRIMODD ret = sysfs_create_group(power_kobj.max_axi_khz = 200000. . acpuclk_hw_init(). drv_state. . acpuclk_register(&acpuclk_7201_data). struct acpuclk_soc_data acpuclk_7x27_soc_data __initdata = { .max_axi_khz = soc_data->max_axi_khz.