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   µ  C  (W / L ) R  K :  ∆V   + I  R    g  ! = 2µ  C  (W / L ) ! I  = (W / L ) ! (W / L ) 2 1  1 −  R K .

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 µ     µ        ( +  −   ) =    ( −  −   ) #  ≤  ≤     .

     (  ).

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  .

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.

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⋅ ) =    ( .

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⇒ .

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1 .

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  µ         =       (  −   )     .

               +    =              =   −    =  −    '    =   #   µ     µ   µ    =       =    =     .

      .

       −  ∆  µ      ⇒ ∆  ≡   .

−    = µ     ∆    ∆ ≡   −    $.

 ' % & ∆ ≤  µ      −   µ      +   µ     ∆  +   +   ⇒ ∆  ∝ ∆ #  ⇒ +  .

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8.  7  . .  +  $  '% ..   $ '% $+% ' )    ' .

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 µ     ⇒  =   µ       µ     −   µ                  −  −                           −  −   +   −                       .

3 ∆  =  −           =   +   ⇒   =   + ∆       =  − ∆                  µ     ∆     ∆   .

       −  −     +    µ     .

  .

            .

   µ     ⇒  =  .

 µ     .

µ     ∆  ∆   ∆   .

  −  −  .

 −  + ∆ .

  −  −    µ           .

   .

 µ   .

 µ  .

  ∆  .

 ∆  ∆  ∆  .

 ∆ ∆     = − + − − +  µ  .

µ  .

  µ  .

           .

 .

 .

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 .

         .

   µ       .

 ∆ −   µ        .

  = ∆ .

 +       ∆ ∆   ∆ −  .

  + .

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'''  &.

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.

≡   ↑⇒    ↓⇒ .

.

↑ :&# 6  ↑⇒    ↓ A    ' $ %  =   <     + + α           &  # BB α.

.

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.

=  +   = +   −       100#   >>    ⇒  ≅   <       .

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= −   (     )     =          =         ⇒ = .

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∝ (  ) "!.

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.

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/* (""!.#$.

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= .

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* &&!&$#  + =  + ! −  =  + ! −  − =  =   −  µ            +  − !            ν      +  µ              .

<#.    D '' #!&$#  = −  =  + ! − + − µ             −              =      +   −   = +       ⇒ .

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Cgs1 + CLeq =>Better high frequency response.6-1 CHUNG-YU WU Chapter 6 Frequency Response of MOS Amplifiers §6-1 Single-Stage Amplifier §6-1. * If fp<fz ∵CLeq>Cgs1 C Leq G 1 = ( − 1) + Leq .1 Source follower +VDD RS M1 Vi CX Vo Vi Zi Vo gds2 M2 VBIAS -VSS AV(s) ≡ Vo(s) = Vi(s) sC gs1 + g m1 g + Cgs1 Cgd 1 + Cgd 1C Leq )s 2 + ( m1 RsC gd1 + C Leq + C gs1 )s + g m1 / α1 + G Leq á1 Cdb2 Csb1 CL Zo Cgs1 gds1 High-frequency small-signal equivalent circuit Cgd1 Ii RS -gmb1 Vo gm1(Vi-Vo) Rs(C gs 1 CL eq where GLeq=gds1 +gds2 . How to achieve this? Adding an extra capacitor Cx such that . CLeq=CL+Csb1 +Cdb2 * Left-Half-Plane (LHP) pole: fp = G Leq + g m1 / α1 2π( Cgs1 + C Leq ) gm1 2πC gs1 LHP zero: fz = In general. we have Cgs1 α1 gm1 fp = fz and Av(s) ≅ C gs1 ≅ 1 indep. of s.

the equivalent input capacitances Cin=Cgd1 Cin'      1  Cin' ≅ CLeq  C g   Leq + 1 + m1  C C gs1s   gs1  For large gm1. CLeq. Zo = Ro = If s→∞. Cin '<<CLeq The large load capacitance CL is well blocked or buffered from the preceding stage. Zo(s) ≡ Vo(s ) Io(s ) || |Vi=0 = 1 g m1 + g mb 1 1 G Leq + g mb 1 + sC Leq + ( sC gs1 + g m1 ) R s Cgd 1s + 1 R s ( C gd1s + Cgs1 s) + 1 * If s = 0. and the negative resistance gm1 - C gs1 C Leqω2 Thus oscillation is possible. 1 1 g m1 Zi(s) ≅ + + Cgs1 S C LeqS C gs1 CLeqS 2 The input impedance consists of the series connected Cgs1 . Zo'(without CLeq) ≅ Rs for Rs< Since usually Rs> 1 . we have g m1 + g mb 1 1 and Cgs1 >>Cgd1 G Leq + g m1 . * If gmb1 +GLeq is neglected.  1 Cx+Cgs1 =CLeq  G Leq  1  ( α − 1) + g  1 m1       6-2 CHUNG-YU WU Zi(s) ≡ Cgs1 s + g m1  Vi (s )  1 = +  (C gd1 s) Ii( s)  C gs1s Cgs1 s( G Leq + g mb 1 + sC Leq )    || * If gmb1 +GLeq<< CLeqS and Cgd1 is neglected.

2 Enhancement-load NMOS common-source gain stage +VDD gmb2 Vo gm2Vo M2 Vo RS M1 Vi -VSS RS + Vi _ + CL Vi _ Cgs2 RS V1 Cgd1 Cgs1 gm1V1 Cdb1 gds2 Vo gds1 Csb2 CL V1 Cgd1 Vo Cgs1 gm1V1 GLeq CLeq . * Two source followers in cascade might cause oscillation because First SF : L in Zo 1 Second SF :-R and Cin Z i 2 §6-1.6-3 CHUNG-YU WU |Zo| Rs α 1 /gm1 => Zo α ω => Inductive load Zo(s) ≅ R s C gs1 s + 1 g m 1 / α1 + C gs1 s α1 g m1 R2 ω L R1 Zo R1 =Rs- R2 = α1 g m1 C α α L= gs1 1 (Rs- 1 ) g m1 g m1 L and CL causes output signal ringing.

we have V1 RS Vin Cin (gm1-sC gd1 )V1 GLeq CLeq+Cgd1 Vo Cin =Cgs1 +Cgd1 (1+gm1/GLeq) =>Av(s) ≅ Gs (sC gd1 − g m1 ) (sC in + Gs )[s(C Leq + Cgd 1 ) + C Leq ] * Right-Half-Plane Zero:Sz = gm1/Cgd1 * Left-Half-Plane Poles :Sp1 =-Gs/Cin (input pole) Sp2 =-GLeq/(C Leq+Cgd1 ) (output pole). G Leq G Leq G Leq Zin can be approximated by the previous formula. * The exact Zin is 1   1+ (C gd1 + C Leq )s   G Leq  Zin≅ Cgs1 s  1 1  C (1 + g + C Leqs)  m  gd1s  G Leq G Leq   || If 1 1 1 ( Cgd1 + CLeq )s <<1 and Cgds1 s <<(1+gm ). the dominate pole is Sp2 ≅ (gm2+gmb2 )/C L * The input impedance can be approximated by Zin ≅ 1   1 )Cgd 1 s Cgs1 + (1 + g m1 G Leq     near the upper 3dB frequency. * If CL is large. .6-4 CHUNG-YU WU GLeq=gds1 +gds2 +gm2+gmb2 CLeq=Cdb1 +Cgs2 +Csb2 +CL Applying the Miller's theorem. If Cgd1 and CLeq are small =>Sp1 is the dominant pole.

g2 = gm2 + C 2 = Cgs1 + (1 + 1 rds1 gm1 ) Cgd1 g m2 C 2 = C gd1 + C db1 + C gs2 + C sb 2 C Leq = C L + Cgd 2 + C db 2 + Csb 3 + C gs 3 A v ( s) = − Gs g m 2 ( sC gd 1 − g m 1 ) (sC 1 + G s )(sC 2 + g 2 )( sC Leq + g m 3 ) g m1 Cgd1 RHP Zero: Sz = LHP Pole : Sp 1 = − Sp 1 − gm3 Gs g . gmb3 are neglected. g m 1 = g m 2 .3 Cascode amplifer stage +VDD RS M3 Vo VBIAS M2 CL Vin Cgs1 V1 Cgd1 gm1V1 Cdb1 rds1 -gm2V2 Cgs2 + Csb2 CHUNG-YU WU Cdb2 + V3 _ Cgs3 gm3V3 Vo Cgd2 Csb3 CL RS C1 V1 C2 (gm1-sCgd1)V1 V2 1/g2 Vo gm2V2 CLeq 1/gm3 RS M1 Vin -VSS Vin rds2 . Sp 2 = − 2 . gmb2 . Sp 3 = C Leq C1 C2 usually is the dominant pole. rds3 .then C1 = C gs1 + 2Cgd 1 .6-5 § 6-1. S p1 2π = Gs 2πC1 ⇒ f 3 dB ≅ * Typically.

4 CMOS gain stage +VDD 6-6 CHUNG-YU WU V1 Cgd2 gm2V1 Cgs2 gds2 Cdb2 RS Vin M2 Vo M1 CL Vin RS V1 Cgd1 gm1V1 Cgs1 gds1 Cdb1 Vo CL -VSS RS Vin Cgd1 + Cgd2 Vo (gm1+ gm2)V1 Cgs1 + Cgs2 GLeq CLeq RS Vin V1 [g m 1+ g m 2-s(C gd1+Cgd2)]V1 Vo GLeq CLeq+Cgd1 +Cgd2 Cin G Leq = g ds1 + g ds 2 Cin = Cgs1 + C gs 2 + (1 + Av (s) ≅ C Leq = Cdb 1 + C db 2 + C L g m1 + g m 2 )( Cgd 1 + Cgd 2 ) G Leq G s [s( Cgd 1 + Cgd 2 ) − ( g m 2 + g m 2 )] [ s( Cgd1 + Cgd 2 + C Leq ) + G Leq ]( sC in + G s ) gm1 + gm2 Cgd 1 + Cgd 2 Gs Cin G Leq C gd1 + C gd 2 + C Leq RHP Zero: Sz = LHP Poleo: Sp 1 = − Sp 2 = − If R s is large enough ( R s is the output resistance of the preceding stage).§6-1. S p1 << S p 2 Sp 1 is the dominant pole. .

§6-1.Differential-mode half circuit Cgd1 + 1 V Cgs1 2 id _ CLeq ≡ CL + Cdb 4 + Cdb 1 +VDD +VDD 1 g V 2 m1 id CLeq rds4 ||rds1 + 1 Vod 2 _ 6-7 CHUNG-YU WU VBIAS M4 1 V 2 od M1 CL M3 M4 VBIAS1 CL 1 V 2 id M2 M1 VBIAS2 -VSS -VSS Vod g m1 = H (s ) = − Vid g ds 4 + g ds1 RHP Zero: f z = gm1 2 πCgd1 C   1 − s gd 1   gm1   C Leq + Cgd1   1 + ( g + g )s   ds 4 ds1  fz >fp |Ad| -60db/Octave Ad = g ds4 + g ds1 LHP Pole: f p = 2π( Cdb 4 + Cdb1 + C L + C gd1 ) f u ≒ A0f p = gm1 2 π( C db 4 + C db1 + C L + C gd1 ) fu fz fp 2.Common-mode half circuit: ( g ds 4 + sC M ) Voc + g ds1 ( Voc − Vs ) + g m 1 ( Vic − Vs ) + C gd1 s( Voc − Vic ) = 0 .5 CMOS differential amplifier 1.

6-8 g ds 1 ( Vs − Voc ) + Vs ( Vs [ C + Cdb 5 + Csb1 1 + gd 5 s) − g m1 ( Vic − Vs ) − Cgs1 s( Vic − Vs ) = 0 2 rds5 2 CHUNG-YU WU 1 1 + ( Cgd 5 + C db5 + C sb1 )s + C gs1s ] = −[ g ds 4 + sC M + sC gd1 ]Voc + (C gs1 s + C gd1 s) Vic 2 rds 5 2 [ g ds4 + sC M + sC gd 1 ]Voc − ( Cgs1 s + C gd1 s) Vic C gd 5 + C db5 + Csb1  1  s + C gs1s   2r + 2  ds 5  Cgd1 gm1(Vic-Vs) Cgs1 VS (C sb1 +Cgd5 +Cdb5 )/2 2/gds5 gds1 gds4 CM Vs = − +VDD Vic VBIAS1 M4 Voc M1 VS VBIAS2 2M5 CM=CL+Cdb4 +Cdb1 gmb1 is neglected − C gd1 ( C gd 5 + C db5 + Csb1 + Cgs1 )s 2 + [( Cgd 5 + Cdb 5 + C sb1 CL Voc Vic -VSS ⇒ A c ( s) = ( g ds 4 + C gs1 ) g m1 Voc 2 2 =− Cgd 5 + Cdb 5 + Csb1 C gd 5 + Cdb 5 + Csb1 Vic ( + Cgs1 )( C M + Cgd 1 )s 2 + [( + Cgs1 ) 2 2 1 1 − Cgd 1 − ( g ds1 + g m 1 )( Cgs1 + Cgd1 )]s + g m1 2rds 5 2 rds5 C + C gd1 g + g ds1 + g ds1 ) + M + (C M + Cgd 1 )( g ds1 + g m1 )]s + ds 4 + ( g ds1 + g m1 ) g ds 4 2 rds5 2 rds 5 Solve the pole-zero position : ⇒ 1 RHP zero. 1 LHP zero.2 LHP poles fZR fZL fp1 fp2 dB Ad fZR >> fZL CM (C gd5 +Cdb5 +Csb1 )/2 Ac fp1 CMRR CMRR fZL fp2 Load pole fp1 < fp2 tail pole degradation region .

6 CMOS differential-input-to-single-ended output converter Vi Vo Vi = Vid + Vic Vo = Vod + Voc ﹡The hail-circuit method cannot be used in the high frequency analysis. g + g ds 4 Output pole Wp 1 ≅ ds1 CLeq Mirror pole Wp 2 ≅ Tail path: A1 (s ) = g m 34 CE Vin Ro M4 +VDD E M3 Vo CLeq CE Load M1 Tail Io -VSS CS M2 A0 s 1+ Wp1 A0 (1 + s s )(1 + ) Wp 1 Wp 2 A0 ( 2 + Load path: A2 ( s) = s ) Wp 2 Ad ( s) = A1 (s ) As ( s) = s s (1 + )(1 + ) Wp1 Wp 2 LHP zero: Wz1 ≅ 2 g m 34 = 2Wp 2 CE g ds1 + g ds 4 (output pole) CLeq ﹡Approximate analysis: The dominant pole of Ad ( s) is Sp 1 = − Ad ( s) ≅ g m1 + ( g ds1 + g ds 4 ) sC Leq . ﹡Two unequal signal paths to the output ⇒ Load path and tail path ⇒ Both Cs and C E appears in the Ad(s) expression.6-9 CHUNG-YU WU §6-1. ﹡There are two dominate poleo in Ad.

Ac §6-2 Frequency Compensations +VDD Ml1 M l2 V1 Cd M i1 gdsl+gdsi Mi2 ~ vi2 M s1 CC M g1 gdsgl+gdsg2 V2 M g2 CL ~ vi1 VBIAS M s2 -VSS Without CC SP 1 = − 1 ( g dsl + g dsi ) .10 CHUNG-YU WU g ds1 + g ds 4 CLeq 1 1 ( ) R 0 Cs Ad ) is degradated by 20dB/decade at high frequency. Cd SP 2 = − 1 ( g dsg1 + g dsg 2 ) CL V2 V1 CC Cd g dsl+gdsi CL g dsg1+gdsg2 gmg1+gmg2 equivalent circuit ⇒ g mi(vi1 -v i2) =gmivd vd ≡ vi 1 − vi 2 .The A c ( s) can be written as Ac ( s) ≅ − The dominant pole of A c ( s) is Sp 1 = − But the left-half-plane zero is SzL = − The CMRR ( ≡ g ds1 2g m 4 1 ( ) + sC s R0 sC Leq + ( g ds1 + g ds 4 ) 6 .

.135 o 180 o ⇒ Phase margin is not large enough log(f) ﹡Feedforward effect on CC How to solve this problem ? If I C = ( gmg 1 + g mg 2 )Vd . C IC V1 C V2 CC Ro I o = 0 and V2 = 0 Io (gmg1+gmg2)v ⇒ A zero is formed.45 o .11 CHUNG-YU WU H(s ) = v2 vi1 − vi 2 + g mi ( g mg1 + g mg 2 )R d Ro ( 1 − sC C ) g mg1 + g mg 2 = 1 + s [( C L + CC )RO + ( CC + C d )R d + CC ( g mg1 + g mg 2 )RO Rd ] + ( C C C L + CC C d + C d C L )RO R d s 2 where Ro ≡ − ⇒ Sp1 ≈ − ' 1 g dsg1 + gdsg 2 1 Rd ≡ − 1 g dsl + g dsi ' ( g mg1 + gmg 2 ) RO Rd CC CC gain dB Sp2 ≈ − CC ( g mg1 + g mg 2 ) CO CL + Cd C L + Cd CC Sz ≈ ' gmg 1 + g mg 2 à RHP Zero RHP zero f p1 ' fz ' f p2 ' log(f) phase 0 o .6 .

﹡Source follower can act as a unity gain buffer.6 . .(1) (g mg 1 + gmg 2 )V1 + V2 Vd --------. ﹡Keep the Miller effect unchanged.12 CHUNG-YU WU §6-2.(2) H( s ) = = g mi( g mg1 + g mg 2 ) 1 + s[RoCc + Rd ( Cd + Cc ) + Cc ( g mg1 + g mg2 )Ro Rd ] + ( Cc CL + Cd C L )Ro Rd s S p1 ≈ − ' (g mg 1 + g mg 2 )Ro Rd Cc 1 (unchanged) Sp2 ≈ − ' Cc ( gmg 1 + gmg 2 ) C cC L + C d C L RHP Zero has be eliminated.1 Using a unity-gain buffer in the feedback path Unity Gain Buffer CC V1 V2 CC V1 + ~ V 2 V2 ﹡Isolate node 1 from node 2 to prevent feedforward. g miVd + V1 + Cd sV1 + ( V1 − V2 )Cc s = 0 Rd 1 V2 + CL sV2 = 0 Ro --------.

But usually this RHP zero is large.6 . ∵ Cgs1 is very small.13 CHUNG-YU WU Actual Circuits : 1 VDD 2 VDD CC M1 VBIAS CC M1 V2 VBIAS or connected to the output V1 M2 V2 -VSS V1 M2 -VSS Cgs1 CC Rout Cout CL+Cgd1 + - V2 1 2 ⇒ V1 αV2 - + ﹡Cgs1 may introduce a RHP zero. ﹡ Rout ≈ ( g miVd + 1 1 ) g m1 gm 2 V1 1 1 + Cd sV1 + ( V1 − αV2 )( + )− 1 = 0 1 Rd Cc s + Couts Rout If 1 ≥ Cout s Rout −1     1 Cc s  1 +  ≈ ⇒  Cc s  1 C c Rout s + 1 + Cout s   Rout   .

2 Adding Rc in series with Cc. vd V1 V2 (g mg 1 −1 (unchanged) + g mg2 )Ro Rd Cc SP 2 ≅ − SP 3 ≅ − (g mg 1 + g mg 2 )Cc Cd CL + Cc C L + Cd Cc Cd Cc + Cd CL + Cc CL RC Cd CL Cc (unchanged) g mg1 + g mg 2  LHP    Zero : SZ = −  RHP Cc [Rc (g mg1 + g mg 2 ) − 1]   . Also the power dissipation of the buffer is large.large power) ⇒ large Cout. ↓ Somehow difficult to design. CC RC H( s ) = Low frequency gain : Adm = g mi (gmg 1 + g mg 2 )Ro Rd LHP Poles : SP 1 ≅ v2 can be solved. LHP Zero may form a pole-zero doublet with Sp1’ or Sp2’ ⇒ very slow slew rate !! If Rout is small . (additional power dissipation) §6-2. Resp.6 .14 CHUNG-YU WU The numerator of H ( s ) = ⇒ LHP Zero : − 1 Cc Rout V2 ( s ) Vd ( s ) is g mi ( gmg 1 + g mg 2 )( Cc Rout s + 1 ) If Rout is large . * * Freq. ⇒ (large area . too large gm1 or gm2 is required.

c mg 1 =2~4 ωu CL g mi g mi ≅ 2 ~ 4 . Adm A S = do P1 s + 1 s + SP 1 S P1 S P 1 dominant pole ⇒ Ad (s ) ≅ For ω >> S P1 Ad ( jω ) = Adm SP 1 A S . If RC = 1 1 or RC = g mg1 + gmg 2 g m2 g m 2 : second-stage transconductance S Z → ±∞ No effect on the frequency response of the OP. Ad ( j ω ) = dm P1 jω ω g mi Cc At ωu .15 CHUNG-YU WU 1.135 o log(f) . C L ≅ C c stable gmg 1 + gmg 2 Gain dB -6 dB/octave 0 dB VDD CC -VSS MC 1) NMOS Realization : f p1 fu f p2 log(f) -12 dB/octave V1 V2 phase 0o .6 . Ad ( jω u ) = 1 ⇒ ω u = Adm S P1 = Large CL ⇒ S P 2 ≈ − gmg 1 + g mg 2 CL For phase margin 450 ~ 600 ⇒ If SP2 C g + g mg 2 ≅ 2 ~ 4.180 o .45 o .90 o .

16 . s. CHUNG-YU WU  ∂I  RC =  DS   ∂V   DS  = V DS =0 1 µ n Cox W [2( VDD − V2 − VTH )] 2 L V2 ↑ VTH ↑ body effect RC ( RC )o = g mg 1 1 + g mg 2 RCmax RCmin Nonlinear Rc V2min (negative) 0V V2max V2 Design Rc : (1) Design Rc. CC VDD b. frequency performance will be degradated.I DS µC W 2 = n ox 2( VDD − V2 − VTH )VDS − VDS 2 L −1 [ ] 6 .t. 1) CMOS Realizations : a. CC M cn M cp V1 V2 V1 -VSS V2 V1 -VSS V2 Consider the case in c. CC c.: I DSn = R cn = µnCox Wn 2 [ 2( VDD − V2 − VTHn )VDS − VDS ] 2 Ln 1 µn C ox W n [ 2 ( V DD − V 2 − V THn )] 2 Ln . Sz must be large enough ! Otherwise. ( Rc )V =0V = 2 1 1 ( ) gm 2 g mg1 + gmg 2 (2) At Rc= Rcmax or Rcmin .

. Of V2 −1 Rc −1 V 2 =0 V = g mg1 + gmg 2 Rc-1 Rcn-1 Rcp-1 V2min 0V V2max V2 2.µC W 2 I DSp = p ox p [ 2( V2 + VSS − VTHp )VDS − VDS ] 2 Lp Rcp = µ pCox Wp [ 2( V2 + VSS − VTHp )] 2 Lp −1 −1 6 . If Rc = 1 + ( Cd + CL ) / CC g mg1 + gmg 2 Sz = Sp2 and pole-zero cancellation occurs. ⇒ Sp3 >> Sp1 ⇒ AdmSp1 < Sp3 ⇒ stable However. if the cancellation is not complete ⇒ pole-zero doublet occurs ! ⇒ slow slew rate.17 CHUNG-YU WU 1 Rc = ( Rcn // Rcp )−1 = Rcn + Rcp −1 = µ p C ox W p µn C ox Wn [ 2(V DD − V2 − VTHn )] + [ 2( V2 + VSS − VTHp )] 2 Ln 2 Lp If µ nCox Wn µ pCox W p = =β 2 Ln 2 Lp Rc = β [ 2VDD − 2VTHn + 2VSS − 2VTHp ] nearly indep.

z 2 ' .8pF) to control Cgs 9 + Cgs11 . z3 ' : LHP Zeros Design consideration : Any zeros below the unity-gain frequency must be placed as close as possible to their matching poles. Vout = AVTOT ( s ) = AV 2 ( s ) + AV 3 ( s ) Vin s s s ( 1+ )( 1 + )( 1 + ) z1' z2' z3' = [ AV 2 ( 0 ) + AV 3 ( 0 )] s s s ( 1 + )( 1 + )( 1 + ) p1 p2 p3 p1' : dominant pole z 1' .2 Feedforward compensation Av3 is the gain of the source follower A V3 + + -A V2 Vin + ∑ Vout Av 3 ( 0 )( 1 + Av 3 = (1 + s ) P3 s ) z3 1 LHP zero 1 LHP pole Av 2 ( 0 )( 1 − Av 2 = s s )( 1 + ) z1 z2 s s ( 1 + )( 1 + ) P1 P2 2 LHP poles 1 RHP zero (C C) 1 LHP zero z3 & z2 are generated from the Cgs of the source follower. This prevents the formation of any doublet ! z 1' = p 2 by adding CB1 and CB2(3.6 .18 CHUNG-YU WU §6-2.

19 CHUNG-YU WU Ref:IEEE JSSC . §6-3.6 .1979 Feedfoward +Miller(direct) Ref:IEEE JSSC .01% V (quasi-linear operation) Settling Time (TSET ): Ts +( TSET -Ts) = slewing period + settling period. 1%V or ± 0.921-928 .01%V V V − Io g m1 0 Slewing Period TS TP Settling Period TSET t Slewing Period (Ts): Vo from 0V to V-Io/g m1 under voltage follower connection and worse case loading.Stage Gain Stage ~ Io differential-input to single-ended output converter Vo .6 pp. col SC-15.1 Single-pole case CC + Input .1070-1077 . no. no. DEC.1% V or ± 0.(nonlinear operation) Settling Period (TSET -Ts): Vo from (V-Io/g m1) to ± 0.1980 Feedfoward +Unity gain buffer + Miller §6-3 Settling Behavior Vo ± 0. DEC.6 pp. col SC-14.

C2 >> C1) gm 2 / c2 ω2 ω2 ω1 + ω 2 ≅ = = 2ω n 2 aoω1 2 ω u 2 g m 1 / cc . Feb.(19) conventional expression After Ts: Vo= V-Io/g m1 Input voltage = V-( V-Io/g m1) = Io/g m1 => enter the linear (or quasi-linear) region Feedback Function for unity-gain voltage-follower connection => A( s ) = a( s ) 1 + a( s ) eq.1 pp.Slew rate: SR ≡ ωu = SR = dVo I |max = o dt Cc gmi ← single-pole case Cc I oω u Io = ωu uC W gmi 2 ox ( )i 2 L 6 . 1982 Ts = − g I 1 ln[ 1 − m 1 ( V − o ) ω1 I o ao g m1 1 S Fig. no.74-80.(20)-(23) two poles: S = −ξω n ± ξ 2 − 1ω n (double negative real poles) ξ = 1 critically damped ξ < 1 underdamped (complex conjugate poles) ξ= eq.2 approximation: e− ω T ≅ 1 − ω 1TS => eq.SC-17.(24) ξ= ω1 + ω2 2ωn damping ratio ξ > 1 overdamped (real and negative pole) (CC.1 Two-pole case Ref;IEEE JSSC vol.20 CHUNG-YU WU §6-3.

Fig.overshoot: eq. C2 >> C1) ω 2 < 4ω u ω 2 > 4ω u underdamped overdamped ω 4ω u ⇔ 2 = 2 ~ 4 ωu (1) Underdamped: TS eq.(39) Vo(t): eq. (33) (2) Critically Damped V max. vol.8 t Further references: (1) IEEE JSSC. 1986 . pp.(40). (35). Aug.389-394.7. SC-18. June.478-483.(47) Simulation & Calculation : Fig. (14) or (19) TP eq.6 . SC-21. pp.21 CHUNG-YU WU ξ 1 => CC => ω2 4( g m1 )C2 gm 2 (CC.(36) settling time: eq.(43) 0. vol.001 TS TSET t (3) Overdamped V TSET : eq.(41) TSET : eq. 1983 (2) IEEE JSSC.

S p 2 .1 Two-stage OP AMPs Two poles: S p1 .6 . S p 1 << S p 2 If S p1 << ω u << S p 2 .( W / L )i ↓ ⇒ SR ↑ * I o / C L ≥ I o / CC or CL dVout dV ≤ CC out ( = I o ) dt dt Slew rate enhancement and degradation Vin V1 t Vo Vin V1 + Vo degradation t enhancement . I o ↑.22 § 6-4 Slew rate of CMOS OP AMPs § 6-4.Vout ( s ) = g miVin ( s ) / sCc Vout ( jw ) g = m Vin ( jw ) jwCc At ω = ω u . ⇒ ωu = Vout =1 Vin CC gm1Vin + CHUNG-YU WU CL Vout gmi or CC = g mi / ωu CC dt max The slew rate SR = dVout = I o / CC = ICω u Io = ωu gmi 2uC ox( W / L )i ω u ↑.

23 (1) Positive step + VDD M3 off off M4 Io + iw Io + iw + CHUNG-YU WU CC vout CL M1 off vw Cw iw on M2 Io .VSS + ~ + vin - V1 0 iω ( t ) = Cω dvω ( t ) dv ( t ) ≅ Cω in dt dt 1 I C vout ( t ) = ( I o + iω )dt = o t + ω CC 0 CC CC ∫ t ∫ 0 t dvin dt dt = Io C t + ω V1u( t ) CC CC (2) Negative step + VDD M3 on M4 on Io .VSS off M2 + + Io + iw CC vout ~ + vin - V1 .i w Io.iw M1 Cw iw on vw Io .6 .

6 . I o :First-stage bias current Vi CL Vo SR of the folded cascode OP AMPs + VDD Ip Io VBIAS2 M6 VX Ip-Io M3 M4 Ip VY Ip Io Ip-Io M7 VB M9 .24 vout ≅ vω d I −i dv i vout = − o ω = ω = − ω dt CC dt Cω dvout Io =− dt CC + Cω ⇒ iω = I oCω ( CC + Cω ) CHUNG-YU WU slew degradation § 6-4. .VSS M 10 M8 CL Vout M5 VBIAS1 M1 V off M2 Vs Io SR = Io CL * If Ip=Io. we can keep M5.2 Single-stage OP AMPs SR = Io CL + Different phase margins ⇒ different settling behavior. M1 and Io current source in saturation.

How to solve this problem? (1) Keep Ip = Io as the optimal design. the recovery time of Vx is very short.1 Low frequency analysis for integrators + VDD M3 M4 CC Cgd Vin Cgs Io . * If Ip < Io.VTH12.25 CHUNG-YU WU The change of Vx is not significant because the gain of the common-source amplifier M1 is nearly equal to –1. The decrease of Vx is large. § 6-5 Power supply rejection ratio (PSRR) § 6-5.6 . the current source Io is forced to linear region and Vs ↓ Vx ↓ . ⇒ The settling is slow down. Thus the recovery time of Vx when M2 is turned on is very long.VSS M1 M2 gain stage Vout CI . When M2 is turned on. M11 and M12 are turned off by setting VDD-Vx < VTH11 . (2) Add clamping devices between VDD and Vx(VY) + VDD VBIAS1 M 11 X M12 VBIAS1 In normal operation.

vol.26 ∂Vout Cgs  ∂I o 1 ∂V  C 1 ∂I o ≅ + GS 1  + gd  ∂VSS CI  ∂VSS 2 gm1 ∂VSS  CI 2 gm3 ∂VSS CHUNG-YU WU Io -VSS Cgs + CI C ∂ Vout ≅ − gd CI ∂VDD  ∂I o 1  C gs 1 ∂I o 1 − V 2 g  + C 2 g  ∂ DD m3  I m1 ∂V DD CI VDD M3 Cgd + Ref. 1984.929-938 . Dec. * Cgs / CI and Cgd / CI have a strong effect on PSRR+ and PSRR-. 1980. pp. sc-19 . JSSC . * Small CI ⇒ chip area↓ but PSRR↓.SC-15 . § 6-5. Dec. vol. : IEEE . pp.VSS .6 . 919-925 . + VDD M3 M4 CC V1 Vi + Vi Rz Vo M6 M1 M2 VBIAS M5 M7 . : IEEE JSSC .2 High frequency analysis for OP AMP’s Ref.

e. i. .27 CHUNG-YU WU * PSRR+ ≡ ∂Vo ∂Vi ∂Vo ∂VDD = ∂Vo ∂Vi Vo = 0 ∂Vo ∂VDD V  ∂V =  io  ∂VDD  Vo =0     −1 o =0 How to calculate ∂Vio ? ∂ VDD VDD ~ Vi Vio + VSS V1 Go1 gm1Vio C1 gm2(V1-Vi ) CC Rz =1/gm2 Go2 Vio Vio ~ PSRR+ ( s ) ≅ Vi( from VDD ) s + Go 1Go 2 /( g m2 Cc ) s + g m1 / Cc where Go1=go4 ( go2 is connected to the drain of M5 which is open-circuited. rds5 → ∞) Go2=go6 (rds7 → ∞) Go1Go2/(g m2Cc) < gm1/Cc ⇒ Low-frequency LHP zero degrades the PSRR .6 .

Cc must be decoupled from the gate of M6 to eliminate the LHP zero .6 .28 CHUNG-YU WU * To improve PSRR. .

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+   +      ≈ ≈  Ω      B→   = .

=   Ω    .

  = µ  .

  [ ( +  −   )]  1 .

   A7 ⇒   /A7  ⇒  ⇒ ⇒   .

    .

  ≈  4 µ   ≈  µ   89>   =  .

     µ (  −   )   −   ≈  6    ≈ .

    =    µ .

 ( −  )     / .

!⇒!:.

! D .

 "  89>  ≈ µ.

      #    ( ) = ( ) ≈    ≈   µ .

  .

     ≈ $      =      ≈ µ  .

  .

       =      ≈ $ / .

  ⇒  =  =  µ =  =  µ =  µ  *8 7    89%   %=%   % + .

 ≈ .

   .

× µ  .

      = .

+ ⇒  " =  =  − %   %=    ! µ  .

 =       − −    ⇒  = −.

.

 **.

     .

 89         µ  .

 .

       +  − .

 =   ⇒      ≈       =  =  µ  *'.

               89 =  +  =    = − +  = −  /  # =  µ  ⇒   = −  =  ⇒  = −    =  +  = −      ≈ .

.

µ  .

    $ −    # ≈        = µ  .

     −   /  $ =  µ  : $ =  µ       =  µ  :  =  µ      $ = #         *2% !B/8        ! 3!  E   C &&'&()& * &&'&()& ++.'&+'#/( /( 0&& 11 " . -+  .

 .

  .

          .

           .

    #$%&'(        .            (                       6 5       = / -(.                                                              = " !                                    !             ! #$%&'( )                     *+     )        %    )            "(    . !   .          .      = / -(. =    =   0   = "  "   0        = 1 -( ! 0   ( )      !    )     ⇒  !     2   3                          3 4          . !  #$%&'(.

*.*9        ⇒  :   )    0& .          .    ))                              %)  ⇒  )      ⇒      < -7        = !  2  !=     =        !=2( )         ⇒    /2        =  +  =  / -(. + -  2  != > !     )         =         .     8  = ! 7      !  #$%&'(   .

 .

  .

   '  4)   ? = − α  ! =      ! =  # 8  8   @    =  != # 48 58 ?  = α               (     )        :  =  ?    +  ?      ?    =   +  = ?     ?   =  +   ! = = .

         ! ↑  =  ↑   ⇒      :             (    )  = = =        )   !       .

 .

  .

  2#$%)           ? = −    .

 AA .

      ?  = −    .

 AA .

        = "  µ  2  !    " = µ  2  !    " =  µ  2  8 .

  #   58  8  # 8           = "         = " B +   >  µ 2 ! = =        "  .

         "2#$%    4 )   4        :  = ? =     +     .

 AA .

           "  8 .

 48 58 #   8 ?  =     .

 AA .

       =         =     #   # µ 2          = "   >  ⇒   :  = "  B + µ  2  ! = =     "        ! ↑  =  ↑    :  ↓         $)  = =    " =  µ  2      " µ2     = 0µ? 8 "  µ  2  # # 48   (    #    #      )C   ') 3D#$%3            = /1 × 9  µ8 ⋅ µ            µ2    = Eµ?  8 "    :#$%3  .

         = 019 × 9 µ8 ⋅ µ             .

 3 ≈                           . :#$%    D#$%              !F    4          "  )                                      0'     ))              = Gµ? .

  3 #  #   3 G99µ                   #   #   3 99µ      00H Gµ  D#$%  :#$% Gµ /µ  D#$%  :#$%      ⇒   :  = 01µ8            .

  3 #  #   3 G99µ            #   #   3 G9µ      IH //µ      ⇒   :  = EGµ8         02#$%   )   8 ? ≡  =    +     .

 AA .

    8 ? = −    .

 AA .

       ?  = −    .

 AA .

          :  =       +            +    8  58  D#$% # 8  :#$% #    =     ⇒   :  =         +   = +   " " ! = ! =  48        =  J != ⇒         ≠     .

   ⇒   :  = µ  2        = "  +  µ  2    =  ! =   "    µ 2        ! =  "  + µ  2  ! =        "                                  )      ') 3   99µ ?   .

  3 # 3 999µ Gµ  # " 3 /99µ /µ        ⇒   :  = 1µ8EHEµ8                  .

   3 # 3 999µ Gµ  # " 3 "99µ 1µ                     ⇒   :  = GHµ8GIGµ8                  .

   3 # 3 G99µ       9µ  # " 3 /99µ /µ  ⇒   :  = 9Gµ890Iµ8             ⇒     !  D#$% =                             !  :#$% =   : 3!=D#$%:#$%     .    3K42  K%%2%24/))EE04EEI? HEH   :  )  ) #$%&'(3   8  @   8@7J   9   9         9    99 - 9- 99- # 9# &  7J         .

 .

    # ?  .

5 4 .

    %      )      8    ? 8 ?  ?   8 8  8  # #  8  ? 8   8  # ? # 8   8  # # .   8      8  8  .

       8 #  8.

= 8 + 8  +     8  + 8      # # 8 = 8  +     @      8   8 ≈ 8.

+ 8        8 48  ?.

 = 8 + 8  +           8  + 8               + B 8  +        8  > ? .

   ?  L-7        A ? .

   A++    ⇒ 8         $D      (  )              ?     A ? .

   A ≈     >>  ! #   #            >>                       8  ⇒    8   )  8   8  (  #     4            . D#$%     (    8           )                        !.

 "# $$ %.

&! '  (         &2#$%"4 $D?#D       4                    .

  O A ? A++ .  2  2 .      .  =  ⇒ J = ∞     A J  ALA D ALA D A 8 8         D ≈ − 8 D ≈ − 2  8  2  ? 4"9 @. . .  >− P 8      J! =      ≈ −                  =7DJ 3 −              .  << . + .  + .  .  > 8     = 8  + ? +  +   +                   8 N + B2   .  << .   + .7DJ   8    3 J = B2   − . . > +   2 2  .  ?  4 2 . + 2  . + ."   ′ − + .   + 2 .    ′    = 2 2  2  .  > + 2 .J 5   ? 8  5 4  8 5  8  4  8  .  M  = ?  8   + ?  +  +       ? = ? + ?         = 2 B?     8  2"Q*252 .        ′ ′ ′    = .  .   2 << 2   2 << 2   ⇒  =7DD 3 D ≈ −         2  << 2     2 D ≈ −    2  D ≈ −  2 . + 2  .  2 2  + 2 2  + 2  2   + .  ? B − 2   − .  2  8   8                                4  .

 4/9 @.

 R ≈ −  2. D ≈ −    2 D ≈ − 2 4"9 @.

 5"9 @.

 .

              (                 ! =   ! =    ≈   /2     = A D A   / −   /2     = A D A − A D A   / / /2  /2    2++2   8 = ∑ / -(γ      0  !  ?   S  =    ≈     " 2      ′ ? ?        / -(γ  + / -(γ    /2  /2  ′  + ?     + ?  =     = ′ ? ?  -( -(  γ + γ  + ? 2  + ? ′ 2      ′ ′    ?    ?         D   D        (      $D?#D    ))  2                             2         .

    P"   )  )  ))            .                     $D?#D  T                  4)       )*$  .      P0     .      %2&                    )       2.

          8  3    )   $D?#D                                   8  3     )                           8  8          .

  ≡       &) 4)$D?#D .

            8  ≈ 8 ?.

                 8  ≈ 8        ⇒  .

   ≈  −   !  .

     +#'.

.

'' .

    .     .≡            2  µ  " 58 #  .

 #.

   #  5 6 8  # #  8 8*848 8.

*8 48 #.

 5 8.

6  8 .

 !   " .  ?≡ ? + ?       ∆? ≡ ? − ?   "   " =    ∆  +      !   "         .  !     = + ∆=   "  ∆!  ! + "    ∆=      = −   "   + ""   −    ! − ∆!     "       "         = ∆8! +   . "  8%# ≡ 8#$" − 8#$   "  =   =    "  −      + 8! " − 8!   !  "   . −       ≅ ∆8! +        −         !   " = " !   .       " =     ∆=   ∆!    ∆=   ∆!    −  −  −   +  + "         ≅ ∆8! +      +          !   " " =  " "!   " " =  " "!   " =    ∆= ∆!   " =    ∆. # 48  " =  .

 " .& ! (8# − 8!  )  ∆.&.& "! " =  8#  − 8!    ∆! ∆=   .& "  !  . !  " =  " !        "%    8%# =     $D?#D  .∆ =  " −  =  = . ∆.&  !     (8#  − 8!  " ) −   (8#  − 8!  "  =  " "  =  )        .& ∆! ∆=  " ∆8!    + − −   =    ! =  8#  − 8!    &  ⇒ 8%#  " =    ∆= ∆! ∆.& + ∆! − ∆=  − "∆8!     " = ! =  8#  − 8!    &   ∆.& ∆! ∆=  ∆8!      − = ∆8! +  − + + − −   "=   !   " ! " .& !   ∆=  ∆! −  ∆8!      → 9  ≅ ∆8! + (8# − 8! ) +  "! " =   .

.

' ' ! "# .

     =                      "   "  ?   "? "U "U    0U 0U "U "U 0U 0U  "? ? 4 )      "   "U "U ?   "?  "       # 0U 0U "? ? 0U "U "U 0U = =  ! ∝ 8' ⋅   =  = -=  =  " = -= "   =  = :  !Q    = =  " = "     8%.

     8%.

 ≠ 9   ? %       ?%   24 ) 3  # " +  # =  #  " +  #     8# 8 8 8 8  + -:  + # = #  + #  ⇒ # ≅ = " = =" = 8#  -+:  .

3 '''K%%2%240))EH4EH1.  0H))"G94"EEK  HE1  24         ∆8!  .  -**+)      ⇒  ≅ 9 ⇒ 8%# ≅ 9         -*:*   " 8# ≅  ⇒  $      8#     8# = 99"0  8#    4)    " ?"? 8#  = . 3.2?.=  = 9/H    8#  "  8%#  8#   .

HE1  '''K%%2%24I))II4II1.

H1  ". 3'''K%%2%24"9))IGE4IIGK  H1G 0= 8# − 8!           /.  )             %        G 4       " %  )       I %     0 % )   J    E %      / #         1 :    J   .

              ! @ = "  ! @ =    ! @ =   " 8.

3  '''K%%2)/HH? HE1 '''K%%2%249))0E40EH. = 9  "    ≈ 9  = =  ! @ = (  ! @ = ( "  ! @ =   (  ) 4             = ( = = " = =                 D#$% # "  #   :#$% # "  #   D#$%4 )     "?)       G%) 4            .

HEG '''K%%2%24"9))19G419EK  H1G '''K%%2%24E))991490.

H1I '''K%%2%24I))E/G4E/1.

H1 '''K%%2))10E41//? H1G ?))  3 R 4 $D?#D7 4)   )    )  7 4)   )   %  4) )  %  4)  .  .

     $    $D4?#D4   4) %2)   %2)    %  8  α2 " 5 8 4  2 $D?#D  " 8   α +  =  ⇒  = α +        "#  %2?)   2  % "  α2 8   " 5 8 4   $D?#D " 8  % )3% $:% "$&&3 α2 8  5 × 4 5  8 4 5 8 4  $D?#D ×  8  % )"3% "$:% $&&3    .

5 8 4     α2   9 * 2 9 !3! 5 8 4 .   .   α +  −  =    (   T      %      " $    )   )     > .%#)  D4#$%&'( %  %" 2  &. /   2 )       3 ε = 9    = 9    +   .  / ≡ / /≅* *.  / 9  ⇒ ε = 9 9  + 9999   = 99 µ  ↑ ε ↓         )       )          ε  .

.

%# )    4J    )) 4 J    . )       J            J .

)       </      " %0  2" %/ 0  B5 %? .

φ φ" φ0 φ/        $: $&             .

 )      .  =   + ε   @     −  3 )    ε  3)  .

vol. *V BIAS is nearly independent of V DD and V ss .6-26 ∂Vout C gs  ∂I o 1 ∂VGS1  C gd 1 ∂I o ≈  ∂V 2 g + V  + C 2 g ∂V ∂V ss C I  ss m1 ss  I m3 ss ∂Vout C gd  ∂I o 1  C gs 1 ∂I o ≈ + 1− ∂V DD C I  ∂V DD 2 g m3  C I 2 g m1 ∂V DD   If I o Where I o represents the input stage bias current.8-1 CHUNG-YU WU Chapter 8 Advanced Design Techniques and Recent Design Examples of CMOS OP AMPs §8-1 Advanced Design Techniques of CMOS OP AMPs §8-1. is independent of V ss and V DD and the input devices have no body effect. SC-15. M5 . 1980 BIAS GENERATOR +VDD M3 OP AMP M4 M6 M9 IREF V- M10 V+ M1 Io M2 M8 M7 Vo M11 M12 VBIAS -VSS * I REF is generated by using the power supply independent current source. pp.929-938. Dec. C gd ∂Vout ∂Vout →0 →− ==> CI ∂V ss ∂V DD Ref.1 Improved PSRR and frequency compensation P.: IEEE JSSC. *It is better to use separate p-wells for M 1 and M 2 to avoid the body effect.

process .8-2 *Tracking RC compensation Conceptual circuits : +VDD gm1VIN + VIN2 CHUNG-YU WU + V 2 os V oltage source Mc (M10) MB(M6) CC MA (M8) (RC) KI -VSS CL I In the quiescent case . =>Tracking design to make sure that z=P2 =>No pole-zero doublet problem! . and supply variations. P3 ≥ Ado P1 or Cc ≥ g m1 c 1c L gm 2 allows a smaller gm2 and larger C L * RdsA ≈ Rc indep of temperature.Vin2=VOS2 If (W / L) A ≈ [(W / L) B • (W / L)C • K ]1/ 2 => RdsA ≈ Cc + CL ≈ Rc gm 2Cc Cc Cc + CL The requires Rc is Rc = 1 / g m2 [1 + (C d + C L ) / Cc ] ≈ 1 / g m 2 [(Cc + C L ) / CC ] Thus LHP zero=LHP pole P2 and P3 becomes the second pole. The stability considerations.

: IEEE JSSC .2 Improved frequency compensation technique. pp 629-633.1983 Grounded gate cascode compensation +VDD M11 M12 VBIAS1 M13 IBIAS M16 + VBIAS2 M1 MC1 M2 MC2 Cc 5pF M5 2x M9 3x MB M7 M12 M14 M16 M11 Cc M8 M13 CHUNG-YU WU + M15 V out M8 3x M10 3x V o M14 M15 M3 M4 M6 VBIAS1 .sc-18. * VBIAS is not strictly independent of VDD and VSS.8-3 CMOS Design +VDD M1 M3 M5 VBIAS M9 M6 M17 M2 M7 M10 M4 -VSS * M17.M11:Sharing the separate n-well.Cc : Tracking RC compensation. Ref. Dec.vol. §8-1. * M9.

969-982. dt o The input voltage Vi can’t reach the node A è * Better PSRR (∵ no low-freq.3 Improved cascode structure 1. To improve gain: Ref: IEEE JSSC .M10:new compensation circuit. Conceptual circuits: +VDD 2Io CS1 I1 A Cc _ gm1 -gm2 Vi R1 CS2 I1 R2 + V o -VSS Net current in CC (C c d V ) enters the second stage. 1982 ☆☆ +VDD M1 M9 M2 V o M1A Rc M2A M7 M4A M3A M4 M3 -VSS M8 M6 Cc . especially PSRR * Allow larger capacitive loads. vol. pp.8-4 CHUNG-YU WU MB. § 8-1. M11~M16:Bias generator. * Slight increase in complexity .Cgs7:low pass filter for high frequency noises.M9. zero ) . Dec. M8. random offset and noise. SC-17.

47V ~ VDD 99dB 1. * Improved wilson current source is used as the load to improve the balance of the first stage. Dec. (+ grounded) * Capable of high current driving and M2 M4 BIAS IN high voltage gain. SC-19. 919-925. pp. vol. 1982 * Inverting mode only. vol SC-19. Cascoded CMOS OP AMP with high ac PSRR Ref: (1) IEEE JSSC .8 V/ìsec . vol.969-982. _ + M6 M7 OUT M1 M3 Cc M8 M10 3.sc-17. pp. 1984 (2) IEEE JSSC .8-5 CHUNG-YU WU * Substantial reduction in input-stage common-mode range.5/10 MN6 42. pp. 1984 1) Original version +VDD 200/10 200/10 25/10 M9 -VSS Mp2 50/10 Mp3 Mp4 A Mp7 100/10 1125/10 Mp5 Cc V out CL 50/10 IBIAS 5µA 100/10 - MN1 MN2 + Mp5 100/10 200/10 MN5 100/10 42. +VDD 2.0MHz 1.55-61. Feb. Single-stage push-pull class AB CMOS OP AMP M5 Ref: IEEE JSSC .5V Input offset voltage Supply current Output voltage range Input common mode range CMRR @ 1KHz Unity-gain frequency Slew rate 5mV 100ìA -VSS~VDD -VSS+1.5/10 MN8 500/10 MN9 MN3 100/10 MN4 -VSS MN7 Chrarcteristics: VDD=VSS=2. * Not a differential-amplifier-based OP AMP. Dec.

Dec.Simple cascoded CMOS OP AMP Ref.:IEEE JSSC . * The possible spike in the settling period.919~925 .8-6 * Better input common-mode range. vol. * C c is decoupled from the gate of the driver M 8 . 1984 +VDD M5 VBIAS1 M3 M6 M4 Cc M1 VBIAS2 M2 M5 -VSS + M9 M8 V out * Good PSRR * Reduced input common range. M10 M11 + Cc M3 M4 V out M6 M8 CHUNG-YU WU M9 . pp. * Vic↓è VDSN4↓è IDSN4↓è VA ↑è MN8 is turned on è Vout→-VSS voltage spike at Vout. ⇒ No voltage spike at Vout Also serves as CMFB * Better PSRR and input common-mode range. 2) Improved version +VDD VBIAS1 M7 M12 M5 VBIAS2 M13 M1 M2 VBIAS3 M14 -VSS * M 12 . ⇒ restrict its applications to those which use a virtual ground. M 13 and M 14 : Let the drain bias currents of M 10 and M 11 follow the change of I D7 under positive input common mode voltage. 4.SC-19 .

T10 : Cascode structure * Output conductance ↓ without any noise penalty and with only a very small reduction of phase margin.8-7 5. * Maximum output swing↓ § 8-2 Advanced Design Techniques on High-frequency Non-differential-type CMOS OP AMPs 1.657~665 . June 1985 ☆☆ CHUNG-YU WU + T6 T2 1 T4 A T8 T12 T10 Out CL Io T9 T14 InT1 T3 In+ T5 IBIAS T11 T7 T13 T15 T17 - T9 .Single-stage cascode OTA Ref. vol. SC-20 . pp. Single-ended push-pull CMOS OP AMP *Current-gain-based design .: IEEE JSSC . ⇒ Gain↑ no any compensation is necessary.

1mW 2.1mWatt V DD = +3V .2mW M11 -Vcc M2 M16 M12 CL M9 M6 CHUNG-YU WU .5VP Output Resistance 3 MΩ Input Referred Noise (@1KHz) 0. CL=1pF TABLE II Bias Current 25 µA 50 µA 100 µA Unity-Gain Bandwidth 50MHz 70MHz 100MHz DC-Open Circuit V oltage Gain 70dB 69dB 66dB DC-Power Dissipation 0.54 µV / Hz DC-Power Dissipation 1. VCC = −3V . I B1 = 50 µA .55mW 1.8-8 +VDD M8 M5 M14 M15 M13 M7 OUTPUT M1 INPUT IB1 M3 M4 M10 TABLE I Parameter Measured Value DC-Open Circuit Gain 69dB Unity0Gain Bandwidth 70MHz Phase Margin 40o 200 V / µ sec Slew Rate PSRR (DC+) 68dB PSRR (DC ) 66dB Input Offset Voltage 10mV CMRR (DC) 62dB Output Voltage Swing 1.

C L = 1 pF .VSS .8-9 V DD = +3V . CMOS output stage using a biplar emitter follower and a low-threshold PMOS source follower. + VDD VBIAS Vout Vin .Low output resistance CMOS OP AMP * C L is a compensation capacitor *For low-resistance load *Smaller maximum output voltage swing. A.1 Efficient Output Stages. CL=1pF 2. f u = 60MHz +VDD M8 M5 M14 M15 M13 M18 M7 CL M16 IB1 M3 M4 M10 M11 M20 -Vcc M12 M19 M21 OUTPUT M1 INPUT M2 M9 M6 M17 M22 CHUNG-YU WU § 8-3 Advanced Design Techniques on High-drive MOS Power or Buffer OP AMPs § 8-3. * I B1 = 50 µA. VCC = −3V .

VSS § 8-3. Complementary class B output stage using compound devices with common-source output MOS. + VDD MP A Vi A Vout MN .2 High-drive power or buffer CMOS OP AMPs 1.8 .10 CHUNG-YU WU B. Large swing CMOS power amplifier (National Semiconductor) + V DD V IN + C0 M16 A1 + M6 M9 V OUT M8 M8A M10 VBIASN M17 - A2 + M13 VBIASN M12 M6A M11 -VSS .

VCC M3 M4 MPC VIN M1 VBIASN M5 VSS VSS M2 CC VOUT M6 . and M 12 form a current feedback to stablize the bias current of M 6 and M 6 A . M 10 . Full swing from + VDD to − V SS M 9 .g. M 6 A form a class AB push-pull output stage.8 . M 11 . VinA1 + ↑⇒ Vout ↓⇒ VinA1 − ↓ (virtual short between + and -) ⇒ VinA 2 − ↓ througt M 8 ⇒ All the bias voltage and current are restored to the normal values and the offset is absorbed by M 8 A . Offset in A1 .e. i. M 6 and A2 . VinA1 − ↑⇒ VoutA1 ↓⇒ I DM 6 ↑ and I DM 9 ↑⇒ I DM 11 ↑ and I DM12 ↑⇒ VGSM 8 A ↑ and VinA 2 + ↓ ⇒ Vout ↑.e.some current variation in transistors M 6 and M 6 A still exists. Since the current feedback is not unity gain .11 * Noninverting unity gain amplifier CHUNG-YU WU Vout + Vi A1 M6 ~ + V DD * * * Vin ≅ V out M 6 provides the negative feedback A1 .

. M N 4 . M P 4 and M P 5 are output short-circuit protection circuitry. M 3HA and M 4 HA turn off M 6 A in the positive voltage swing * * M P 3 . (because Vin ≅ V out ) The maximum VGS 6 which M 1 and M 2 still in the saturation region is VGS 6 max = −( VDD − ( VIN − VGS 1 + VDSAT 1 )) = −( VCC − VIN + VTH 1 ) ⇒ VTH 1 ↑⇒ VGS 6 max ↑⇒ I DM 6 ↑ (1). ⇒ M 1 . M 6 will be turned on.8 . M P 5 is off. Similarly. M 16 . Normally. M 3 and M 4 are off ⇒ M 3 H and M 4 H are still on to keep VGS 6 ≅ 0V . If Vout → −V SS .VSS V OUT * * The input stage is not shown in the diagram.12 CHUNG-YU WU Large positive common mode range allows M 6 to source large amount of current to the load. M 17 form the second stage with C D the Miller compensation capacitor. VDSM 5 → 0 and I DSM 5 → 0. M 8 . M 2 . Otherwise . Threshold implant to increase VTHO1 VTH 1 (2). Negative substrate bias − V SS to increase + VCC M3H M4H VIN + MP3A MP4 MP5 MP3 M1 M2 MN4 M5A M13 M12 M11 MN5A MN4A MRC CC M6 M8A CF M9 MRF MP4A M5A V BIASP C0 M16 M3 M4 M10 MN3A M2A M1A M8 M4A M4HA M3A M3HA M17 V BIASN M5 MN3 . M N 3 .

0Vp RL=15 kΩ CL=200 pF Tsettling (0. I DMP3 ↑⇒ I DMN 4 ↑⇒ VGSMP5 ↑ .14 13 CHUNG-YU WU CHUNG-YU WU When I DM 6 ≅ 60mA.1%) Slew rate 1/f noise at 1KHz Broad-band noise Die area Simulation 7.08% 0.13%(1KHz) 0.0us 0.0mW 83dB 420KHz 1mV 86dB 80dB 106dB 98dB 0.4mV 85dB 81dB 104dB 98dB 0.6V/us 130nV/Hz 49nV/Hz 1500mils2 TABLE II COMPONENT SIZES ( µm.0mW 82dB 500KHz 0. Table I POWER AMPLIFIER PREFORMANCE Parameter Power dissipation( ± 5V ) Avol Fu Voffset PSRR+(dc) (1KHz) PSRR-(dc) (1KHz) THD VIN=3.88.0us 0.03% 0.32%(4KHz) 0. ⇒ I DM 6 is limited to approximately 60 mA..3Vp RL=300Ω CL=1000 pF VIN=4.05% 0.8V/us N/A N/A Measured Results 5. pF ) .20%(4KHz) <5.16% 3.13%(1KHz) 0.

High-performance CMOS power amplifier (Siemens AG) (1).:IEEE JSSC . + VDD BIAS M5 M10 M11 M13 + M1 M2 M8 M9 CC M7 M3 M4 M6 .M4HA M5A M6A MRF CF 184/9 66/12 184/6 36/10 194/6 16/12 145/12 2647/6 48/10 11.M2 M3.0 M8A M13 M9 M10 M11 M12 MP3 MN3 MP4 MN4 MP5 MN3A MP3A MN4A MP4A MN5A 481/6 66/12 27/6 6/22 14/6 140/6 8/6 244/6 43/12 12/6 6/6 6/6 337/6 24/12 20/12 6/6 Maximum loads : 300 Ω and 1000pF to ground.VSS M12 * Cc is connected to the source of M9 to improve PSRR .0 88/12 196/6 10/12 229/12 2420/6 25/12 10.M2A M3A.M4 M3H.MI6 MI7 M8 M1.SC-18 . Ref.M4H M5 M6 MRC CC M1A.624-629 . pp. vol.M4A M3HA.1983 2. Dec. New input stage : 3 gain stages.

VSS Class AB source follower * * One pole and one zero at high frequencies. g m13 >> g m 6 (2).15 * Three poles and one zero : Z= P ≅ 1 − 2 g m 6 g m8 g m13 C c g m6 g m13 + C 1 g m8 g m12 − g ds10 g o g m13C c 1/ 2 CHUNG-YU WU LHP.8 . Not full swing . Output stage + VDD VBIAS Vout Vin . 2 g g  g m8 (C O + C C )   − g m8 (C c + C O ) m8 m13   P2 . P3 ≅ ± j −   2C O C c 2C O C c  C O C1      where g o ≡ g ds12 + g ds13 C O = C L + C db12 + C db13 C1 = C gs13 + C db11 + C db 9 + C gd 9 Design guidelines for stability : g m8 large .

M15 M5 M6 - AMP 2 error amp.2 M2 . M17 . Large phase shift at high frequencies due to A1 and A2 ⇒ stability problem. + VDD BIAS Vos M3 M4 Vos VIN + -AMP 1 + error amp. M1 and M2 provide a high-frequency feed-forward path.VSS Pseudo source follower * The quiescent current in M1 and M2 will vary widely with variations in V and V os1 os2.8 .17 CHUNG-YU WU CHUNG-YU WU + V DD A1 + M1 Vout Vin + A . Suitable common-mode range of the two amplifiers A1 and A2 are required. * * Combined output stage: * M1 and M2 are turned off in the quiescent state by building a small offset voltage into A1 and A2 ⇒ M3-M6 control the output quiescent currents. M6 . * * M2 (M1) sinks (sources) approximately 95% of the required currents.VSS Still has a smaller swing limited by M5. .16 8 .

8 . P3 ≈ − m 7 c    2Cc C L C cC L C1 2C cC L        where C1 = C gs 9 + Cdb 6 + Cdb 7 + C gd 7 . * * Z1 ≈ − g m7 + g mbs 7 Cc + Cgs 7 − gL P≈ 1 C L + CC g m15 g ds 6 1 g m15  2  g m 7 g ds6 (C L + Cc g )  g (C + C )  2  g (C + CL ) ds 6 L   ± j −  m7 c P2 . M14 and M15 form a circuit to turn off M15 when Vout < VTP13 (negative) Cc : compensation. Three poles and one zeros.18 CHUNG-YU WU +V DD M4 M6 M15 M1 M2 Vout M13 M7 M14 M15 M8 -V SS CC M5 * M13.

19 + V DD BIAS4 CHUNG-YU WU ML3 M L7 C C3 M5 M10 M11 M L10 BIAS3 ML11 M H4 MH5 M L6 M15 M12 M1 M2 M14 M L9 M8 M9 CC1 M H9 M16 M7 MH10 BIAS2 M L1 MH1 M H2 ML2 MH8 ML8 M 17 MH6 MH11 C C2 MH7 ML4 ML5 M3 M4 M6 M 13 BIAS1 M H3 .VSS TABLE I Component Sizes M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 400/15 400/15 150/10 150/10 100/15 150/10 150/10 300/5 300/5 300/10 300/10 1200/10 600/10 200/5 200/5 600/6 600/6 MH1 MH2 MH3 MH4 MH5 MH6 MH7 MH8 MH9 MH10 MH11 Cc1 Cc2 Cc3 48/10 50/10 500/15 300/6 300/6 200/5 250/15 700/6 15/6 10/15 20/15 20pf 4pf 4pf ML1 ML2 ML3 ML4 ML5 ML6 ML7 ML8 ML9 ML10 ML11 48/6 50/6 300/15 150/5 100/5 300/6 100/15 400/5 5/5 5/15 15/15 .8 .

1V 93dB 91dB 76dB 60dB 102dB 89dB 75dB 53dB 1. Ref.: IEEE JSSC .2MHz CHUNG-YU WU x ó 12. .3V -5.1200-1205.5V/ìs +3.5V 1000 mils2 Output Swing (RL=200Ù) PSRR+ at DC 1 10 100 PSRR1 10 100 kHz kHz kHz kHz kHz kHz at DC Slew Rate Input Common Mode Range Die Area (5ìm CMOS) Harmonic Distortion (3 kHz) Vin=3 Vp RL=200Ù HD2 HD3 -73dB -78dB Maximum Loads : 1000pF and 200Ù to ground.20 TABLE II POWER AMPLIFIER PERFORMANCE SUMMARY (First Revision) parameter Supplies Open-Loop Gain Bandwidth Power Dissipation Measured Results ±5V 93dB 1.7 mW 1. 1985. vol. pp. Dec. sc-20.8 .76mW ±3.

MX5 MX2 MX3 MX4. MX6 MR1 MA1.VSS Bias stage + V DD MB1 VB1 TABLE I TRANSISTORS’ DIMENSIONS TRANSISTOR MX1. * MX2 and MX3 Quiescent operation: ² MX2 and MX3 are on. Efficient Unity-gain CMOS buffer for driving large CL. MA3 MA5 MX7 MX8 W (µm) 225 75 30 90 6 45 450 36 600 240 L (µm) 3 3 3 3 21 3 3 3 3 3 * MR1 has a low W/L and is operated in the linear region ⇒ like a linear resistor. MA4 MA2. .21 CHUNG-YU WU 3. High-drive OTA buffer VDD MX5 MA1 M A4 MX1 A V B1 Vin+ V B3 MA2 MA3 VinV B2 M A5 MX3 MR1 B MX8 M X2 Vout CL V B2 MX7 M B2 MR1 M B3 VB3 MX6 V SS MX4 MB4 .8 . ⇒ Keep VGSMX7 and VGSMX8 low to reduce dc power.

MB4 ↔ MX4. the current through MX2 and MX3. MB2 ↔ MX2. TABLE II BUFFER’S PERFORMANCE PARAMETER Supply V oltage Supply Current V offset V oltage Gain F3dB (CL=100pF) Gain Peaking RoCL CMRR Input CM Range SR (CL=5nF) MEASURED VALUE ± 2. MR2 ↔ MR1.00 V/V 6 MHz 0. In the quiescent case.4 dB 330 Ω 80 dB ± 1. : stable.8 .22 ⇒ Provide a low-impedance level at node A and B.5 V 285 µA < 10 mV + 1.00 V/V 8 MHz 0 270 Ω 84 dB ± 1.e. * RBIAS controls the current through MB2 and MB3.0 V/µs Tsettling (to 1%) 3. CL ≥ 100pF and RL ≥ 10 kΩ CL=5000pF ⇒ f ≈ 100kHz.7 V ± 1.5 V 270 µA 5 mV + 1. MB3 ↔ MX3. VB = VA because of MR1 ⇒ MX8 on. of MX7 and MX8 can be avoid * If Vin << 0 MX3-MX6 are turned off and MX1 and MX2 are on ⇒ Node A has a high voltage ⇒ MX7 off.9 V/µs SPICE ± 2. CHUNG-YU WU The low-order poles created by the Miller cap. ⇒ i.8 V ± 0. MB1 ↔ MX1. * In the bias circuit. VGSMX1 ≈ VGSMX7 and VGSMX4 ≈ VGSMX8 ⇒ The current in MB1 and MB4 controls that in MX1 and MX4 and MX7 and MX8.9 µs 4 µs . Characteristics: 3 µm CMOS area: 100mils2.

June 1986. The correlated double sampling (CDS) method b. a. sc-21.8 . Possibly too large chip area. pp. 2) Use buried channel devices Not a standard technology.: IEEE JSSC. vol. CDS method Vn2 + Vn 2 VIN ∑ - a VOUT S/H f V neq12 VIN V neq12 a VOUT f ⇒ Noise reduction b. Chopper stabilization method .23 Input Noise Density F = 1 kHz F = 50 kHz CHUNG-YU WU 270 V / H Z 70 V / H Z NA NA Ref. Low-noise chopper-stabilized OP AMP Techniques for the reduction of 1/f noise: 1) Use large device geometries. 3) Transform the noise to a higher frequency range So that it does not contarninate the signal. The chopper stabilization method a.464-469. § 8-4 Advanced Design Techniques on Fully differential type CMOS OP AMPs 1.

Disadvantage: . Improvement of PSRR 2.24 CHUNG-YU WU SIN Vn2 +1 f Vn2 VIN + + f -1 - a1 - a2 VOUT Signal f Noise f Vneq 2 VIN Vneq 2 + f f - a1 + - a2 VOUT f * If the chopper frequency is much higher than the signal bandwidth. the 1/f noise in the signal band will be greatly reduced. Example: Fully differential class AB chopper stabilized OP AMP with DCMFB circuit.8 . Major advantage of fully differential OP AMPs: 1. double the output swing 4. Reduction on the sensitivity to clock and supply noise. Improvement of dynamic range 3.

Additional design complexity 3. mainly due to interconnection 2.5 3. + V DD Vcm+ M29 M13 M9 M10 M14 M30 M17 V+ M25 M21 M22 M26 M18 M43 M5 M1 M2 M6 M44 M45 V- M46 Vo+ M33 M39 M35 M47 M49 M51 V df C3 M53 M7 M3 M4 M8 M48 VoM34 M40 M50 M52 M36 M54 M55 M19 M23 M27 M56 M28 M24 M11 M12 .1. Larger area.5 17. Increase power dissipation.5 3.5 3.5 3.5 7 7 L(um) 3. C1-C4 : DCMFB circuit Device M1 M2 M3 M4 M5 M6 W(um) 25 25 25 25 25 25 L(um) 3 3 3 3 3 3 Device M19 M20 M21 M22 M23 M24 W(um) 7 7 17. M47-M54: the input chopper and the output chopper.5 3.5 3.5 3.5 8 .VSS M16 M32 M38 M42 M20 C2 C4 C1 VcmM41 M37 M31 M15 M43-M46. M29-M42.25 CHUNG-YU WU M7 M8 25 25 3 3 M25 M26 3.5 3.5 .

5 3. the faster the settling response. the higher the 2nd pole frequency.5 17.K.5 3.5 3.5 3.5 M27 M28 M29 M30 M31 M32 M33-M34 M55 M56 3 3 12 12 16 18 7 7 7 7 7 3.5 3.5 3.5 3. +VDD IO CC M2 M1 -VSS TWO-STAGE +VDD IO IO V + O CL - VBIAS CGS Vin -VSS M2 CL Vin M1 CP SINGLE-STAGE CASCODE DOMINANT AND NONDOMINANT POLE LOCATIONS FOR THE TWO-AND SINGLE-STAGE AMPLIFIERS Dominant pole location Two-stage amplifier One-stage amplifier 1 ro C c g m ro 1 ro C L g m ro Nondominant pole location gm CL gm Cp In general.sc-21.5 3. has a faster settling behavior. ⇒ Single-stage cascode amp. ⇒ simple 2-stage or single-stage OP AMP. .5 3.5 3.8 .1986 2. Fully differential folded cascode amplifier(National Semiconductor) For internal OP AMPs.5 17.5 3 3 3 Ref: IEEE JSSC vol.26 CHUNG-YU WU M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 10 10 4 4 17.5 7 7 17.5 3.5 3.5 3. pp. high output impedance is O.57-64 Feb.

+VDD + Vin CL -V out + CL VBIAS CMFB -V SS CMFB: Common-mode feedback circuitry 3. High-performance micropower fully differential OP AMP. Simplified schematic of the class AB amplifier: A M12 M17 M20 BIAS3 M5 Iin(+) M1 M2 M6 I in(-) OUT(-) M7 M3 I M10 M9 A -VSS I1 I2 M4 I M8 BIAS2 BIAS1 +VDD M11 M14 M16 OUT(+) M19 M18 BIAS4 M15 M13 .

27 CHUNG-YU WU +V DD M17 M20 BIAS3 Iin(+) OUT(+) 4µA 3µA 2µA 1µA -400 -200 200mV 400mV M12 M5 M1 I2 M6 M8 BIAS2 I M9 M13 M15 Iin (-) OUT(-) I class AB M7 I2 M4 class A I − 1µA − 2µA V in -VSS Active portion of the amplifier for a positive input signal.8 . Detailed schematic of the entire amplifier without CMFB: +V DD M11 M23 M17 M20 M22 M5 OUT(+) Iin(+) M7 M3 M 60A M18 M10 M21 M9 -VSS M13 M25 I2 I1 M4 M30 M15 M1 M2 M6 Iin(-) M8 OUT(-) M27 M26 M16 M12 M14 M19 M24 .

VGS 9 = VGS13 = VGS15 V DS13 = VGS 30 − V GS9 Set VDG13 = −VTH ⇒ VGS 30 = 2VGS 9 − VTH Design ( W )30 .8 .28 CHUNG-YU WU * NMOS dynamically biased current mirror: I30 M30 10 10 OUT M 15 40 10 I9 M9 40 10 M 13 40 10 . such that VGS 30 = 2VGS 9 − VTH L ⇒ M 13 is always sat.VSS If I 9 = I 30 . at the edge of the linear region. ⇒ Output swing↑ * Dynamic CMFB is used. AMPLIFIER DEVICE SIZES DEVICE M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 Z(μm) 180 180 140 140 150 150 200 200 22 22 L(μm) 6 6 6 6 6 6 6 6 10 10 .

1122-1132.5 V from Supply« olts 300 mils 2 «inferred from filter measurement Ref: IEEE JSSC.29 CHUNG-YU WU M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 M27 M30 29 29 22 29 22 29 29 22 22 29 20 6 28 6 20 6 28 6 7 7 10 7 6 6 7 10 6 6 9 12 6 14 9 12 6 14 AMPLIFIER SPECIFICATIONS CORE AMPLIFIER SPECIFICATIONS (0-5 V Supply) olts 100μW Quiescent Power Dissipation DIFFERENTIAL GAIN UNITY GAIN FREQUENCY NOISE OUTPUT SWING AREA >10. vol.000« 2 MHz« 140 nV/ Hz 1KHz 50 nV/ Hz white 0. Dec. 1985 . pp.8 . SC-20.

sc-20 .1985 .30 CHUNG-YU WU 4. Ddec.vol.VSS M17 M19 MC12 MC11 100µA 100µA MC1 MC2 MC4 BIAS MC5 M8 5µ A M10 MC6 MC7 M12 Characteristics: Technology Open loop gian CMRR Area : 5um. P-well CMOS.3mw power supply : ± 5V Ref: IEEE JSSC .8 . pp.1103-1112 . : 1180 : 61db : 290 mils2 unity-gain freq : 10Mhez power consumption : 2. Fully differential class AB OP AMP with CMFB circuit + VDD M18 M20 BIAS Vin Vout+ M2 M6 M3 M14 BIAS M4 BIAS M13 MC17 M11 MC16 M1 M7 M5 M16 M15 BIAS Vin+ VoutMC15 MC14 BIAS 5µ A M9 . double-poly cap.

6. Dec 1990.High-frequency behavior .8 .25.Gain boosting 1) Cascode gain stage with gain enhancement +VDD V o Vref + _ Aadd M2 Cload Vi M1 -VSS Rout = [g m 2 ro2 ( Aadd + 1) + 1]ro1 + ro 2 Atot = g m1ro1 [g m 2 ro 2 ( Aadd + 1) + 1] Aorig = g m1 g m2 ro1ro 2 2) Repetitive implementation of gain enhancement +VDD V o M2 M4 M6 M8 M1 Vi M3 M5 M7 -VSS 2. vol.1379-1384.31 CHUNG-YU WU § 8-5 Recent Design Examples of CMOS OP AMPs § 8-5. no. pp.1 Fast-settling CMOS OP AMP for SC Circuit with 90-dB DC Gain Reference : IEEE JSSC. 1.

Aadd and M2 forms a close loop with the dominant pole of ω 2 and the second pole at the source of M2. Rout and Cload.32 CHUNG-YU WU gain (log) Atot gain enhancement = Aadd(0) +1 ω3 : Upper 3-dB frequency of Aorig ω5 : Unity-gain frequency of Atot ω2 : Upper 3-dB frequency of Aadd ω4 : Unity-gain frequency of Aadd ω1 : Upper 3-dB frequency of Atot ω5 : Unity-gain frequency of Aorig Aadd Aorig ω (log) ω6 ω1 ω2 ω3 ω4 ω5 We want ω5 Aorig = ω5 Atot ω 2 > ω 1 => The bandwidth is determined by ω 1. => ω 4 > ω 3 But ω 4 < ω 5 for easy design of Aadd. That is:gain↑ without fu↓ . i.e.Settling behavior 1.e. 3. i. ω 6 The stability consideration requires ω 4 < ω 6 =>The safe range of ω 4 is ω3 < ω4 < ω6 * The repetitive usage of the gain-enhancement techniques yields a decoupling of the op-amp gain and unity-gain frequency fu.8 . Total output impedance Ztot Ztot= Z load // Z out Zload: impedance of Cload Zout: output impedance of the amplifier Z load g −1 m Z tot g −1 m Zout ≅ Zorig (Add+1) Normalized impedance (log) Z out g −1 m Z orig g −1 m Pole-zero doublet ω (log) ω1 ω2 ω3 ω4 ω5 .

where β is the feedback factor. must be smaller than the main close-loop time ω PZ 1 . CMOS OP AMP circuit . Of Aadd For ω > ω4 . Design technique for fast settling The time constant of the doublet. 1 . constant. Aaddd 1/β Aclosed-loop ω2 βω 5 ω4 ω5 ω6 ω (log) Safe range for ω 4 βω5 < ω4 < ω6 doublet 4. Aadd < 1è Z out → Z orig ω4 for Z out ω4 èA zero is formed at Z total = Z load || Z out èA pole-zero doublet is formed around èThe same doublet of Atotal 3. Of Aadd èthe same for Z out ω4 : Unity-gain freq. βω unity The safe range for the gain (log) ω4 .33 CHUNG-YU WU ω2 : Upper-3dB freq.8 .

2V 5. DC-gain Unity-gain freq.2V 5.1. Phase margin Power cons.33-44 Jan. no.0V - § 8-5.5ns Off 46dB 120MHz 16pF 63deg 45mW 4.: IEEE JSSC vol.34 CHUNG-YU WU +VDD Vbp1 Vbp1 Vcm VinVin+ Ib Vout+ Vout- Vbn1 Vbn1 -VSS MAIN CHARACTERISTICS OF THE OP AMP Gain enh.2 1V Rail-to-Rail CMOS OP AMPs Ref.0V 61. 52mW 4. Output-swing Supply voltage Settling time 0.35. ∆V o = 1V on 90dB 116MHz 16pF 64deg.1% . 2000 . Load cap. pp.8 .

Usually mismatches cause negligible input current.p. Dynamic level-shifting current generator Vi.cm+IR Vi.cm=Vi.n.8 .cmi-IR * The input resistance over the entire voltage range is infinite and no loading effect or input current over the previous stage.35 1. Typical input stage for rail-to-rail amplifiers * Parallel-connected complementary * Operating zones for low VDD/VSS differential pairs. CHUNG-YU WU * Operating zones for extremely low VDD/VSS Dead region.cm=Vi. Both pairs are off. * The symmetrical topology ensures very high CMRR 1 ∆ R ∆Gm −1 CMRR = ( + ) RG m R Gm where Gm = ∆I / ∆ Vi .cm . 2.

M1B M2A. Rail-to-rail very LV CMOS OP AMP with input dynamic level-shifting circuit MAIN TRANSISTOR ASPECT RATIOS (IN µm) AND ELEMENT VALUES OF THE AMPLIFIER BASED ON COMPLEMENTARY PAIRS M1A.M2 M3.M2B M1.8 .36 CHUNG-YU WU Circuit implementation 3.M4 M5-M8 M9-M12 400/5 200/5 400/2 200/2 400/5 500/5 M15 R1-R4 RM CM I bn = I bp 700/2 30 KΩ 5 KΩ 10pF 10µA 40µA Io .

cm ≅ V ref Circuit implementation: 5. .(Vi.cm 2RGmA *Vi .p.dm Vi.cm ) I = G m Vx => Vi.p. p .cm ≅ Vref + Vi.dm = Vi. Input CM adapter CHUNG-YU WU + Vx = A[2Vref .37 4.cm is degraded by A and Vi .p.8 .p )] - = 2A(Vref − Vi.p + Vi. Very LV CMOS OP AMP with a single differential pair and the input CM adapter.

34.5dB 600/4 50/2 300/4 150/2 200/2 400/2 M7-M10 M11 R1-R2 RM CM Is=Ir/2 300/4 700/2 15KΩ 5KΩ 5pF 10µA §8-5.8 .9V/us 1.26 mm 2 208uA 70.Measured results Experimental performance of amplifiers(Vsupply=1V .3 1.5Vpp@40kHz Vni(@1KHz) Vni(@10KHz) Vni(@1MHz) CMRR PSRR+ PSRR0. 248-252.2.5V High Drive Capability CMOS OP AMP Ref. 1999 .2µm CMOS.M2 M3-M5 6.technology:1.1dB 0.5dB 2.8V/us 1V/us -54dB -32dB 267nV/ Hz 91nV/ Hz 74nV/ Hz 62dB -54.81mm 2 410uA 87dB 1. pp. Feb.7dB -51.9Mhz 61° 0.: IEEE JSSC vol.38 CHUNG-YU WU Main transistor ratios(in µm) and element values of the amplifier based on a single input pair M1A M1B 1000/6 M6 1600/2 M2A M2B MA1-MA4 MA5-MA6 M2D M1.1Mhz 73° 0.5Vpp@1kHz) THD(0. CL=15pF) Parameter Dynamic-shifting amp CM adapater amp Active die area Ido(supply current) DC gain unity-gain frequency Phase margin SR+ SRTHD(0.7V/us -77dB -57dB 359nV/ Hz 171nV/ Hz 82nV/ Hz 58dB -56.4dB -52. no.

M6A and M7A off è Class A operation.7V -VSS CMR of the conventional NMOS-input differential pair is 0. IB1 . 7 + VTHn = 2VTHn + ∆V6. M8A sat M6A.39 +VDD 1. . IN+ VBIAS1 M1 M2 IN- M7 M5 M6 CMR is independent of supply voltage. IB2 Output section: M5A-M6A and M7A-M8A M5A.5V . For low input levels .5V 2. For large negative input signals. (W/L) 5A. 2 CMR = VTHn − ∆V5 ∆V : overdrive voltage. For large positive input signals. Output Stage +VDD M6A M8A M4A IB2 IB1 A OUT B IN M1A M3A M5A M7A M2A -VSS Input section : M1A-M4A . 2 = 2VTHn + ∆V5 + ∆V1.6 ~ 0. M7A off. But M7A remains cutoff.3-0. CMR=0. Folded-mirror differential input stage CHUNG-YU WU VCM ≤ VGS 6.8 .7A for low dc power dissipation and high drive. ID1A=IB1 è M3A and M5A OFF è VA → -VSS è M6A is turned on to supply most of the output current. 7 VBIAS2 M3 M4 OUT VCM ≥ VDSsat 5 + VGS 1. M7A supplies most of the output current.8A << (W/L) 6A. For VDD=1. The current of M8A is increased.

B 2 g m5 A. Overall LV CMOS OP AMP.40 3. Thus the gain of the gain stage M8 and M9 is approximately equal to CC1 .8 A (ro 5 A || ro8 A )C C 3 A.4 A g m5 A. CC 2 * The open-loop gain of the inner amplifier is   C  g Ain ≅ − C 1  m1 A.B The inner amplifier M8.M1A~M8A contributes the nondominant poles. CC2.8A(ro5A || ro8A )]}Cc g m1.2 sCc 2 g m1.2 sCc 1 g m1. 2 A 2 g m 5 A. The gain of M1-M7 at high frequency is .7{(gm8 ro8. 2 Cc 2 at high frequency. 4 A  Dominant pole : ωP1in ≅ Second pole : ωP 2in ≅ g m3 A . 2 C c1 Gain-bandwidth product: WGBW ≈ Hybrid nested Miller compensation: CC1. CC3A.8 . +VDD M15 M3 M6 M7 M8 M1 M2 IN+ M4 M5 MC CC2 M9 M1A M3A CHUNG-YU WU IBIAS M18 M6A M8A M4A M11 M12 CC3A CC1 OUT CC3B INM14 M16 M5A M7A M2A M13 -VSS Dominant pole : Wp1≈ 1 ro5. 8 A CL . * The two-stage OP AMP M1~M9 has a gain-bandwidth product of and the gain of g m1.M9.9 )2[gm5A. 8 A (ro 5 A ro8 A )  C  g   C 2  m3 A .

2 g m5 A.1709-1716.2 30/1. Setting 2C C 3 A.2 90/1.M5.M16 M15. 2 A ⋅ Component values : M1.8 A CL CL g m5 A. we have the unity-gain frequency equal to one half of the second-pole frequency.2 15/1.27.CC3B IBIAS VTH 60/2 20/2 15/2 90/2 5/1.M10 M4. 2 A C C 2 C C 3 A. we have C C1 = 2 g m1.M11.2 30/2 4pF 6pF 2pF 5uA 0.M2A. Dec.M12.M13 M6.MC CC1 CC2 CC3A.M3. pp. B or the second pole of the whole amplifier Design consideration : To obtain a maximally flat Butterworth response without gain peaking.8 .2 10/1. vol.M7 M8 M3A M4A M5A M7A M6A M8A M14. 2 g m1 A.M2.2 360/1.M9.8 A C C 2 = 2C C 3 A. B = 2 g m1. B = C C 2 .8V .2 120/1. ωGBWin = ωuin = 1 ωP 2 in 2 1 1 ωGBW = ωu = ωuin = ωGBWin 2 2 Reference : IEEE JSSC. 1992.41 CHUNG-YU WU C g Gain-bandwidth product : ωGBWin ≅ 2 C1 m1A .M1A.

08 mm 2 1.@1kHz CMRR @1kHz Offset Power Dissipation Die Size Technology Loading 75dB 75dB 95dB < 8mv 280μW 0.2μm CMOS 50pF || 500Ω . ∆V = 200mV 68dB 1MHz 65o 16dB 400ns 1 V/μs Slew Rate THD@1kHz Vout = 0.42 CHUNG-YU WU Experimental results: MEASURED MAIN PERFORMANCE Open-Loop Gain GBW Phase Margin Gain Margin Settling Time(0.5V RL=500Ω -57dB Closed-Loop Gain=20dB PSRR+@1kHz PSRR.1%).8 .

P-well (N-well) diffused resistor (Well or tub resistor) Thermal oxide Metal p+ n+ p n p+ * Compatible with CMOS metal-gate or Si-gate technology. Voltage Coefficient of Resistance (VCR)=100~500ppm/ oC Tolerance= ± 20% (Absolute) * High parasitic capacitance (n+-p junction cap. (Because of shallow junction) 2. * R□ = 20 ~ 100Ω /□ ( 100KΩ max) * Temperature Coefficient of Resistance (TCR) = 500~1500 ppm/oC. * R□= 1KΩ ~ 5KΩ /□ Large VCR .9-1 CHUNG-YU WU Chapter 9 Passive Components and Switches § 9-1 Resistors 1. Source/Drain diffused resistor Thermal oxide Metal n+ p * Compatible with NMOS and CMOS.) Piezoresistance error. metal-gate and Si-gate techniologies.

* Higher VCR . smaller tolerance. * The resistor implant can be combined with the depletion implant. Tolerance= ± 40% . * Difficult to eliminate the piezoresistance effect. Poly-Si resistor Vapor-deposited oxide Metal Poly Si I or II P Field oxide * Realizable by NMOS and CMOS Si-gate technologies. 3. metal-gate and Si-gate technologies. * Need an additional masking step.9-2 Tolarance= ± 40% (absolute) * Large depth and lateral spreading ⇒ narrow resistors are impossible. * R □ = 30Ω ~ 200Ω / □ (doped with the source/drain diffusion) * TCR ≅ 500~1500 ppm/oC . * R□> 500Ω ~ 1000Ω /□ . can be accurately controlled. Implanted resistor ( metal-gate technology ) CVD SiO2 n+ Implanted N+ p-sub n+ CHUNG-YU WU SiO2 * Compatible with NMOS and CMOS. 4.

* High frequency operation? CHUNG-YU WU φ i V1 R V1 − V2 R φ V2 V2 V1 C i= f C is the clock frequency of φ or φ i= C (V1 − V2 ) . PN junction capacitor * Well known and understood. metal-gate and Sigate technologies. * Non-conventional material may be involved. * Nonlinear capacitance with a large VCR. * Fully isolated with smaller parasitic capacitance. * Si-Chromium resistor or Mo resistor. metal-gate and Si-gate technologies. ² Version I :Poly-I resistor ² Version II:Poly-II resistor ² ² Version III :Poly-I and Poly-II distributed RC structure (please see the structure shown in poly to poly capacitor) 5. T R= T 1 = C fC ⋅C 6. * Need additional process steps. § 9-2 Capacitors 1. Thin-film resistor * Realizable by NMOS and CMOS. Switched-capacitor simulated resistor * Realizable by NMOS and CMOS . * Laser trimming is possible. .9-3 * Can be trimmed by laser or poly fuse.

MOS capacitor metal CHUNG-YU WU thin oxide p+ P-sub * Realizable only by NMOS and technology. 2.9-4 * Compatible with all MOS technologies. * TC=25 ppm/oC Tolerance=±15% VC=25ppm/V * Voltage-dependent capacitance accumulation depletion Co (Co-1 Cd-1)-1 3. ( Poly-fuse : blown with 10-20mA ) * Bottom plate pn junction parasitic capacitance ( ≈ 15% − 30% ) * VC of the capacitor ≈ -10ppm/V . * Can be trimmed by laser on poly-fuse. Poly (or metal ) to bulk silicon capacitor Poly Si Metal CMOS metal-gate n+ Thin thermal oxide P n+ Heavy n+ implant * Realizable by NMOS and CMOS poly-Si-gate (metal-gate ) technologies. + * Need an extra mask to define the heavy n implant as the bottom plate.

Interdielectric is poly-oxide. Metal to poly capacitor metal poly oxide poly CThick CB Thick oxide P-sub * * * * * Realizable by NMOS and CMOS Si-gate technologies. 5. * Smaller oxide capacitance per unit area ∵ Thick field oxide * The capacitor’s bottom plate must be always connected to the substrate.9-5 * TC ≈ 20-50 ppm/ C * Tolerance ≈ ±15% 4. Poly to field implant region capacitor poly-Si o CHUNG-YU WU field oxide n+ p+ substrate p-sub * Realizable only by NMOS and CMOS Si-gate technologies with the field implant. CVD oxide is not good as capacitor dielectric . * Low quality dielectric oxide. Poly fuse trimming is possible. Extra mask to define the ploy-oxide pattern.

IEEE Proc. 1983. Thin thermal oxide Poly 2 Poly 1 Field oxide P * Realizable by NMOS and CMOS double-poly technologies. poly to poly capacitor Vapor deposited oxides Co CB CThick poly to substrate parasitic cap.9-6 CHUNG-YU WU ∵ hysteresis in Q-V due to dielectric changing and relaxation. ⇒ CThick exists ⇒ parasitic capacitance * VC=100ppm/v.. Allstot and W. TC=100ppm/oC 6. Resistors : Absolute tolerance ≈ ±20% ~ ±40% Matching or ratio tolerance ≈ ±0. the top metal layer must be larger than the poly oxide layer. Jr. § 9-3 Tolerance Considerations. vol-71.1% ~ ±10% Capacitors: Absolute tolerance ≈ ±15% Co CB . C Black. pp967-986. * For reliability consideration. J. * VC=100ppm/v TC=100ppm/ oC * Double-poly ⇒ EPROM or E 2 PROM are available ⇒ may be applied in trimming * The poly2 area may be smaller than the poly-oxide area ⇒ small CThick General Reference: D.

9-7 Matching or ratio tolerance ≈ ±0. = − ≈ − W R L Rs L W ∆L ∆R ∆W If L is large ⇒ ≈0⇒ ≈ L R W R = Rs  δ ρ  2  δL  2  δ W  2  δXt  2  ρ L  +  +  R= .01% ~ ±1% Resistors : L ∆R ∆L ∆Rs ∆L ∆W .minimum perimeter leads to minimum telerance. σ ∆ C = C ⇒ σ ∆C C square( L=W ) < σ ∆C C For the same WL . Circular shape? CASEII : Ratio or Matching tolerance under geometry random variation . σ R =   +     Xt W  ρ   L   W   Xt     δW = for long resistor W * Long resistor pattern is recommended in precise resistors. Capacitors: ε ∆C ∆W ∆L ∆ε si02 ∆t ox C = sio 2 WL = + + − t ox C W L ε sio 2 t ox edge effect Oxide effect CASE I : Absolute tolerance ∆C ∆W ∆L = + (if W and L are small or ∆εsio 2 and ∆tox are C W L neglible) If ΔW and ΔL are independent with σ ∆l = σ ∆w = σ l σ ∆C = σ l C 1/ 2 CHUNG-YU WU 1 1 + 2 (random variation) W2 L 2 l is minimum d non − square( W ≠ L ) Assume L=W=d .

both conditions(1) and (2) can be satisfied ⇒ Ratio tolerance ↓ .e.9-8 α≡ C1 W1 L1 dα dC1 dC2 = . σ dα α σ = l d ⇒ σ dα α min =2 σl if L1 = W1 = αd d (1) square versus square CASE III : Ratio tolerance under the uniform undercut effect Uniform undercut is not a random variation. L2=d W2=d ∆x ∆x W1 L1 α≡ α actual = C1 W1 L1 = 2 C2 d W1 L1 − P1∆x + 4∆x 2 W1 L1 − P1∆x ≅ 2 d 2 − P2 ∆x + 4 ∆x2 d − P2 ∆x ∆α ∆x P ≅ 2 ( P2 − 1 ) α d α P 2( W1 + L1 ) IF P2 = 1 ⇒ ∆α ≅ 0 i. 4d = α α So W1 L1 = αd 2   2( W1 + L1 ) = 4 dα  ⇒ W1 = d( α − α 2 − α ) ; L1 = d ( α + α 2 − α ) σ dα = α (2) σl 2 α >>1 σ l 6− ≅ 6 d α d If α = 1 . = − C2 W2 L2 α C1 C2 2 2 2 1 CHUNG-YU WU σ dα = σ dc + σ dc α c1 = σl c2 1 1 1 1 2 + 2 + 2 + 2 L1 W1 L2 W2 L + W1 2+ 1 ( αd )2 2 2 For W2=L2=d.

9-9 CASE IV : Ratio tolerance under edge and oxide effects Take α = 1 ⇒ unit capacitor array D D D C2 D D D D C1 D D D D : Dummy capacitor pattern D D D D D D C1 =4 C2 CHUNG-YU WU * Centralized structure to avoid the oxide effect. * Ratio tolerance can be ±0.06 % Similarly. MN on ⇒ V2=V1 full transimission . The NMOS switch 1) If Vφ≥V1+VTHN . for resistors. we have R1 dummy resistor R2 R1 R2 dummy resistor * Ratio tolerance can be ±0. * Dummy capacitor may be omitted to save area.25 % § 9-4 The MOS Switch 1.

Vφ n+ A CHUNG-YU WU 2 V2 p If Vφ = 0V for a very long time.5V ⇒ V2= 5V 2) If V1 + VTHN > Vφ > VTHN . Vφ= 8V. VTHN = 1. M N off Node 1 or 2 may be floating ⇒ V1 or V2 will be gradually charged or discharged by the leakage current in MOS or PN junctions. V1 = 5V . V A → 0V by the n + p junction leakage current ⇒ Not allowable in circuit design * When the switch is turned on or off.5V 3) If Vφ < VTHN . the charging or discharging current is nonlinear ⇒ Nonlinear resistor Capacitance feedthrough effect: . M N on V 2 = Vφ − VTHN Example: Vφ = 5V .10 Vφ Mn 1 V1 VBS Example: V1= 0V.5V (under substrate bias). VTN =1. VBS = 0V ⇒V2 = 3.9 . Vφ= 3V ⇒ V2= 0 V1= 5V.

Example: Vφ = 0V .1V Compensation circuit: Vφ Vφ − 2 Vφ 1 2 1 2. C 2 = 2 PF. The PMOS switch VDD * Can pass high voltage without offset.9 . VDD = 10V .02PF. VDD = 5V = V1 ⇒ V2 = 5V Q 1 = source and VGS = 5V .11 Vφ Cgs 1 C1 Vφ : VDD → 0 V1 f ≈ V1i −VDD V2 f ≈ V2 i − VDD Cgs Cgs + C1 C gd Cgd + C1 CHUNG-YU WU C Cgd 2 C2 + Vout error voltage Example: C gd ≈ 0. error voltage ≈ 0.

5V = 3. V1 = 0V . * If V1 = 5V = Vφ . Example: Vφ = 0V .5V ⇒V2 f ≈ 1.5V → V2 = 5V : Only PMOS If V1=0V.5V ≠ 0V 3. V 2 i = 5V . V2i=5V V2 = 5V → V 2 = 1 .5V → V 2 = 0V : Only NMOS .5V : NMOS and PMOS V2 = 3.V = 0V .9 .12 * Can’t pass low voltage completely.5V φ _ V 2 = 0V → V2 = 5V − 1.VTN =| VTP |= 1. φ − * Nonlinear Cgs and Cgd and the delay between Vφ and V make the compensation of the feedthrough effect quite φ − complicated.5V : NMOS and PMOS V 2 = 1.VDD = 5V . if the delay between Vφ and V is zero. VTP = 1. The CMOS switch Vφ CHUNG-YU WU 1 VDD 2 Vφ * Full transmission * The clock feedthrough effect can be greatly compensated.

of T.(2)  dT  mVthermo Substituting (2) into (1) . µ = CT − n I S : Reverse saturation current of a BJT A : Area of a BJT QB : Base minority carrier charges D : Average diffusivity of carriers C:Constant.-indep. indep..10 . of T. indep. of T. ⇒ V BE (on ) = VGO − Vtherm [(γ − α) ln T − ln( FG )] In general. ⇒ VBE ( on) = mV therm ln[ I 1T −γ F exp(VGO / Vtherm )] F : Constant . ni 2 = ET 3 exp( −VGO / Vtherm ) E : Constant. the output voltage Vout is a sum of V BE (on ) . of T. exponent. we have . of T. n:Temp.1 CHUNG-YU WU Chapter 10 CMOS Bandgap References §10-1 Basic Principles of Bandgap References (BGR) VBE ( on ) = mV therm ln( I1 / I S ) I S = qAn i 2 Dn / QB = Bn i 2 D = B ' ni 2T µ where B and B ' are constants. and KVtherm with a weighting factor K such that Vout is nearly indep. indep. γ =4−n I1 = GT α where I1 is the collector current and G is a temp. V BE (on ) + KV therm = V out = VGO − mV therm (γ − α) ln T + mV therm [ K + ln( FG )] …………(1) dVout dT =0= T =TO mV thermo [K + ln( FG )] − mVthermo (γ − α) ln TO − mVthermo (γ − α) + d VGO TO TO TO dT TO  d  ⇒ K + ln( FG ) = (γ − α) ln TO + (γ − α) −  VGO  ⋅ …. constant. indep. VGO : Energy gap.

2.093V 21.0259) − = 1.16 − 14.02 × 10 −4 ⋅ TO =− + TO + 1108 (TO + 1108) 2 ⇒ Vout = mV therm (γ − α)(1 + ln 2 7. I S1 I 1 .2 CHUNG-YU WU VGO = 1.16 + 2.02 × 10 −4 ⋅ TO2 ⋅ T + (TO + 1108) 2 TO + 1108 If γ = 3.02 × 10 −4 ⋅ T 2 TO ) + 1.06 × 10 −4 (298) 2 7.02 × 10 −4 ⋅ T 2 T + 1108 10 . m = 1. * Q4 also serves as a start-up circuit.2(0. R2 / R1 and I S 2 / I S 1 to give a suitable K And Keep I ≅ I 2 to obtain I B 2 ≅ I B 3 and I3 I S 3 I3 = to obtain V BE1 = V BE 3 .04 × 10 −4 TO (TO + 1108) − 7. *Vout = I 2 R2 + V BE 3 I2 = I3 if I B 2 = I B 3 I3 =  I I  V BE 1 − V BE 2 1 = mVtherm ln( 1 ) + ln( S 2 )  R3 R3 I S1   I2  I  + ln S 2  I   S1      ⋅ Vtherm     I1 +Vcc I Q4 R1 I2 R2>>R1 + R2 + Q3 V out Q1 R   R  Vout = V BE 3 +  2 mln 2  R3   R1   + - VBE1 VBE2 - + Q2 VBE3R3 - I1 / I 2 = R2 / R1 If V BE1 = V BE 3 Adjust R2 / R3 .02 × 10 −4 ⋅ TO 2 d V =− dT GO T =T (TO + 1108) 2 O 14.16 − − T T + 1108 14. TO = 25 O C ⇒ Vout (T ) T =25 O C = 1.Vout T d = V GO + mVtherm (γ − α)(1 + ln O ) − T V GO T dT 7.04 × 10 −4 ⋅ TO 7.04 × 10 −4 ⋅ TOT 7.α = 1.02 × 10 −4 (298) 2 + 298 + 1108 ( 298 + 1108) 2 §10-2 Bipolar Bandgap Reference Widlar bandgap reference *Feedback element Q4 is used to force Q3 on.

10 .Q2:Substrage-well-source/drain parasitic vertical BJTs I V BE = mVtherm ln E IS V REF = ±{VBE 1 + R2 R I R + R2 Vtherm (ln 2 + ln s2 ) + VOS [ 3 ]} R3 R1 I s1 R3 .1 CMOS BGR via BJTs and Resistors Version 1: N-well CMOS.Vos+ + CMOS OP AMP R1 I1 R1 I1 R2 I2 -Vos + + CMOS OP AMP - _ + R3 VREF - _ VREF R3 + Q1 Q2 Q1 Q2 -Vss -Vss Q1. Negative VREF §10-3. V1 Q2 R2>> R1 R2 VBE(on) + V2 Cut-in State 2 1 3 ON State 4 §10-3 CMOS Real Bandgap Reference (BGR) Version 2: N-well CMOS. positive VREF I2 R2 .3 CHUNG-YU WU V2 R1 V1 Q1 R3 The operating point 4 is the desired operating point =>Need a start-up circuit.

26V × 300 o K VOS : 3. è ∆V BE due to rb and βis large.4 CHUNG-YU WU I1 △VBE + I2 rb/A â1 Q1 rb â2 Q2 ∆ VBE = Vtherm ln A + Vtherm ln I2 + Vtherm I1 -Vss 1 β1 I I + rb ( 2 − 1 ) ln 1 β2 Aβ1 1+ β2 1+ If â1.5KΩ.poly resistors well resistors Both transistors are in the active region Error analysis: 1. â2 are not large enough or rb is too large. R3 + R 2 R R I ) + 2 Vtherm (ln 2 + ln s 2 R3 R3 R1 I s1 1 β1 R I I ) + 2 rb ( 2 − 1 )} + ln 1 R3 β2 Aβ1 1+ β2 1+ V REF = ±{VBE 1 + VOS ( 2.Typical design values: I1=80μA I2=8μA R2 ≈ 0.6V R 60mV = 75 KΩ.R2. Error due to base resistances I 1 rI VBE 1 = Vtherm ln 1 + Vtherm ln + b 1 1 IS Aβ1 1+ β1 10 . R3 = = 7.5KΩ 8 A μ 10 8μA Large resistanceèuse well resistors R1.R3: n+/p+ diffusion resistors n+ .Error due to input offset voltage Vos R Vos =10mV. VOS (1 + 2 ) ≈ 10VOS = 100mV R3 TC error due to 1 VREF d VREF = dT (1 + R2 )VOS R1 10 × 10mV = = 264 ppm / o C VREF T0 1.Error due to Bias current variation VBE 1 = Vtherm ln I1 V ln A = VThrem ln therm (R3=R1) I S1 R I S1 . R1 = 2 = 7.

or base current .TC Error due to Base Resistance I ∆V BE = rb 2 β2 TC error = (1 + R2 rb I 2 ) R1 Vref β2  1 drb 1 dI 2 1 dβ2   r dT + I dT − β dT  b 2 2     Example : rb = 2 K Ω .Error due to base current Base current cancellation technique *To compensate for the different between the collector.. TC of rb = 1000 ppm / O C .V ln A R (T ) = V therm ln therm + Vtherm ln 1 O R1 (TO ) I S1 R1 (T ) If R1 is indep... 4.. we still have PTAT 2 term The PTAT 2 term can be cancelled via curvature compensations. I 2 = 30µA . emitter. TC of β = 7000 ppm / O C ⇒ TC = –8. of T ⇒ V BE = V therm ln If R1 depends on T ⇒ V BE = V therm ln V BE = V BE  1 dR − Vtherm ⋅   R dT  I1 = I 2 10 ..6 ppm / O C 5. β = 150 .   PTAT PTAT 3 If R is only linearly dependent on T.5 CHUNG-YU WU Vtherm ln A R1 (TO ) I S1 V therm ln A R (T ) + Vtherm ln 1 O R1 (TO ) I S1 R1 (T )  (T − T )2 O   PTAT ideal TO 2   (T − TO ) − Vtherm  1 d R   2 R dT 2 T   O PTAT 2  1 dR + V therm  2  2 R dT  PTAT PTAT 3 TO  (T − TO )2 − .

pp634-640. DEC. pp1014-1021.Solid-State Circuits.2 Improved structure 1.10 . vol.Solid-State Circuits. 1984 The circuit to obtain VREF from a BGR +VDD Q1 Q2 R3 _ + R1 R2 VBGR + _ R5 §10-3. R4 VREF=VBGR(1+R4/R5) VBIAS ãN M1 M2 Vo=VR1 +VR2 +VBE3 *Better matching KT VR1 = VBE1-VBE2= ln(αγ ) q KT Vo=VBE3+ [ln(αγ )] (1+R/R) =>Bandgap Reference q .SC-19. 1983 2. IEEE J .6 Version 1: +VDD I1 IB IB I1 IB IB IB -VSS -VSS IB Version2: +VDD IE CHUNG-YU WU Ref:1. DEC. vol.SC-18.IEEE J .

CHUNG-YU WU VBIAS M4 M3 M2 M1 3.10 .7 2. M110 .

10 .8 CHUNG-YU WU M110 +VDD M105 M104 M103 M111 M109 M110 M108 M112 M101 M102 M106 M107 M3 M1 -Vss M2 M6 M4 M5 .4.

5v V oltage T=25°C NMOS Inputs VTN ≤ 1.95v 1. vol.1151-1157. pp.Solid-State Circuits.0V 1. 1985 Structure of a lateral BJT in CMOS: .Low Power Supply Circuit: M101 M102 -Vss *Low driving capability Power supply limits: Low Possible Bandgap reference Topology 1 2 3 5 PMOS Inputs VTP ≤ 1.95v 1.5v §10-3.90v 2.2v 2. SC-20.0V 2. DEC.3 CMOS BGR via lateral Transistor Ref:IEEE J .5v 1.10 .9 CHUNG-YU WU 5.

A. 10 . metal sub V oltage reference via LBJT: Conceptual circuit: Symbol: Q2 Q1 A:Current comparator VCC:V oltage-controlled current source G:A negative voltage is applied to cause accumulation. Advantages:(1)The offset of the amplifier A has a negligible effect on VREF (2)Simple structure.10 CHUNG-YU WU sub B. Purpose of VCC : To provide a current path for IR1>>IB1.IB2 .

42 mm2 ( white) .R3.2285V .11 CHUNG-YU WU +VDD +VDD + + Vref _ -Vss 1:A Vref _ -Vss * Low supply voltage * Low current gain in A * R2 is trimmable * High supply voltage. 560nV 1 .2V 79ìA 316nV Hz 60dB 3.=>higher current gain R4.T3:VCC R3: To keep T3 from quasi-saturation R4:To sense the output voltage and transform it into the collector current of T3. Minimal supply voltage Supply current Noise spectra PSRR(100Hz) Load regulation (ÄV out/Iout) Chip area standard deviation :150ìV 2.10 . Measured results: VREF mean :1. * Two source follwers+one emitter follower in(A) current amp.1KHz ) Hz f ( . * All resistor are polyresistors * Low output impedance.6ìV/ìA 0.

of Analog ICs and Signal Processing. Kluwer. pp. 207-215.1283-1285. vol. Experimental results: VREF 1.1KHz) Hz f PSRR(100Hz) 77dB -Vss Load Regulation 4. sc-20.12 CHUNG-YU WU +VDD 500nV Hz 1µV ( white) : : 1 ( . J. 1985 §10-4 High-Precision Curvature-Compensated CMOS Bandgap Voltage References (BVR) Ref: Int.2281V (mean) 350ìV (ó) Minimal Supply 1. Solid-State Circuits.High PSRR BGR: * R1.7V Supply Current 20ìA Noise Spectra 10 . pp. Dec.R2 may be p-well resistors and PSRR still high.18 mm2 Curvature-Compensated BGR: Ref: IEEE J. Type A structure The circuit stricture of the proposed BVR (Type A) . 1992 1.1mv/ìA (ÄVout/Iout) Chip area 0.

13 Vout = VBE 3 + I 3 R2 = VBE 3 + r3 2. Type B structure . Type A structure R2 kT ( ln A* + ∆Vsg ) R1 q CHUNG-YU WU Cst 3.10 .

10 . Type C structure The cascode structure of BVR (Type C): CHUNG-YU WU The variation of △Vsg versus temperature .14 4.

15 CHUNG-YU WU The simulated output voltages versus temperature in Type A and Type A BVR The variation of △Vsg versus MOS channel length in Type A BVR .10 .

9KÙ(external)] .10 .16 CHUNG-YU WU The Spice simulated output voltages versus temperature in Type C BVR The measured output voltages versus temperature in the fabricared cascaded-structure BVR(Type C)[ 3.5 ìm CMOS technology . R1=1KÙ(external).R2=25.

7V PMOS VTHP = −1. * The built-in voltage V f of the diode → the current I 2b The thermal voltage Vtherm → the current I 2 a ( I 2 a + I 2b ) R → V ref < 1V 1.: IEEE JSSC.670~674.10 . 0.Schematic of the proposed BGR I1 Vf1 R3 I1a I1b R1 I2 I2a Vf2 R2 I2b R4 I3 Native NMOS VTHI = −0.2V NMOS VTHN = +0.1963V ~ 1.25V Can’t be operated below 1V supply. pp.5 ppm/ oC -60 oC ~ +150 oC 5V~15V * At 25 oC. vol.34.1965V 5V ~ 15V 2 * 2 mil .17 CHUNG-YU WU * Average temperature drift 5. average voltage drift 25ìV/V V out=1.0V .8 mW at 5V §10-5 CMOS Bandgap Reference with Sub-1-V Operation Ref. May 1999 Concept: * Convertional BGR V ref = 1.

I1b = I 2 b dV f = V f 1 − V f 2 = Vtherm ln( N ) . N = 100 I 2a = I 2b = dV f R3 Vf 1 ∝ V therm ∝Vf R2 I 3 = I 2 = I 2a + I 2b R R4 V f 1 + 4 dV f R3 R2 V ref = R 4 I 3 = 2. Simulated V ref characteristics VDD .10 . *The control signal PONRST is used to initialize the BGR circuit when the power is turned on.18 CHUNG-YU WU *The diode is realized by the parasitic P + / n − well / P − substract BJT as * C1 and C 2 are used to stabilized the circuit. * R1 = R2 V a = Vb I1 = I 2 = I 3 and I1a = I 2 a .

8 ~ 1.Measured results: -0.Minimum V DD min V1 ≅ V s ≅ Vb − VTHI ≅ V f + VTHI ≅ V DD + VTHP = min V DD − VTHP ⇒ min V DD = V f + VTHI + VTHP ≅ 0.10 .3 conventional BGR proposed BGR CHUNG-YU WU VDD VDD * TC ≅ 60 ppm / O C 27 O ~ 125 O C V oltage drift (average) ≅ 600µV /V 2.0V 0.19 *V ref = 1.54 4.25V *V ref = 0.2 -0.2V~4V .84V 3.

Sensor. Audio..) Filtering and A/D Conversion Digital Processing Control D/A Conversion and Filtering Analog Output Analog World Digital World Analog World (Digital signal processing has better noise immunity than analog signal processing. 11..11-1 CHUNG-YU WU CH 11 Digital-to-Analog Converters (DACs) in CMOS Technology §11-1 Introduction 1..1 A block diagram of a typical signal processing system Digital Data Input Data Latches D/A Converter Output Sample and Hold Analog Output Control Fig.. Block diagram Analog Signal ( Video. 11.) Fig.2 Functional block diagram of a D/A converte .

. 0 ]− (2 N −1) (LSB) Vout VLSB (LSB) Ideal transfer response Actual transfer response Actual transfer response with Eoff(DAC)set to zero 1..0 ... N-bit resolution → 2Ndistinct analog levels.. b N : N-bit digital data input The signal change when one LSB changes is VLSB VLSB ≡ V ref 2N If in LSB unit. (2) Offset error: E off (DAC) ≡ (3) Gain error: E gain (DAC) ≡ [ Vout VLSB 1... Ideal DAC: Analog output signal Vout = Vref (b12-1+b22-2+ ---.... 1LSB= 3.. DAC performance specifications 1 2N (1) Resolution: The number of distinct analog levels corresponding to the different digital words.+bN2-N) Vref: analog reference signal b1 … … .. 0 ( LSB) Vout VLSB 0. 1 − Vout VLSB 0..11-2 CHUNG-YU WU 2.......1 Digital Data Input Bin Gain error Offset error o 0..

It includes the offset.11-3 CHUNG-YU WU (4) Accuracy absolute accuracy: The difference between the expected and actual transfer response. INL error is referred to as the maximum INL error.... gain..1 Bin .0 1. INL error (best-fit) and INL error (endpoint) Usually... and linearity errors. relative accuracy: The accuracy after the offset and gain errors have been removed... • effective number of bits • fraction of an LSB *12-bit accuracy ⇒ all errors<1 LSB ( (5) Integral nonlinearity (INL) error Vout ) 212 Definition: The deviation of actual transfer response from a straight line... ⇒ maximum integrated nonlinearity (INL) error *Accuracy units: •% of full-scale value. Vout VLSB (LSB) Best-fit straight line Transfer response without gain and offset errors (maximum) INL error (best-fit) Endpoint straight line (maximum) INL error (endpoint) 0.

5 LSB) (9) Sampling rate The rate at which sample can be continuously converted.11-4 CHUNG-YU WU (6) Differential nonlinearity (DNL) error Definition: The variation in analog step sizes away from 1 LSB.5 LSB * Maximum INL error < 0. Types of DACs (1) Decoder-based DAC (2) Binary-weighted DAC (3) Thermometer-code DAC (4) Hybrid DAC (5) Oversampling DAC . gain and offset errors have been removed) (7) Monotonicity: The output signal magnitude always increases as the input digital code increases.5 LSB ⇒ monotonicity * Many monotonic DAC may have a maximum DNL error>0.5 LSB ⇒ monotonicity (8) Settling time The time it takes for the DAC to settle to within some specified amount of the final value (usually 0. ( usually. * Maximum DNL error < 0. (Typically the sampling rate is equal to the inverse of the settling time) 4.

if 16RT > 2N Ri ( Ri = 200 Ω .1 Resistor-String DAC 1.into 16 voltage intervals H0-H15 L0-L15: To divide each of those intervals into 16 a-p subintervals * To insure maximum uniformity of step size. * For 8-bit DAC. Conceptual 8-bit resistor-string DAC.11-5 CHUNG-YU WU §11-2 Decoder-Based DAC §11-2. the error due to loading can be held to less than 1 LSB. linearity.2KΩ ) . i. Practical realization R0-R15 : To divide VREF + to VREF. REF+ S256 R R 255 RESISTORS R R S255 S254 S253 S4 R R S2 R S1 REF0 1 2 3 4 5 6 7 (DAC INPUTS) 8 To 256 DECODER S3 + _ DAC OUT 256 OUTPUTS 2.e. the resistance of the transmission gates should be made as large as possible ⇒ minimal loading. RT > 3.

11-6 CHUNG-YU WU 8-bit Resistor-String DAC (Multiple Resistor-String DAC) REF+ H15 n15 R15 n14 R14 n13 R13 n12 R12 n11 R11 n10 R10 n9 R9 n8 R8 n7 R7 n6 R6 n5 R5 n4 R4 H15 p15 o H14 p14 L0 L15 n H13 p13 L14 m 0 1 4:16 2 3 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 H14 H13 H12 H11 H12 p12 L13 H10 H11 p11 L12 l H9 H10 p10 L11 k H8 H9 p9 L10 j 0 1 4:16 2 3 H0 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H7 H8 p8 L9 i DAC OUT h H6 H7 p7 L8 H5 H6 p6 L7 g H4 H5 p5 L6 f H3 n3 R3 n2 R2 n1 R1 n0 R0 H4 p4 L5 e H2 H3 p3 L4 d H1 H2 p2 L3 c H0 H1 p1 L2 b H0 REF- p0 L0+L1 a .

Vout : ±2. * VDD = +5V. Ri Ri R i +16 R T 2 N ⇒ 2N R i ≤16R T occurs when L1=1 .5MHz. also by the operating speed of the output buffer.2kΩ = R T * The raw speed of the DAC is limited by the resistance of transmission gates a-p and the capacitance of the output node. the jump in step size can be held to less than 1 LSB if 16R T R i Ri − ∆R i R i +16R T Ri = = ≤ 1 16RT ≥ 2NRi.11-7 CHUNG-YU WU Subinterval Generation: 14R T's o Lo Transmissiongate resistor L15 n L14 m L13 L12 l L11 k L10 j L9 i + _ A RT Hi L8 h L7 g DAC OUT Ri+1 200 Ω Ri Ri-1 Hi L4 d RT L6 f L5 e R T=3.2KΩ L3 c L2 b L0+L1 a * Transmission gate size: 24µ /12µ →3. -VSS = -5V. * For 8-bit DAC.5V Maximum conversion rate 0 → full scale : 2.

11-8 CHUNG-YU WU §11-2.2 Folded Multiple Resistor-String DAC .

11-9 CHUNG-YU WU .

11-10 CHUNG-YU WU .

Multiplying DAC * All top plates are connected to the OP AMP input ⇒ To reduce substrate noise voltage injection. Multiplying DAC with bipolar input LSB MSB sign bit If bo = 0 ⇒ the signal Vin is positive ⇒ the same as 1. * Switched-induced errors are large.11-11 CHUNG-YU WU §11-3 Binary-Weighted DAC §11-3.1 Charge-Redistribution DAC 1. * offset cancellation 2. .

the MSB current source needs to be matched to the sum of all the other current sources to within 0. result in glitches which is most severe at the midcode transition. ⇒ not guaranteed monotonic. maximum Midcode glitches Transfer response Reference: IEEE Journal of Solid-State Circuits. General characteristics or features of charge-redistribution DAC: (1) The auto-calibration cycle can be performed to remove the effects of component ratio errors. pp.2 Weighted-Current-Source DAC (Current-Mode BinaryWeighted DAC) Conceptual circuit: 1. φ1. §11-3. (2) Good linearity and stability due to good linear capacitors. as all switches are switching simultaneously. * At the mid-code transition 011---1→ 10---0. ⇒ difficult for large bit number.11-12 CHUNG-YU WU If b0 = 1 ⇒ the signal Vin is negative.33.1998. φ2 positions are exchanged. (4) Suitable for medium-speed DAC with 6-bit resolution or below. Dec. (3) Too large capacitance ratio is required for high-bit DAC. Conventional structure * Simple circuit structure without decoding logic. such as charge injection and clock feedthrough. * Low-accuracy matching causes inaccurate bit transition ⇒ typical DNL plot as shown → * The errors caused by the dynamic behavior of the switches. n i =1 Vout = -Vin ∑ bi 2 −i 3. vol. . ⇒ contains highly nonlinear signal components ⇒ manifest itself as spurs in the frequency domain.1948-1958.5 LSB.

11-13 CHUNG-YU WU Conventional Weighted-Current-Source D/A Converter 2. CHUNG-YU WU 11-13 .

1. CHUNG-YU WU 11-14 .11-14 CHUNG-YU WU Improved Structure The Proposed 10-bit D/A Converter Reference: IEEE JSSC.635-639.) 2. Using Two-Stage Architecture: 32 master & 32 slave current sources (Occupied small chip area but cause tight matching requirement among master current sources. PP. Using Threshold-Voltage Compensated Current Sources to satisify tight matching requirement. June 1989. Only need local match & do not need global match.

11-15 CHUNG-YU WU Two-Stage Weighted Current Array D/A Converter CHUNG-YU WU 11-15 .

CHUNG-YU WU 11-16 . Conventional switched current source.11-16 CHUNG-YU WU I1 = K (W/L)(Va-Vth1)2 IN = K (W/L)(Va-VthN)2 (VthN-Vth1) may be as large as 80 mV due to the oxide thinning effect.

I2>>IC 2. M2 and MC are locally matched ⇒ I 2 ≅ K W VR1 L CHUNG-YU WU VR1 Switched current source with threshold-voltage compensation. 11-17 .11-17 CHUNG-YU WU I 2 = K W (Va − Vth 2 )2 L = K W ( VR1 + Vth c − Vth 2 + LcIc ) 2 L KWc 1.

(b) current sources with threshold-voltage compensation. .11-18 CHUNG-YU WU Spice Monte-Carlo simulation results for (a) Conventional weighted current sources.

11-19 CHUNG-YU WU To Coax Y Driver D5 YB Driver D1 A Vdd Y YB To Dummy Load A Vdd Vdd Vdd Y YB Y YB VR2 Vb IMSB-5 D10 x16 A Vdd VB VR2 Va IMSB Gnd x16 VR1 IMSB-1 x1 VR1 c VR2 Va IMSB-4 x1 VR1 c VR2 Va Vdd VR3 ILSB x1 VR2 Vb ILSB VR3 x1 VR2 Vb VR3 Driver A Vdd VB Two-stage weighted-current-source D/A converter with threshold-voltage compensated current sources. Driver D6 CHUNG-YU WU 11-19 .

(b) The SPICE simulated output waveforms of the input driver with high logic-threshold.11-20 CHUNG-YU WU CKs Din VB1 DB VB1 Vdd D out in VB1 out in VB1 Vss (a) (b) (a) The circuit. .

M2 . (b) 5-cell unit. Compact Symmetry M2 M2 M2 M2 Mc M2 Mc M2 Different layout arrangement for the devices M2 and Mc in each current source: (a) 4-cell unit.11-21 CHUNG-YU WU 16I 8I 4I 2I I I Symmetrical layout configuration of each 5-bit current array.

11-22 CHUNG-YU WU Differential linearity error of the D/A converter Integral linearity error of the D/A converter. .

DNL<±0. 4. . 2. 125MHz.23 LSB. 150mW. Two-step weighted current array 32 master.6 82.9 89.11-23 CHUNG-YU WU Differential and Integral linearity distribution of two kinds of layout methods for each current source. 3.23 LSB 125 MS/s < 8 ns 3 ns 40 psV 150 mWatts 5V 0.21 LSB. Using threshold-voltage compensated current sources.8um CMOS 1.0mm SUMMARY 1.21 LSB 0.9 5-Cell Unit(%) 21. Few analog components & good performance.8mm×1.1 93. Resolution Differential Nonlinearity Integral Nonlinearity Conversion rate Settling Time (±1/2 LSB) Rise/Fall time (10-90%) Glitch Energy Power Dissipation Supply Voltage Process Chip Size (without pads) 10 bits 0.4 67. INL<±0. 10 bits. Linearity Error <1/2 LSB <1 LSB <2 LSB 4-Cell Unit(%) 28. 32 slave unit current sources.3 Characteristics of the D/A converter.

.p Vout. (2) The matching requirement is much relaxed . 50% matching→DNL<0. . ∵ only 1 LSB current source is switched. Current-cell-matrix DAC 1. 1 1 0 → 0 1 1 1 1 1 1 1 1 1 → 1 1 1 1 1 1 1 2. Thermometer code (3 bit) b2 b1 b0 d6 d5 d4 d3 d2 d1 d0 0 0 0 → 0 0 0 0 0 0 0 0 0 1 → 0 0 0 0 0 0 1 0 1 0 → 0 0 0 0 0 1 1 . e. . .5 LSB (3) At the midcode transition the glitch is greatly reduced. Conceptual circuit of thermometer-coded DAC V DD Vout.n Binary input 10 1 2 3 Binary-to-thermometer decoder 1024 +50% Tolerance -50% one step 1 LSB 1 SWITCH 4X 4 LSB 4 SWITCHES Advantages: (1) Monotonicity is guaranteed.g.11-24 CHUNG-YU WU §11-4 Thermometer-Code DAC Current-mode thermometer-coded DAC.

D7) . -----.11-25 CHUNG-YU WU (4) Glitches do not contribute much to nonlinearity. * The six MSB bits are fed to the decoders. Glitches ∝ switched LSB ⇒ Glitch/LSB ≅ constant ⇒ Good linearity. 3. a switch. (D2. and the binary to thermometer decoder. Disadvantage: Area consuming ∵Every LSB needs a current source. a decoding circuit. 8-bit current-mode thermometer-coded DAC •Conceptual architecture Vdd R Vout 4LSB 2LSB LSB * The two LSB bits D0 and D1 are fed to two parallel three-stage pipelined latches directly.

11-26 CHUNG-YU WU •Segmented decoding structure of the DAC D2 D4 Two-stage decoding of low bits Cell Two-stage decoding of high bist D5 D3 D7 D6 •Decoding scheme: Column D4 D3 D2 D4+D3+D2 = C1 D4+D3 = C2 D4+D4D3+D3D2+D4D2 = C3 D4 = C4 D4D3+D4D2 = C5 D4D3 = C5 D4D3D2 = C7 •Decoding of current-source matrix: R1 R2 R3 R4 R5 R6 R7 R1+C1 R2+R1C1 R3+R2C1 R4+R3C1 R5+R4C1 R6+R5C1 R7+R6C1 R7C1 R1+C2 R2+R1C2 R3+R2C2 R4+R3C2 R5+R4C2 R6+R5C2 R7+R6C2 R7C2 R1+C3 R2+R1C3 R3+R2C3 R4+R3C3 R5+R4C4 R6+R5C4 R7+R6C4 R7C3 R1+C4 R2+R1C4 R3+R2C4 R4+R3C4 R5+R4C4 R6+R5C4 R7+R6C4 R7C4 R1+C5 R2+R1C5 R3+R2C5 R4+R3C5 R5+R4C5 R6+R5C5 R7+R6C5 R7C5 R1+C6 R2+R1C6 R3+R2C6 R4+R3C6 R5+R4C6 R6+R5C6 R7+R6C6 R7C6 R1+C7 R2+R1C7 R3+R2C7 R4+R3C7 R5+R4C7 R6+R5C7 R7+R6C7 R7C7 Row D7 D6 D5 D7+D6+D5 = R1 D7+D6 = R2 D7+D7D6+D7D5+D6D5 = R3 D7 = R4 D7D6+D7D5 = R5 D7D6 = R6 D7D6D5 = R7 .

Φ D5 D7 Φ Buffers Φ Φ Buffers D5 D7 D7 D6 D7 D7 D6 master slave First stage Second stage •Logic diagram of the segmented column decoder is similar to that of the row decoder. •Current cell circuit Ci Ri Φ Φ Ri+1 Third stage * The third stage of the pipelined circuit. .11-27 CHUNG-YU WU •Logic diagram of the segmented row decoder * Clocked CMOS gates * Pipelined structure with two stages.

Switching order 1 Switching order 3 5 7 C1 C3 C5 C7 C6 C4 C2 1 3 5 R1 R3 R5 R6 R4 R2 R7 6 6 4 2 7 4 2 Switching order Switching order •Current source and current switch Vdd Vdd Ir Vcomp M1 Vcomp Vref D A M2 M3 C Vp Vref Vp B 1 LSB current source 2 LSB current source Vdd Vcomp Vref Vp 4 LSB current source .11-28 CHUNG-YU WU •Symmetrical switching sequence to reduce the gradient effect.

∵Current switching and better matching than resistors. (4) Complicated wiring (5) Large chip area ⇒ worse matching problem. . (2) Require special layout arrangement and complicated switching sequence to reduce the mismatches among current cells in the matrix ⇒ complicated decoder (3) Logic circuits and long delay.11-29 CHUNG-YU WU •General characteristics/features of current-mode thermometer-coded DAC: (1) No resistor or capacitor are used. (6) Suitable for high-speed (video) and high-resolution (10-bit) CMOS DAC.

Dec.0 lsb THD↓ binary segmentation [%] thermometer .11-30 CHUNG-YU WU §11-5 Hybrid DAC Combined architecture: Resistor-string + charge-redistribution DAC Weighted-current-source + current-mode thermometercoded DAC §11-6 Case study Ref. PP.1948-1958.5 1024 )σ = 16σ DNL (10-bit) σ 1024σ = 32σ Area (INL=0.5-lsb) 256*Aunit 64*Aunit 1024*Aunit 256*Aunit 64*Aunit Aunit σ : standard deviation of current sources. Chip area ∝ 12 σ •Normalized required chip versus percentage of segmentation and THD versus percentage of segmentation ⇒ Optimal point Adigital = AINL = 1.: IEEE JSSC. Aunit: minimum required area to obtain a DNL = 0. vol.5-lsb) Area (INL=1-lsb) Area (DNL=0.33.1998 10-bit 500-MS/s CMOS DAC: •Chip area comparison between weighted-current-source DAC and thermometercoded DAC TABLE I AREA R EOUIREMENT FOR BINARY-WEIGHTED AND THERMOMETER-CODED DAC Requirement Binary Weighted Thermometer Coded INL (10-bit) 16σ (0.5 LSB for the thermometer-coded architecture.

11-31 CHUNG-YU WU •Block diagram: 8+2 segmentation •Cell circuit Digital: decoding logic + latch Analog: differential switch + cascoded current source. •Biasing scheme Global biasing: common-centroid layout Local biasing: 4 quadrants without direct connection between any two quadrants ⇒ DNL ↓ and INL ↓ .

SFDR=60dB •SFDR versus Fsig/Fs SFDR 73dB 60dB 51dB Fs(MS/s) 100 300 500 Fsig(MHz) 8 100 240 .11-32 CHUNG-YU WU •Sinewave spectrum for Fs=300MS/s and Fsig=100MHz .

2 LSB 2.1 LSB 0. SFDR = ID1* .ID3* = ID1* .11-33 CHUNG-YU WU •Summary DNL INL 0.N0 ∵ ID1 curve has a slope=1 ⇒ (dB) SFDR= A I D3= N0 − AN 0 ID1= N 0 . Definition of SFDR (Spurious-Free Dynamic Range) SFDR: The signal-to-noise ratio when the power of the third-order intermodulation products equals the noise power.

Canepa. Dec." 1990 Symposium on .E. 1986." IEEE J. Ahuja. June 1989. pp. Cremonesi. N. " IEEE J. "A CMOS triple 100-Mbit/s video D/A converter with shift register and color map. "An 8 bit 150 MHz CMOS D/A converter with 2 Vp-p wide range output. Nakamura. Nakaya. 1986. 989-995. Asai. Miki. Y.N. pp. Ono. Solid-State Circuits.J. L. N. Y. 1041-1047. 2. 4. solid-State Circuits. Dec.R. R. Horiba. Sakamoto. K. and Y. 1987. Mayer. Maloberti." IEEE J.K. and N. Kumazawa. Soulid-State Circuits. " A high-performance CMOS 70-MHz palette/DAC." IEEE J. " A 100-MHz CMOS DAC for videographic systems. A. Quader. Fukushima. T. and G. Lteham. Polito. 5. N. Akasaka. 3. pp. 635-639. S. "An 80MHz 8-bit CMOS D/A converter. Chi et al. pp. R. 983-988. M. B. Solid-State Circuits. F. Kuang K. Dec. Larsen and G.11-34 CHUNG-YU WU §11-7 Summary [16] [15] [14] [9] [10] [7] [6] [13] [12] [3] [2] [8] [5] [11] [14] [4] [1] 1.

Solid-State Circuits. H Termeer.6 mm2. W. 12. pp. A. Marcel Pelgrom. Member. 12. Yazawa. C. 200-201. pp. 1998. 10. Alex R. Shu-Yuan Chin and Chung-Yu Wu. A. Willy Sansen. D. of IEEE International Solid-State Circuits Conference. " IEEE J. 13. Willy Sansen. no." IEEE Journal of Solid-State Circuits. Member. Yokoyam. 1374-1380. pp. Dec. Marques. NO. A. Bastiaansen. Rakers. Steyaert. pp. "A 10-b. pp.11-35 CHUNG-YU WU 6." IEEE J. 1998. 11. 26. " A 10-b 125-MHz CMOS Digital-to-Analog Converter (DAC) with Threshold-Voltage Compensated Current Sources. Fourier and P. pp. Jose Bastos. pp. " IEEE Journal of Solid Circuits. Takakura. 14. July 1991." IEEE Journal of Solid-State Circuits. " IEEE J. Miki. J Greoeneveld. and N. Gielen. " A 320 MHz CMOS triple 8-bit DAC with on-chip pll and hardware cursor. " A 10-b 70-MS/s CMOS D/A converter. 12. Solid-State Circuits. 1073-1077." IEEE JOURNAL OF SOLID-STATE CIRCUITS.5. IEEE "A 14-b. Dec. " A 130-MHz 8-b CMOS Video DAC for HDTV Applications. " IEEE J. DECEMBER 1999. M. J. Dec. and Steven F.M. 1994.8-ìm CMOS current-output D/A converter. Solid-State Circuits. no. and A. and H. 1994. . 1545-1551 DEC. pp. 917-921. and Georges G. 11. " 1991 IEEE Custom Integrated Circuits Conference. Bugeja. 1990.29. Y. 12. July 1991. "A 14-bit Intrinsic Accuracy Q2 Random Walk CMOS DAC. 34. 9. M. pp. Gilling. 55-56. Chi-Hung Lin and Klass Bult. vol. Augusto M. J. VOL. pp. Member. vol. Bang-Sup Song. 34. IEEE. J. 7. 33.1708-1718. H. 16. Solid-State Circuits. Michel S. Nov.1-26. H. 1959-1969. VLSI Circuits. IEEE. 12. 12. 637-642. Reynolds." IEEE Journal of Solid-State Circuits. " A 50MHz 10-bit CMOS digital-to-analog converter with 75Ù buffer. 1991. 500-Msample/s CMOS DAC in 0.4. 1948-1958. 15. vol. no. 33. Kondoh. Fellow. 8. " A 10-b 40-MHz 0. T. A. no. Michel S. Jan Vandenbussche. J. Van der Olas. E. D. 100-MS/s CMOS DAC Designed for Spectral Performance. Greet A.5. 29. 1999. Maeda. no. " A 10 bit 80MHz glitchless CMOS D/A converter. Apr. vol. Senn. Nakamura. 7. Schouwenaars. Patrick L. Yamaquchi. no. IEEE. Steyaert. H. pp. "A 12-Bit Intrinsic Accuracy High-Speed CMOS DAC. vol. 26. vol." Proc.

Well suited for the logic circuits usually following the latch. whose amplitude and waveform are independent of those of the input signal. If no latch: -1mV → +1mV input =>-5V→+5V output Gain=5000.12-1 CHUNG-YU WU CH 12 CMOS Analog Comparators §12-1 General Considerations Purpose of Comparators: To compare two input voltages and produce a very large output voltage with an appropriate sign to indicate which of the two is large.2V =>Gain = 200 (1) Static configurations (2) Dynamic configurations B. Differential-input OP AMP _ A + or Latch Vout Vout The latch provides a large and fast output signal. which is about 0. Cascaded inverter stages Vin -A1 -A2 -A3 -An Vout Latch * Mostly dynamic or Vout . 74 dB If use latch: The output voltage of A must be larger than the combined offset and threshold voltage of the latch. Types of MOS Comparators: A.

General-purpose comparators * Propagation delay: * Power Dissipation: (±10mV. * Power Dissipation: ~10 mW 2.0µs~2.8µs .12-2 CHUNG-YU WU §12-2 Differential-Input OP AMP Comparators §12-2.1 Static Configurations without Latches 1. +VDD M9 M8 Vbias M11 M10 M1 M2 + M12 Vout M15 M3 M4 M6 M7 M5 M13 M14 -VSS * High Speed Comparator * Open loop gain: ~80dB * Output Swing: ±5V * Propagation Delay (±10mV Vin ): ~1.4µs (15PF Load) * Generally. compensation circuit is not needed since there is no feedback connection. 15PF) ~ 4mW 1.2µs~2.

+VDD M3 M7 Vbias M 8 + M1 M2 M9 M10 M5 M6 M13 M15 -VSS M11 M12 Vout M4 M14 - * Open loop gain: 60-80dB * Output Swing: +5V→0V * Propagation delay (±10mV. 15 PF): 1.12-3 CHUNG-YU WU +VDD M3 M7 Vbias M8 M1 M2 + Vout M10 M4 M5 M6 M9 M11 -VSS 3. Comparator with level shift.8µs .0µs~0.

§12-2. (1) Dynamic OP-AMP type comparator * Compensated by C2 * Vc1=Vin-Vos + _ ψ 1=1 Vin . CMOS Voltage Comparator MC 14574 (Motorola) V+ Q5 Q6 input+ I Q Q8 Q10 Q12 Vo inputQ1 Iset Q9 Rext Q3 External resistor VQ4 Q7 Q11 Q2 * Quad comparators * Open loop gain (Iset=IQ=50µA): 96dB * Propagation delay: ~1µs 5. Fully differential OP-AMP Comparators. ψ 2 :nonoverlapping clocks .Vos + C1 +V in C2 _ + Vos ψ 2=1 Vref +V in + C1 △ Gain Stage + _ Vout * offset memorization C2 _ + Gain Stage + _ Vout Vc1 + _ Vos *△Vc1=Vref-Vin * No compensation * offset cancellation ψ 1 .5mW 4.12-4 CHUNG-YU WU * Power Dissipation: ~1.2 Dynamic Configurations without Latches.

Vs.Vin+ * S1 and S2 generate feedthrough voltages at A and B => common-mode voltage * CMRR can be promoted by using negative common-mode feedback circuit..12-5 CHUNG-YU WU +VDD φ1 Vin S1 C1 φ1 S4 + _ C2 Vout φ2 Vbias Vref -Vss S3 φ 1a * Practically. △VC2=Vin.. VC2 =Vin+ . .Vin-. C2: Autozeroing capacitors φ1 =1 Vc1=Vin.Vs φ2 =1 △Vc1=Vin+ . (2) Dynamic fully differential comparator Vin+ +V DD Vbias1 + Vout C1 S1 A Vs Vs S2 B Vin- φ2 φ1a φ1a C2 φ2 φ1 φ1 Vbias2 VinVin+ -V SS C1. φ1a must go low first in advance of φ1 to avoid the clock feedthrough effect of S1 by φ1.

Q6 and Q7 are a bistable latch. Q2.12-6 CHUNG-YU WU §12-2. Q5. φ2 →1. Operating clock waveforms: . Q3. Q4. S5 short S6 short => => Q1. Q4 and Q7 are differential amplifier. Q3.3 Dynamic Configuration with Latches Preamplifier-latch combination +VDD VBIAS1 Q3 VC Q4 D S8 Q1 VinS1 C1 Q2 B C2 S5 VB + Vout C φ1 S7 φ1 + Q5 Q6 φ3 Vin+ φ3 S4 Vin+ S6 φ2 φ3 S3 Vin- φ3 φ2 Q7 VBIAS2 -Vss * φ2 →1.

* Q1 ≡ Q3. CA<<C. VA1=Vin + VAo △VA=Vin (2) CMOS Cascade Comparator. Q2 ≡ Q4 (b) =>negligible feedthrough .12-7 CHUNG-YU WU §12-3 Cascaded Inverter Stages (1) Basic Structure VT ↓ VDD Q2 S3 VA VB Q1 VT ↑ -VSS (a) +VDD (b) ψ1 C Vin A ψ2 VA CA (stray) + S3 B ψ3 Q2 VB Q1 -Vss (a) φ2 →0.

5 pF VDD Q2 ψ1 Vin S1 S2 ψ3 VB B Q4 ψ3 C VC S8 D C3 VD Q5 Q1 Q3 ψ 5 (balance) VSS LATCH S5 Vout ψ 6 (strobe) Q6 C2 A S3 C1 VA ψ2 (a) (b) . R = R 0 = rdsp rdsn Cin=Cgs + Cgd(1+ A ) A ~ 10 ~ 100 kΩ ~0.12-8 CHUNG-YU WU * The speed of the cascaded inverter stages is limited by the RC times constants.

=>Two amplifiers share one latch. the speed of a latch is faster than that of a amplifier. VDD ψ1 Vin S1 C ψ3 ψA SA ψ1 LATCH VSS VDD ψS ψ2 C ψ4 ψB SB ψ2 VSS * Operating clock waveforms . * Usually.12-9 CHUNG-YU WU (3) Fast comparators with two amplifiers and a single latch.

may be replaced by a threshold voltage or can be generated by self-biasing 2. Vin+ or Vin. Direct-coupled latch with differential input signals VDD ψ1 Vin + C1 Vout + Vout C2 Vin ψ2 ψ1 ψ2 -VSS * For single-ended inputs.12-10 CHUNG-YU WU §12-4 CMOS Dynamic Latches for Comparators 1. Capacitively coupled latch with autozeroing input V DD Vout ψ1 ψ 3 Q5 ψ C 2 C4 C3 ψ S5 Q6 2 Vout + ψ D S6 B VB C2 + S8 S7 ψ 3 1 S3 C1 A VA VC Q1 Q2 S4 VD Q 3 Q4 ψ 3 Vin- S1 ψ3 S2 + V in- VSS Vin + (a) .

. H.: VC Vin. VD VD L. L. * Vin+ < Vin.12-11 CHUNG-YU WU * φ2→1 => inverters Q2-Q5 and Q3-Q6 are biased at their optimal points C3 and C4 are also precharged such that any asymmetry between the two inverters is compensated by the slightly different bias voltages provided by C3 and C4.< Vin+ : VC H. => loop gain of the latch=1.

M8. Q established for input sampling V ψ 2e ψ2 ψ1 t1 t2 t3 t4 t .12-12 CHUNG-YU WU §12-5 Case Studies 1. 1992 input stage VDD 1:2 M13 M3 M10 ψ1 IB c flip-flops S-R latch M6 M7 M11 Q d Q Vinp1 M1 M2 M8 Vinp2 a VSS M4 ψ2 M12 M9 b M5 t1~t2: M12 ON (φ2 =1) M10-M11 ON. Q= Q Vinp1 and Vinp2 settles t2~t3: Va ≠ Vb established with some regeneration of M4 /M5. vol. M12 OFF t3-t4: φ1 =1. Differential-Input OP AMP Comparators with Dynamic Latches Ref. 27. M9 ON strong regeneration =>Vc ≠ Va. M10. IEEE JSSC. Feb. M11 OFF. M8-M9 OFF (φ1=0) Va=Vb. Vc=Va. φ2=0 => M12 OFF. pp. 208-211. Vb=Vd =>Q. Va=Vc.

5 V 2.6 mV ( < 7 bits) 65MHz 3.12-13 CHUNG-YU WU Performance: Technology Die size Power supply Input dynamic range Resolution Sensitivity Sampling rate Offset voltage Input capacitance 1.5 V 8 bits.5 / -2. 1LSB=9.3 mV 30 fF .5 um CMOS 140 x 100 um2 +2.8 mV 10.

b N is the digital output Vx is the tolerable input signal range − 1 VLSB ≤ Vx ≤ 1 VLSB 2 2 2-bit ADC: Input-output transfer curve: equivalent DAC transfer response Bout 1V 1 LSB) Offset by ( 2 LSB 2 11 1 VLSB = Vref → 1 LSB 4 10 VLSB 1 = →1 LSB 01 Vref 4 The input voltage or current 0 0 1/4 1/2 3/4 should remain less than 3/4 Vref + V V V V V V 1/8 Vref =7/8 Vref and greater than V V 0 . = 0 1 01 10 11 Vin Vref ref ref ref ij ref . Functional block diagram of a A/D converter Analog Input Sample and Hold A/D Converter Output Latch Digital Output Control Logic 2. Ideal A/D Converter (ADC) Vin ± Vx = Vref ( b12−1 + b2 2−2 +⋅⋅⋅⋅ +bN 2−N ) Vref (b12 N −1 + b2 2 N −2 + ⋅⋅⋅⋅ +b N −121 + bN 20 ) N 2 where Vin is the input analog voltage or current Vref is the reference voltage or current b1 … … .1/8 Vref = -1/8 Vref .13-1 CHUNG-YU WU CH 13 CMOS Analog to Digital Converters (ADCs) §13-1 Introduction 1.

the quantization error is greater than 1/2 VLSB.13-2 CHUNG-YU WU Overloaded ADC: When Vin > Vin ideal + Vx or Vin < Vin ideal − Vx . V1 = Vin + VQ V in VQ = V1 . Quantization noise Quantization error → Quantization noise. 3.Vin ADC DAC V1 + + Quantization noise modeling: (1) Deterministic approach  VQ(rms) =  1 T VQ ∫ T/ 2 −T /2 2 VQ  dt  1/ 2  =1 T 1/ 2 ∫ T /2 −T/ 2 2 VLSB ( − t )2 T  dt  1/2  VLSB3  t 3  = T3  3       − T /2    T /2 = VLSB 12 V Vin V1 + VQ 1 VLSB 2 0 V1 1 VLSB 2 T 2 T 2 t t ( time ) (2) Stochastic approach  VQ ( rms ) =     = 1 2   VLSB   High = ∵ 1 V LSB fQ (x) (probability density function) ∫ ∞ −∞  2 x 2 f Q ( x ) dx   1/ 2 ∫ f Q (x) ∞ ∞ dx =1 ∫  x 2 dx   − VLSB /2   V LSB /2 1/2 X = VLSB 12 1 2 V LSB + 1 2 V LSB .

(4) Sampling-time uncertainty or aperture jitter Due to the effective sampling time changing from one sampling instance to the next.5 LSB or maximum INL < 0.76dB VQ ( rms ) VLSB / 12  2  The above SNR is the best possible SNR for an N-bit ADC Vinpp = Vref ( 0dB) → SNR = 6. Typically.76 )dB − 20 dB 5.02 N +1. Signal-to-Noise Ratio (SNR) (1) Vin is a sawtooth of hight Vref (or a random signal uniformly distribut between 0 and Vref )  Vin ( rms ) ⇒ SNR = 20 log  VQ ( rms )   V / 12   N   = 20 log  ref   V / 12  = 20 log 2 = 6. the sampling rate is equal to the inverse of the conversion time except in the case of pipelining structure or multiplexing structure. ⇒ SNR = 20 log Vin( rms ) V /2 2   = 20 log ref = 20 log 3 ×2 N  = 6.13-3 CHUNG-YU WU 4. (2) Conversion time The time taken for the ADC to complete a single measurement including acquisition time of the input signal.02 N +1.5 LSB ⇒ The ADC is guaranted not to have any missing code.76 dB Vinpp ⇒ − 20 dB → SNR = (6.02 N +1. Sinusoidal waveform case: Vin = Vref sin (2π f in t ) 2 .02 N dB   LSB  (2) Vin is a sinusoidal waveform between 0 and Vref . Performance specifications (1) Missing codes (equivalent to monotonicity in DAC) Maximum DNL < 0. (3) Sampling rate The speed at which samples can be continuously converted.

1 MHz (5) Dynamic range Dynamic range ≡ f in ⇒ ∆t < 5 ps f in ⇒ ∆t < 5 ps rms value of the maximum input (output) sinusoidal signal rms value of the output noise plus the distortion when the same sinusoidal is present at the output It is also called the signal-to-noise-and-distortion ratio (SNDR). * Input frequency dependent. ∆t < VLSB = N1 π f in Vref 2 π f in examples: 8-bit ADC. 250 MHz 16-bit ADC. 6. Types of ADCs Low-to-medium speed: (1) Dual-slope or Integrating ADC (2) Oversampling ADC (3) Successive approximation ADC (4) Algorithmic ADC High speed: (1) Flash ADC (2) Two-step ADC (3) Pipelined ADC (4) Interpolating ADC (5) Folding ADC (6) Time-interleaved ADC . * Can be expressed as effective number of bits using the SNR formula on p.13-4 CHUNG-YU WU dV dt in max =π f in t zero-crossing point If ∆V < 1 VLSB for some sampling-time uncertainty ∆t . 13-3.

vol. * Dividing the string into several equal lengths and locating them in close proximity. 8 bit ± 1 LSB 2 ± 1 LSB 10 20 µs >1000 MΩ <1/4 LSB .85o C) Error Sources: 1. Resolution Nonlinearity DNL Conversion time Input resistance Stability (0o .1 Resistor-string SA MOS ADC Ref.13-5 CHUNG-YU WU §13-2 Successive-Approximation (SA) ADC's §13-2. Resistor matching accuracy. Dec. Conceptual 3-bit unipolar ADC VREF 3R 2 R R R Comparator R _ + C C B B A A Output R VIN R R 2 Typical performance of a 8-bit ADC: p-type resistor 100Ω / . Sc-13. : IEEE J. 1978. 785-791. pp. Solid-State Circuits.

Range 4. 912-920. Similary. Solid-State Circuits. The small on resistance of the switches can decrease the settling time and reduce the feedthrough effect from the gate voltages. 4. 1979. Vref 3rd MSB F E F F E F H G LSB T2 H H G H R/4 D R/8 R/8 1/2 LSB Shift T2 C/16 T1 R/4 R/4 D D C R R R B A B B A B D C 2 nd MSB T2 C MSB Vin 2-bits + T1 T1 T2 C Sample data Comparator T1 C/16 8-bit ADC Linearity Conversion Time 640 KHz clock Analog Input 0 .8mA 0-5V 100 . 1 MHz clock → 2 mV error. §13-2.VDD 1/4LSB 100 µs C=20pF Supply Voltage Current Drain VREF Range Clock Freq. 32 switches. Comparator offset error. Bit capacity ↑ ⇒ Ω / ↓ . 5.2 Charge-Balancing SA MOS ADC Ref. Dec. . * Mixed resistor string and binary-weighed cap. pp.5 .13-6 CHUNG-YU WU 2. The reverse bias junction voltage of the diffused resistors causes nonlinearity. the switch feedthrough only effects the settling time.800 KHz Components used: 8R's.3 V 1. : IEEE J. Major error source: The feedthrough in the switch transistor Q2.6. 4C's. 3.

Post-process triming => Linearity Conversion Time Analog input Clock freq. pp. 10-bit CRSA ADC Ref: IEEE JSSC.3V 5mA §13-2. Dec.5 ~ ±6.3 Charge-Redistribution SA MOS ADC (CRSA ADC) 1.1 ~ 3MHz ± 4. vol.13-7 CHUNG-YU WU 13-bit ADC with laser-cut programmable Si-Cr fuse PROM's. 371-379. range Supply voltage Current drain 1/2 LSB 50 µs -Vss ~ +Vcc 0. SC-10. 379-385. Operation Procedures (a) Sample Mode: (b) Hold Mode: .1975.

Vx = -Vin + Vref /2 If Vx < 0. logic 1 in MSB(b4). b4(MSB)=0. If Vx > 0. Final Configuration: Vin > Vref /2 Vin < Vref /2 and S1 → ground Vx = − Vin + Vref ( + Vx = − Vin + b 4 b 3 b 2 b1 b 0 + + + + ) ≈0 21 2 2 2 3 2 4 2 5 Vref 4 ( 2 b 4 + 2 3 b3 + 2 2 b 2 + 21 b1 + 2 0 b 0 ). Vin > 0 5 2 .13-8 CHUNG-YU WU (c) Redistribution (Approximation) Mode: S1 → Vref .

3µs 22.05 % 2.8 µs .13-9 CHUNG-YU WU Complete ADC block diagram: Measured Results: Resolution Linearity Input Voltage Input offset 10 bits ± 1 LSB 2 0-10 V 2mV Gain error Sample mode acquisition time Total conversion time < 0.

Dec. 920-926. pp. VREF R1 SF Ck+1 R3 Ck C3 2C C C2 C1 C + Comparator SA R2 M-1 CLOCK B R2M SB SWITCH CONTROL SUCCESSIVE APPROX. Solid-State Circuits. 1979. vol.: IEEE J. 12-bit modified CRSA ADC Ref. REGISTER + SWITCH CONTROL LOGIC R2 2 k-1C 2 k-2C A VIN (M+K) BIT OUTPUT OF A/D START * SAMPLE * HOLD * CHOOSE Vref VREF R1 S5 Vin Larger 1 SA 2 2 SB Voltage A.13-10 CHUNG-YU WU 2.SA B Vref 4 Vref 2 discharge set-up - SB 2 S1 S2 S3 S4 S5 S4 3/4 V REF ON ON R2 S3 1/2 V REF Smaller - 1 ON ON R3 S2 1/4 V REF R4 0 S1 2 1 1 1 ON ON ON ON ON 1 redistribution 2 . sc-14.

18Ω/ . 37 MOS R: S/D diffusion. …. …. Offset Operational Principle: Vref S5 5 mV SX 2k-1C C SLK 1 SA 2 SL2 C SL1 + Vx + Comparator R1 R2 S4 S3 R3 S2 R4 S1 VIN 2 SB 1 SA Sample Hold Choose Vref - SB Vin 1 (0) S1 S2 S3 S4 S5 SLK … . 400 µm2. …. 16 R= 9000 Ω C: Unit capacitor. ….13-11 CHUNG-YU WU Implement: 16 R. 8 ratioed capacitor. B B B B B B B B B B Sx ON OFF Vx 0 -Vin ON OFF OFF OFF OFF ON ON OFF OFF OFF OFF ON ON OFF OFF OFF OFF ON ON OFF OFF OFF OFF ON OFF 2 (Vref/4) 1 (Vref/2) 2 (3Vref/4) 4 OFF − V + 2Vref in 4 OFF − V + 3Vref in 4 OFF − V + Vref in Discharge - 1 (0) ON OFF OFF OFF OFF B ….1 pF Measured data: Resolution Monotonicity 12 Bits 12 Bits Area 12. SL2 SL1 B B B B B …. B B OFF -Vin . 0.000 mil2 Power dissipation (15V) 40 mW DNL Total conversion time 1 LSB 2 50µs Integral Linearity 6 Bits Input.

B B OFF (Vref) (3Vref/4) − Vin + 3Vref 4 1 2 -Vin+(3/4)Vref < Vx < -Vin + Vref OFF OFF OFF ON ON A … . .13-12 CHUNG-YU WU Set up Redistribution 1 2 OFF OFF OFF ON ON B …. B B OFF 3V − Vin + ref 4 + 1 Vref 8 * The last capacitor C is always connected to B.

X10 TO DIGITAL SECTION REF LO DE + BUFFER + C2 <10> COMPARATOR 1 + C3 INTEGRATOR <100> COMPARATOR 2 + RINT CINT X10 A - . DISPLAY MULTIPLEXER UP/DOWN RESULTS COUNTER SEQUENCE COUNTER / DECODER CONTROL LOGIC ANALOG SECTION CREF REF HI DE INT1 IN HI DEDE+ COMMON INT IN LO INT1.IN2.13-13 CHUNG-YU WU §13-3 Dual-Slope ( Integrating. Charge-Balancing ) MOS ADC's 4 1 Digit ADC (Modified structure) 2 LATCH.INT REST DE+ DEZI . DECODER.

INT1 REF HI CREF REF LO CINT RINT IN HI COMMON IN LO + + C3 100p + Comparator 1 + + Comparator 2 .13-14 CHUNG-YU WU Waveforms observed at the node A : △ V △ V' INT1 DE1 RESET X10 DE2 INT(ZI) INT2 NOTE: ENCLOSED AREA GREATLY EXPENDED IN TIME AND AMPLITUDE Operational principles: 1.

13-15 CHUNG-YU WU 2. DE1 REF HI + - REF LO R INT + + + - CINT + COMMON C3 100p + - 3. REST (INT2) REF HI CREF R INT + + COMMON IN LO C3 100p △ REF LO CINT +△V + + V + △ V : Residual Voltage 4. × 10 (INT2) RINT 10 △ V + C INT + COMMON IN LO + 10 △ V + C2 10p C3 100p + - + - .

DE2 (The same as DE1).13-16 CHUNG-YU WU 5. ∆V ' : residual voltage 6. ⇒ accuracy ↑ . INT(ZI) R INT C INT + + C3 100p + - + - IN LO The final residual voltage ∆V ' is effectively reduced to 1 of the original 10 residual voltage without amplification.

31. no. 96-97.Vref The conceptual block diagram of the algorithmic A/D converter * The speed is limited by the settling time of OP AMPs used to implement the multiplier. vol. it could reach low-power low-voltage operation. pp. (3) Offset voltage of OP amps. Aug. (2) Finite-gain error of OP amps. 1996 Sample/Hold Comparator S/H V(i) multiplier x2 Comp. Vin + B(i) + Σ - + Vref . IEEE JSSC. * For audio ADC applications. * Major error sources: (1) Capacitor ratio mismatches if SC circuits are used. pp. . IEEE ISSCC. 1201-1207. Digest of Papers. 8.13-17 CHUNG-YU WU §13-4 Algorithmic ADC Refs: 1. 1977 * 2. (4) Capacitor feedthrough error by switches if SC circuits are used.

13-18 CHUNG-YU WU Complete circuit of the ratio-independent and gain-insensitive algorithmic ADCs 1+2 1+2+3+4+5 2 8*1 1+2+3+4 3+4+6+7 C3 (B) C7 S4 S6 C4 3+6 5 C2 S2 1 1+2 5 S3 3+4+6+7 (C) OP2 + 4 3+4+7 7 8 S1 (A) + OP1 Vin C1 Vref 3+4+6+7 4 S5 C5 C6 3+4+5+6+7 3+7 b8*1 3+6 b8(1+2) 6+7+1 2 C8 (D) S7 comp. + + - Latch Q Q bBit Bit 7+1 switch The complete circuit of the A/D converter Clock waveforms: 1 2 3 4 5 6 7 1 8 .

Vx (2) ≅ Vin / (1+2/A) Step 3: C2 C4 C1 OP1 + Vx(3) C3 C7 OP2 + C5 C6 Vx (3) ≅ Vin [1-2/(A2 +3A+2)] .13-19 CHUNG-YU WU Operational principles: Step 1: C2 8*1 C1 Vin 8 + b8*1 C5 OP1 C3 C7 OP2 + C6 Vy(1) C4 b8*1    Vy (1) ≅  2 − 13A + 20 + 13A + 27  Vx ( 3) −  1− 7 A + 82 + 7A + 92  ( A + 2 ) 2 ( A + 3) 2   ( A + 2) ( A + 3)    Step 2: C2   Vref   C1 Vin 8 + OP1 Vx(2) C3 C7 - C4 OP2 + Vy(2) C5 C6 b8*2 to Comp.

13-20 CHUNG-YU WU Step 4: C2 C4 C3 C1 OP1 + C5 Vref C7 OP2 + C6 Vy(4) Vy ( 4 ) ≅ C5 ( Vx ( 3) − Vref )(1+ 3/ A ) C6 Step 5: C2 C4 C1 OP1 + Vref C3 C7 OP2 + Vy(5) C5 C6 Vy (5) ≅ C3 ( Vx ( 3) − Vref )[1+ 6 /( A 2 + 5A )] C4 Step 6: C2 C4 C1 OP1 + C3 C7 OP2 + C5 C6 .

+ .+ bBit Bit Vin- The complete fully-differential circuit of the A/D converter .13-21 CHUNG-YU WU Step7: C2 C4 C1 OP1 + C3 C7 OP2 + Vy(7) C5 C6 ( 2 − 2 ) Vx ( 3) − (1− 2 ) Vref A +3 A+ 3 Vy ( 7 ) ≅ 1+ 3 / A Fully differential circuits: Vin+ Latch -+ +OP1 Vref+(-) Vref-(+) -+ +OP2 -+ +comp.

.13-22 CHUNG-YU WU The folded-cascode fully-differential operational amplifier. VDD m12 m13 m4 m5 VB1 m6 Vo+ VoVinm1 m3 Vin+ m2 m10 m14 m15 VSS m8 m7 VB2 m9 VB3 m11 VB4 Chip photograph of the A/D converter.

. A typical plot of the integral nonlinearity.13-23 CHUNG-YU WU A typical plot of the differential nonlinearity.

13-24 CHUNG-YU WU A typical FFT plot of the A/D converter.8mm Differential nonlinearity Integral nonlinearity Sampling frequency Gain of op amp Power dissipation Supply voltage Process Chip active area . Table I The Experimental results of the proposed A/D converter. Resolution 14 bits < ± 1/2 LSB < ± 1 LSB 10 KHz 60 dB 50 mWatts ± 2.1mm × 0.8 µm CMOS 2.5 V 0.

5] This work 12 8 14 <= 1.4]-[4. A/D converters Performance Resolution (bits) Absolute INL (LSB) OP amp dc Gain (dB) Clock cycles for n bits Sampling rate (KHz) Power dissipation (mW) [4.13-25 CHUNG-YU WU Table II Comparison of the proposed A/D converter with the previous ratio-independent A/D converters [4.5 <= 0.5 <= 1 92 84 60 6n 3n 7n 8 8 10 17 - 50 .4] [4.5].

Full-flash A/D converter VIN VREF+ Clock generator + + 2N-2 2N-1 2N-1 Encoder 2N-1 to N binary code + 2 + 1 comparator VREF1 Latch 2 Output registor & buffer 2N-2 bN-1 bN-2 bN-3 b2 b1 b0 . of analog elements. * S/H usually combined with comparators. ? Large chip area & power consumption. * Need 2N-1 Resister (R) tapes for N bits.13-26 CHUNG-YU WU §13-5 Full Flash (Parallel) * Need 2N-1 comparators for N bits. (No op amp is required) ? Large no.

6-BIT BINARY OUTPUT Block diagram of A/D converter chip.: IEEE JSSC. pp. vol. Dec.1 MOS Flash ADC's Ref.13-27 CHUNG-YU WU §13-5. CMOS/SOS 6 bit 20 MHz ADC. . 1979. 926-932. High speed autozeroed CMOS/SOS comparator. sc-14.

000 (< 10. RTAP = 20Ω Z( w ) R TAP ≥ 50.13-28 CHUNG-YU WU Discrete and distributed reference ladder models Ccomp ≤ 0. don't work) Reference ladder leading as a function of input voltage (|Z|(W) /RTAP = 500) Effect of loading ratio on reference ladder output. .05 pF.000.

⇒ Worst-case static loading which can't be bypassed makes recovery errors the significant error source. If the capacitor bypassing is performed at the externally accessable ladder midpoint tap. Recom.4V 75Ω 1 LSB 2 1 LSB 1.2V reference Input Cap.13-29 CHUNG-YU WU Major source of error is the loading of the reference resistor ladder by the comparator bank. 5V convert mode Tracking mode 3. 20 pF/output. Vref On-chip Zener Reference Input voltage source resistance Accuracy 15MHz 20MHz 25MHz 50mW 45mW 9mW 8 pF 3. * All the errors considered above are of this type.4V 6. ⇒ transient impedance ↓ by a factor of more than 4. Typical 6-bit A/D converter Performance: Power dissipation at 15 MHz clock. (2) Long-term "recovery error" associated with errors at a new input level after the ladder has been loaded for a long period by inputs at another level.2V 3. Resistor ladder loading errors are of two types: (1) "Transient error" associated with instantaneous ladder loading during a single measurement.5 LSB .2V 75Ω 1 LSB 2 ----8V 145mW 130mW 9mW 8 pF 6.

436-440.: IEEE J.2 7-Bit CMOS Flash ADC for Video Applications Ref. vol. June. 10 Ω / bit 2µm Poly-gate VLSI CMOS Overall ship area: 135×142 mil2 . sc-21.13-30 CHUNG-YU WU §13-5. pp. 1986 Overall schematic: D-Type Output Latch Overflow VREF TOP Comparator R/2 Banks Latches 127 R D6 D5 R 64 R/2 Mid Decouple Cext Capacitor Bypassing R/2 128 to 7 bit Encoder Logic D4 D3 R D2 D1 R 0 VREF Bottom Analog Input R/2 D0 Clock Buffer R: Polysilicon resistor. Solid-State Circuits.

(2) it can reduce the amount of hysteresis to ~ 100mV by setting "Latch" . Q5.Q6: Positive feedback to form latch. Q12: To limit the output swing and enable the comparator to recover much faster from the latched state. Q11. Q13: Operated in linear region with on-chip low-power OP AMP and reference loop. The secondary latch is of the hysteresis type. because (1) it can convert the limited logic swing of the primary latch to correct CMOS logic levels. fu↑. ⇒ Ro↓.13-31 CHUNG-YU WU Comparator and the primary latch +VDD OUTPUT Load Bias Q10 Q16 Vbias Q3 Q4 Vbias Q11 Q12 Q 13 Q14 OUTPUT Q5 Analog Input Q1 Q6 Reference Input Q2 Latch I2Bias IBias Q8 Q7 -VSS Latch Q9 I2Bias Q15 Gain: 18dB Bandwidth: 40 MHz Q10.

30 MSPS typically : 5V ± 0. range ± 0. Thus the latch always experiences an overdrive of 100 mV.5V : 1.40 o C to + 85 o C : -3dB 42 MHz. frequency .1 LSB 5 MHz 2 : > 22 MSPS. 56-57. ⇒ Reduce metastability error probability Performance characteristics: 7-bit inherently monotonic Accuracy: differential and integral Analog bandwidth Maximum sample rate VDD Input range Power consumption (25MSPS) Temp.5V : 350 mW : .5V~3. Nonsampling amplifier: φ1 φ1 S1 S5 VDD CA VDD φA S7 LATCH S2 φ1 φ2 S6 Sampling Clock φ2 S3 VDD VDD φB S8 S4 CB φ2 * Higher operating.: ISSCC 84. .5 LSB.13-32 CHUNG-YU WU signal to High. 315. §13-5. ⇒ Avoid ambiguous state and increase the resolution time of the comparators.3 CMOS 20 MS/S (Maga Samples /sec) 7-bit Flash ADC Ref. PP.

Aug.13-33 CHUNG-YU WU §13-5. ⇒7 errors per second * Can be improved to < 10-12 errors/cycle. pp.4 Metastability error Ref. . 1996. * It is nearly independent of the input frequency. vol. * At 70-MHz sampling frequeny. the metastability error rate is ~ 10-7 errors/cycle. VA < V REFi+1 0 0 0 i+1 1 i 1 VA > V REF 1 0 VA < V REFi+1 0 i+1 0 Metastable i X VA ~ V REFi state i-1 1 1 VA > V REFi-1 Thermometer code with valid comparator outputs Thermometer code with metastable comparator * Metastability error rate is an exponential function of the sampling frequency. 7-b 80-MHz flash ADC Metastability error: occurs in ADCs when undefined comparator outputs pass through the encoder to the converter output bits. 31.: IEEE JSSC. 1132-1140.

2 COARSE COMPARATOR NO. 1 TGC2 R3 15 *FINE* DECODER /ENCODER TGC1 R2 15 R1 CLEAR 15 FC #2 FC #1 VREF "FINE" COMPARATOR .13-34 CHUNG-YU WU §13-6 Two-Step Flash or Subranging ADC Conventional two-step A/D converter: + VIN SAMPLE & HOLD COARSE FLASH ADC DAC ANALOG ADDITION FINE FLASH ADC LATCH DIGITAL OUTPUT Two-step A/D converter with single resister ladder: Vin TGS2 SAMPLE TGS VIN SAMPLE MSB'S COARSE COMPARATOR NO. 16 COARSE COMPARATOR NO. 15 COARSE COMPARATOR NO. 14 TGC16 VREF 15 LSB'S TGC15 R16 15 TGC14 R15 15 R14 FC #15 FC #14 "COARSE" DECODER /ENCODER COARSE COMPARATOR NO.

* Need high-performance op amp.13-35 CHUNG-YU WU Two-Step Flash ADCs or Subranging ADCs with: (1) Two Resistor (R) Ladders * Need 2(2N/2-1) comparators & R tapes. ?As many R tapes as full flash type. ?High-performance op amp is not easy to be achieved (especially for 3 V Vdd). ?Nonlinearity caused by the mismatch of the two resister ladder. * Need 2(2N/2-1) comparators. . (2) Single Resistor Ladder * Need 2N-1 R tapes. ?No op amp is required.

Differential Linearity Error Typ. 1989.5 0.4 0. Conventional subranging A/D converter: Trade-offs in Subranging and Flash 8-bit ADC Flash Total comparators Clock cycles/conversion Relative speed Relative input loading Relative power dissipation Relative die size Typ.1 Subranging (Two-Step Flash) ADCs 8-bit 50MHz CMOS Subranging ADC with Pipelined Wide-Band S/H Ref.13-36 CHUNG-YU WU §13-6.12 0. Dec.7 LSB Subranging 31 2 0. . 1485-1491.: IEEE JSSC. pp.2 0.3 LSB 0. Integral Linearity Error 256 1 1 1 1 1 0.4 LSB 0.5 LSB * High accuracy is required only for the S/H circuit and the D/A subconverter. (S/H is to reduce the effect of signal delay differences in the large-area chip.) * Very difficult to develop a high-speed (video) and high-accuracy MOS S/H circuit.

and the second A/D subconverters. (Pipelined structure may be used) * The linearity of the complete converter depends on the accuracy of the gain matching among the first A/D.13-37 CHUNG-YU WU * The conversion rate degrades. the D/A. New structure: (4-bit conceptual structure) Subranging A/D converter using combined DAC/subtraction technique: (a) block diagram and (b) subranging process * Combined DAC/subtraction Technique * No current flows through the switches ⇒ No degradation in linearity in DAC * Amplifiors's settling time < 2 ns .

Gain Matching Linearity degration caused by gain mismatches in pipelined S/H .13-38 CHUNG-YU WU 8bit actual ADC: Block diagram of 8-bit subranging A/D converter * The 2nd ADC has a fifth bit reserved for digital correction of nonlinearity caused by both offset voltages of the second S/H circuit and the subtractor and nonlinear errors in the first A/D subconverter. * The two S/H circuits and two A/D subconverters operate in a pipelined manner ⇒ High conversion rate (≥ 2). * The resistor string has more than 10-bit accuracy.

Tsettling = 12 ns ~ 8. . * Difficult to obtain a fast-settling speed that ensures 8-bit accuracy. RSW = 100Ω ⇒ 8-bit. ⇒ Bandwidth↑. (b) waveform of clock φ and switch opening time deviation for source follower S/H. 50 MHz. Imposed by the relatively high output resistance of the amplifier and the clock feedthrough error of the MOS switch. * Poor linearity. Cc=1. * CMOS transmission gate with dummy transistor (clock feedthrough ↓) * Compensation R R R CC = F C H (1+ SW + SW ) pole-zero RI R1 RF cancellation. * Close loop configuration enhances the linearity. and (c) integratortype S/H New S/H: * Bandwidth-enhanced integrator-type S/H circuit.13-39 CHUNG-YU WU Conventional MOS S/H: SF: * The switch opening time is influenced by input voltages ⇒ severe distortion. Integrator-type S/H: * The same switch closing time.2 pF. Conventional MOS S/H: (a) source follower type S/H.5 ns for 2V step. RF = RI = 1KΩ. Bandwith-enhanced integrator-type S/H * CH=1 pF.

13-40 CHUNG-YU WU Block diagram of pipelined S/H and subtractor * The output of the subtractor is set to analog ground by closing the switch for the limiter. High-speed operational-amplifier circuit diagram .

4 (3 mV at 3V input) (FS) * ≥ 100 MHz with a 7-8 mW power dissipation. .13-41 CHUNG-YU WU Simulated linearity characteristics for S/H circuits Comparator for the second A/D subconverter * Comparators for the second A/D subconverter have an inaccuracy ≤ 1 LSB.

Effective bits and gain as a function of analog input frequency . sampling rate 50 MHz.13-42 CHUNG-YU WU Timing diagram for pipelined subranging A/D converter Experimental results: 1 µm CMOS. 5V single power supply.

241-249. New structure * No OP amps. 2. 24.: IEEE JSSC. vol.2 10-bit 5-MSPS CMOS Two-Step Flash ADC Ref. 1. Apr. * No gain block . 1989.13-43 CHUNG-YU WU §13-6. Classical two-step flash ADC * Limited by matching between the MSB ADC and DAC transitions * Limited by op-amp settling time (conversion rate) 2. pp. no.

⇒ mismatches ↓ .13-44 CHUNG-YU WU 3. Circuit implementation * Shared binary weighted capacitor array for the MSB ADC and DAC and the LSB ADC.

13-45 CHUNG-YU WU 4. ADC Performance .

. 3. Parallel processing with two 8-bit subconverters.3 The Proposed A/D Converter 1. Ÿ The proposed A/D converter with parallel processing architecture. Two-step structure with single resister ladder. (Time-interleaved ADC) 2. Using 31 dynamic coarse and 15 fine comparators for 3V Vdd design. (No op amps is required) 4. 1-bit digital error correction.13-46 CHUNG-YU WU §13-6.

13-47 CHUNG-YU WU Ÿ The proposed 8-bit A/D subconverter. Ÿ The timing diagram of a 8-bit A/D subconverter. .

Ÿ Fine comparator and its clock sequences. .13-48 CHUNG-YU WU Ÿ The circuit of the coarse comparator.

.13-49 CHUNG-YU WU Ÿ Intermeshed resistor reference ladder.

. (a) (b) Experimental Results: Ÿ Chip photograph of the fabricated A/D converter.13-50 CHUNG-YU WU Ÿ The layouts and their equivalent circuits (a) with and (b) without separated unit resistors.

13-51 CHUNG-YU WU Ÿ A typical plot of the differential nonlinearity. Ÿ A typical plot of the integral nonlinearity. .

.13-52 CHUNG-YU WU Ÿ The FFT spectrum for a 85 KHz sine-wave input signal Ÿ The effective bits versus input frequency characteristics.

8 dB 50 MHz 0.13-53 CHUNG-YU WU Table 1 Major characteristics of the A/D converter.4 to + 0. Process: Resolution: Differential nonlinearity: Integral nonlinearity: SNDR(for 85KHz input): Sampling rate: Input dynamic range: Power supply: Power dissipation: Active area: 0.6 to + 1 LSB 46.4 LSB -0.8µm CMOS 8bits -0.5V to 2.5V 3V 100 mW 4950 um × 3790 µm .

13-54 CHUNG-YU WU §13-7 Pipelined (Multistage) ADC u Need m(2N/m-1) comparators & R tapes. ² High-performance op amp is not easy to be achieved (especially for 3V Vdd). Block diagram of a pipelined A/D converter . u Need m op amps for S/H & subtractors.

: IEEE JSSC. pp. Dec. vol. 6. Two-stage pipelined ADC 3. 1. Prototype . no.1 A Pipelined 5-Msps 9-bit ADC Ref. 22. 954-961.13-55 CHUNG-YU WU Pipelined ADCs §13-7. General pipelined ADC 2. 1987.

13-56 CHUNG-YU WU .

13-57 CHUNG-YU WU Ÿ OP AMP: .

13-58 CHUNG-YU WU Ÿ Comparators: 4. Measurement results: .

26.4 DAC + ∑ + 2 SHA ⇒ MDAC .2 A Pipelined 9-Stage Video-Rate ADC Ref. pp.4.13-59 CHUNG-YU WU §13-7.126.: IEEE 1991 Custom Integrated Circuits Conference (CICC).4.

13-60 CHUNG-YU WU .

The pipeline architecture * CMOS SC implementation ⇒ conversion stage speed ∝ feedback factor ∝ (interstage gain)-1 ⇒ 1-bit/stage for power and speed optimization. Advantages: concurrent processing of analog signals ⇒ optimal speed and power dissipation ⇒ high speed and low power Disadvantage: * Inherent passive component matching problem ⇒ hard to control and yield ↓ ⇒ self-calibration and correction technique * Latency ⇒ acceptable in most applications 1.13-61 CHUNG-YU WU §13-7.3 A Single-Ended 12-bit 20 MS/s Self-Calibrating Pipeline ADC Ref. 33. Dec. pp.: IEEE JSSC vol. ⇒ simple calibration. 1998. * Transfer characteristic: The output residue voltage Vout Vout = 2Vin + D Vref D = +1 for 0 < Vin < Vref = -1 for -Vref < Vin < 0 * Digital correction technigue: Very attractive for submicron CMOS (small chip area) . 1898-1903.

the calibration consists of (1) forcing an analog input value of 0V (differential) (2) forcing the digital decision to the left and to the right of the transition.13-62 CHUNG-YU WU * The "radix = 2" overrange stage To correct residues up to 1 Vref 2 outside the nominal ±Vref range for Vin. 2. * For each calibration stage. Transfer characteristic: Vout = 2Vin + 2 ⋅ D Vref D = +1 =0 = -1 1 Vref < Vin < Vref 2 − 1 Vref < Vin < 1 Vref 2 2 − Vref < Vin < − 1 Vref 2 Lower feedback gain for the overrange stage ⇒ maximum operating frequency ↓ * Overall architecture only 3 overrange stages are used for digital correction. Self-calibration and correction algorithm * Starting from the eleventh pipeline stage and working toward the MSB stage. . The rest of the stages (12-15) are not calibrated.

* Global offset and full-scale error can be calibrated. and the last 4 LSB's are truncated for the final 12-bit output code. two coefficients for overrange stage. * All the digital correction is performed in 16 bits.13-63 CHUNG-YU WU * The calibration coefficient Memi = code_l . 3. * The single-ended to differential input S/H: . Implementation of Analog Blocks. All the correction coefficients are stored in 15 registers.code_h Vout = Vref Vout = -Vref Code_l=0 Code_h=0 ⇒ Memi = 2 ∆ Vout ≅ ∆Vin one coefficient for regular stage.

* op amp (telescopic op amp) .13-64 CHUNG-YU WU * Input common-mode fb amp.

13-65 CHUNG-YU WU 4. Measurement results DNL: INL: .

13-66 CHUNG-YU WU Spectrum: SNR & THD .

13-67 CHUNG-YU WU .

V2a. Analog IC Design. . V2c . V2c . §13-8. V2 vs. 516-523.13-68 CHUNG-YU WU §13-8 Folding and Interpolating ADC Ref. pp.1 Interpolating ADC * The number of input amplifiers (or comparators as in flash ADC) attached to Vin can be significantly reduced by interpolating between adjacent output of these amplifiers.: Johns & Martin. V2b. V2b. Logic 0 = 0V Gain of input amplifier = -10 Latch threshold = 2.5V More reference levels between V1 and V2: V2a. A 4-bit interpolating ADC with interpolating factor of 4 * Transfer response of V1. Vin: Logic 1 = 5V.

* Interpolation can be implemented by R string.25V < Vin < 0. current mirrors or capacitors.5V ⇒ correct crossing points of the latch threshold.e. i. the delays of latches must be equalized by adding series resistors.13-69 CHUNG-YU WU Possible transfer responses for the input-comparator output signals. Adding series resistors to equalize delay times to the latch comparators . And the rest of the interpolated signal responses are of secondary importance. V1 and V2. and their interpolated signals * If V1 and V2 are accurately linear between their own thresholds. ⇒ linearity ↑. * For fast operation. 0.

.13-70 CHUNG-YU WU §13-8. * Folding rate ≡ the number of output transitions for a single folding block as Vin is swept over its input range.2 Folding ADC A 4-bit folding ADC with a folding rate of 4. * The use of a folding architecture to reduce significantly the number of latch comparators (2N in interpolating ADC). * The use of analog preprocessing to determine the LSB set directly.

0000 * Total number of latches: 8 as compared to 16 in flash ADC. * Large input capacitance seen by Vin. * Examples: Vin: 0 → 1/4 V Thermometer code: 0000. V2. * Folding blocks realized by BJT cross-coupled differential pairs as an example. * No S/H is required. * The output signal frequency = input signal frequency × folding rate ⇒ limits the practical folding rate used in high-speed converter. and V4 produce a thermometer code for each of the four MSB regions.13-71 CHUNG-YU WU A folding block with a folding-rate of four. * 4-bit folding ADC architecture: MSB 2-bit: flash LSB 2-bit: folding LSB: V1. 0001. V3. 0111. (b) input-output response. . 1111 Vin: 1/4 V → 1/2 V Thermometer code: 1110. 1000. 0011. 1100. (a) A possible single-ended circuit realization.

) * Folding rate: 4. (The MSB converter would usually be realized by combining some folding-block signals.3 Folding and Interpolating ADC A 4-bit folding A/D converter with a folding rate of four and an interpolate-by-two. * Latch number ↓ Input capacitance ↓ * Capable of > 100 MHz operation.13-72 CHUNG-YU WU §13-8. * Can be implemented in CMOS. . Interpolation: 2 * V4 is a new inverted signal from V4.

A 3-bit folding converter and its cyclic code: * Folding rate N. * A practical folder has 5 amplifiers.1998 1. The structure of a folder with differential outputs. 12. full-scale sinusoid ⇒ Folded signal frequency ≈ π N ⋅frequency Fin 2 . no.13-73 CHUNG-YU WU §13-8. vol.: IEEE JSSC. 1932-1938.4 A 400-Ms/s 6-bit CMOS Folding and Interpolating ADC Ref. pp. 33. 2. Dec.

* 5 amplifiers are used * Two stages → higher gm. * Output current mode → speed ↑. The block diagram of the 6-bit converter Fig. * Resistor load → better transient performance. 5 Block diagram of the 6-bit converter 4. . The folder structure: * Folding rate: 4 Interpolation: 2 * 16 comparators and 16 folders → cyclic thermometer → 5 LSBs.13-74 CHUNG-YU WU 3.

7 (a) The contribution of the fifth amplifier goes unused. Interpolation can be used to eliminate half or more of the folder blocks Fig. (b) This redundancy is used to reduce the number of preamplifiers * Vx1 and Vx2 are fixed voltages generated by a single preamplifier shared by all folders. 8. 6. Practical folders: (a) (b) Fig. Interpolation with current-mode folder signals Fig. reducing the bandwidth of the folder circuit. . ⇒ 16 → 8 * Problems: (1) It adds an extra node to the signal path. * Power dissipation ↓. * The number of folders ↓. A current split-infour block is shown on the right. 9.13-75 CHUNG-YU WU 5. (2) It does not work readily at low power supply voltages. Interpolation with current-mode folder signals.

Fig. Comparator design (1) First stage: Fig. 10. The comparator core (a) tracking and (b) latching. * Resistor load. 12. * Current-input voltage-output comparator. A block diagram for a modified folder is also shown.13-76 CHUNG-YU WU * Improved circuit: Merge the current division within the folder. . The modified amplifier is on the right. The folder is modified to include current division. * Fast operation and low-voltage operation. 7.

(2) Second stage: .13-77 CHUNG-YU WU * Advantages: (a) Currents are summed to drive the latch (i. Iin L + Iin R) ⇒ The input signal has very little effect after latching begins.e. * Need the second-stage buffer and latch. (b) Iin L and Iin R always flow from tracking to latching ⇒ The folders are little disturbed.

(a) ADC block diagram with detail of coarse ADC. MSB = MSB .13-78 CHUNG-YU WU (3) Third stage to reduce metastability errors: SR latch 8. 16. MSB = MSB .e. * If MSB-1 = 0. (b) Coarse ADC waveforms * MSB-Lo and MSB-Hi are offset by 1 Fs at either side of the MSB 8 transition voltage. the fine converter) Fig.Hi * Can tolerate a relative offset of up to ± 1 Fs.Lo If MSB-1 = 1. 8 . Complete ADC block diagram The sync block: To suppress the delay mismatch between the coarse ADC and the rest of the circuitry (i.

18. SNDR versus input frequency at 400 Msample/s .13-79 CHUNG-YU WU 9. Measurement results: Fig.

13-80 CHUNG-YU WU Fig. Die photo . 19.

13-81 CHUNG-YU WU §13-9 Summary 16 [5] 15 Resolution (Bits) 14 13 [2] 12 [6] 11 10 9 8 [1] 10 30 320 330 210 190 Conversion Rate (KHz) Resolution versus sampling frequency plot of recently reported CMOS audio A/D converters 50 600 620 [9] [4] [3] [7] [8] CHUNG-YU WU 13-81 .

T3 12 * * (250mW).3V : 3V : 2V : 2. T1) * (76mW. [28]* (307mW) T4&T5 T5 (135mW) (80mW) (1. T2 [36] [22] T2. T3 (200mW. [21] 11 10 T1: Full Flash T2: Two-step flash or Subranging T3: Pipelining T4: Interpolating T5: Folding T6: Parallel T7: Over sampling Resolution (bits) 9 [17] (350mW. T6) [11] [14] (600mW. [20] [18]. T3 (135mW) CHUNG-YU WU *: 5V : 3. T2) * * * [35] (195mW). T3) [23] [25] [10] (225mW) [29]. T2) T1.1W. T3 [34] (35mW) (135mW) T3. T5 8 * [16] (200mW. T3 [24]. T2) [15] [33] (335mW). T1) 5 10 20 30 40 50 60 70 80 Conversion Rate (MHz) 90 Resolution versus sampling frequency plot of recently reported CMOS video A/D converters 13-82 .13-82 13 * [30] (166mW). T2) * * * T4 (160mW) [27] T1 (110mW) [26] T1 T3&T7 (190mW) (225mW) [32] [37] [31] (200mW) T4&T5 125 175 200 300 400 500 CHUNG-YU WU 7 6 *[12] (400mW. T2.5v (900mW) [19]. T2 (85mW) T3 & T6. (75mW) (135mW) * [13] (250mW.

F. [7] B. 1984. A. Solid-State Circuits. P. 12.828-836. Gray. pp. G. 8. Solid-State Circuits..1988. " A low-power 12-b analog-to-digital converter with onchip precision trimming. [2] [3] [4] [6] [8] [9] [10] C. vol. 1994. " A16-b 320-KHz CMOS A/D converter using two-stage thrid-order Σ∆ noise shaping. vol. Li. Dec. P." IEEE J. July 1992. Castello. " A ratio-independent algorithmic analog-todigital conversion technique. 1994. 29. pp. " A self calibrating 15-bit CMOS A/D converter. 4. pp. SC-19. Solid-State Circuits. 6. " A 12-b 600Ks/s digitally self-calibrated pipelined algorithmic ADC. Vertreg. vol. Cline. vol. Feb." IEEE J. R.1200-1203. . pp. 1993. vol. D. no." IEEE J. 1993. pp. 640-647." IEEE J. Chin. Vandemeulebroecke. 1993.28.813-819.13-83 CHUNG-YU WU [1] H. "A cyclic A/D converter that does not require ratiomatched components. Solid-state Circuits.1514-1523. T. and K. A/D converter for embedded application. [11] Shu-Yuan Chin and Chung-Yu Wu. Lee. Yin.29. 1984. June 1993. 455-461. Apr. R." J. no. P. T. Apr. Shu-Yuan Chin and Chung-Yu Wu. Gray. A. Reyhani and P. S. 28. D. Solid-State Circuits. Tateishi. Solid-State Circuits. and M. and W. Lee. 29. pp. " A CMOS 13-b cyclic RSD A/D converter. Hodeges. 509-515. J. J. R. Solid-State Circuits." IEEE J. " A 25-Ms/s 8-bit CMOS . and P. May 3-6. Gray. vol. Apr. " An 8-b 85-Ms/s parallel pipeline A/D converter in 1-um CMOS. J. Jespers and A. Tamaru. Tan. Ginetti. vol. quinlan. no. [12] H. no. no. K." IEEE J. Dec." 1993 IEEE International Symp. and P. "A 3 V 8-bit 50-Msample/s A/D Converter. C. vol. 152-158.1994. 23. K. pp. 8. vol.957-964. Solid-State Circuits. no. M. Solid-State Circuits.447-454. Dec. H. pp. Solid-State Circuits. Sansen. "A ratio-independent and gain insensitive algorithmic analog-to-digital converter." IEEE J. Dijkstra. Ritoniemi et al. Solid-State Circuits." IEEE J. SC-19. vol. [13] M. Solid-Dtate Circuits. Solid-State Circuits. W. 28. Aug." submitted to IEEE J. pp.873-878." IEEE J. G. de Wit. S.A. B. and R. H.27. Chicago. Stubbe. A. pp. U. Conroy. Pelgrom. Ondera." IEEE J. M. " A 5V 6-b 80Ms/s BiCMOS flash ADC.879886. W. Hester. 1994. no. M. 7. no. S. V Rens. pp. 4. G. S. vol. on Circuits and Systems. [5] M. R. 29. IEEE J. pp. " A stereo audio sigma-delta A/D converter.S. vol. 4. Aug.

[15] B. J. 80-mW." IEEE J. vol. vol. pp. Etoh. 3.1667-1678. Ishikawa and T. 3 V-supply A/D converter for PRML read channel LSI. vol. 12. Doernberg. "A 2. 938-944. Solid-State Circuits. vol. S. [16] A. 1993. 2. vol. 12. Hotta. R. Tsukahaara. 1995. Hodges. "A 10 b." IEEE J. Dec. J. 1995. [17] J. . 1831-1836. Gray and D. 10 b. 11. W." IEEE J. pp. G. 35 mW pipelined A/D converter. 30. Allstos. 1996. no. [26] S. Solid-State Circuits. Dec. Dec. " A 10-bit 5-Msample/s CMOS two-step flash ADC.5-V." IEEE J. 3." IEEE J. Mar. SolidState Circuits. "A 12-b 5-Msample/s two-step A/D converter. 28. pp. 3. Dec. 12. 7. 1854-1861. 1994. pp.1531-1536. 6 b. A." IEEE J.. "A 175 Ms/s. P. "An 80-MHz. no. vol. no." IEEE J. R. 1989. no.3 V CMOS A/D converter. 1996. [18] M. Venes. no. Nauta and A. 5-Msample/s pipelined CMOS ADC. pp. pp. Sc-20.1985. 24. Cho. pp. vol. 1485-1491. and D. 12. Lee. Dec. 173-183. 29. 1138-1143. no. 30. [24] P. Roover and M. F. vol. "A 2 V.13-84 CHUNG-YU WU [14] M. 160mW. no. Nov. R. 292-300. Dec. Venes and R. vol." IEEE J. 12. Solid-State Circuits. C. Gray. Solid-State Circuits. Hirata. SolidState Circuits. pp. 12. vol. 29. Yotsuyanagi et al. no. pp. T. 1846-1853. and K." IEEE J. vol."A 70-Ms/s 110mW 8-b CMOS folding and interpolating A/D converter. Dingwall and V Zazzu. "A CMOS 6-b. [20] T. 10b. Solid-State Circuits. van de Plassche. [21] K.31. [25] A. SolidState Circuits. 24. no. pp.1989. Solid-State Circuits. . [22] M.. 241-249. pp. 1995. July 1996. no.. Steyert. 30. Solid-State Circuits. pp. Dec. 31. no. Solid-State Circuits. "An 8-bit 50-Mhz CMOS A/D converter. S. Apr. 166-172. no. 31." IEEE J. Solid-State Circuits.1533-1537. Razavi and B." IEEE J. " A 10bit 20 Ms/s 3V supply CMOS A/D converter. Nakamura. [23] B. Dec. no. vol." IEEE J. 30. G. vol. 20 Msample/s. Mar. 1996. L. 40 Msample/s CMOS parallel-pipelined ADC. Mar. [27] R. no. " An 8-MHz CMOS subranging 8-bit A/D converter. Carley. pp. 6. [19] M. B. 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing. Solid-State Circuits. pp." IEEE J. 12. Yotsuyanagi. A. M. "An 85 mW. mixed-mode subranging CMOS A/D converter. J. " A 10-b 50-MHz pipelined CMOS A/D converter with S/H. 1995. 3. Ito et al. G. Solid-State Circuits. P. 1302-1308. 1992. W. Yu and H. Wolley. 200 Msample/s. Tsukamoto et al. vol." IEEE J.31. 20 Msample/s. 12-b.

1996. 912-920. Allstot. and T. 1932-1938." IEEE J. 12. 3. P.5 effective bits at nyquist. 31. [32] S. Wong. 12. 1248-1257." IEEE J. Mehr and D. CMOS. Dec. Dec. Endo. Lewicki. 33. 25-Msample/s two-step ADC in 0. Tsukamoto. Solid-State Circuits. 33. 1803-1811. G. vol. Solid-State Circuits. Flynn and B. 1998. "A CMOS 6-b. Solid-State Circuits. 6-bit nyquist-rate ADC for disk-drive readchannel applications. M. "A continuously calibrated 12-b. 1999. pp. vol.2/spl mu/m CMOS. 1998. Ingino and B. pp. no. "A 500-Msample/s. [29] M. vol. Meng. Solid-State Circuits. P. pp. Wooley. 9." IEEE J. no.13-85 CHUNG-YU WU [28] C. D. A. 1920-1931. Mar. [35] H. Solid-State Circuits." IEEE J. 400-Msample/s ADC with error correction. no." IEEE J. 1132-1140. Solid-State Circuits. no. pp. no. vol. R. 12. W. . [37] I. Solid-State Circuits. and B." IEEE J. 33. "A 400-Msample/s. pp. Solid-State Circuits. vol. no. [33] J. Y. 34. pp. W. "A 75-mW.3-V 10-b. Dec. Aug. pp. pp. "A 3." IEEE J. Dec. Gray. no. L. 1998. Portmann and T. 294-303. Dec. Solid-State Circuits. no. Dec. 10-Ms/s. [36] B. pp. 34. H. 1996. 10-b. J. Brandt and J. L. [30] D. [31] M. 3. Schofield. 12. 1996. Lutsky. [34] I. 12. 34. P. E. vol. no. 12. Remmers. Cline and P." IEEE J. "CMOS folding converter with current-mode interpolation. 1999. Flynn and D. vol. 12. vol.35-um . 1999.3-V A/D converter. C. "A power optimized 13-b 5 Msamples/s pipelined analog-todigital converter in 1. no. Solid-State Circuits. Sep. 8. 6-b CMOS folding and interpolating ADC. pp. 1788-1795. vol. 20-MSPS CMOS subranging ADC with 9." IEEE J. van der Ploeg and R. 1939-1947. Dec. Dalton. "A single-ended 12-bit 20 Msample/s selfcalibrating pipeline A/D converter. 1998. 33. 31. 18981903. Opris." IEEE J. "Power-efficient metastability error reduction in CMOS flash A/D converters. vol. 31. Sheahan.

MOS Switched-Capacitor Filter Design §14--1 Preliminary Considerations §14-1. Input x(t) Loss Ampt. discrete-time.: SCF discrete-time system e.: analog Filter differential equations sampled-data system e. T Input x(kt) t Output y(t) τD τD Output y(kt) t Output y(kt) τD t k: integer continuous-time system e.I. and sampled-data systems Ampt.q. Tine-invariant systems and causal systems T. Causal : x(mt) => y(kT)=0 for k<m 3.q. Continuous-time.q. T Input x(kt) Loss Ampt.14-1 CHUNG-YU WU CH 14. : x(kt)→ y(kt) => x[(k-n)T]→ y[(k-n)T] for any x(kt) and n.: digital filter difference equations 2.1 Classification of systems and filters 1. Filter types: (1) Low-Pass(LP) Kω p 2 H ( jω ) dB -N*20dB/decade N: order H(s)= 2 S 2 + (ω p / Q p ) S + ω p Ideal (biquad) Two complex poles (LHP) ωp ωs ω .

gain: k center freq.14-2 CHUNG-YU WU (2) High-Pass(HP) KS 2 H(s)= 2 2 S + (ω p / Q p ) S + ω p Two complex poles(LHP) Two zeros at S=0 H ( jω ) 3) Band-Pass(BP) H(s)= K (ω p / Q p ) S dB -3dB +N*10dB/decade N: order ωp Qp -N*10dB/decade N: order 2 S 2 + (ω p / Q p ) s + ω p center freq. ωp Two complex poles (LHP) One zeros at S=0 4)Band-Reject(BR) K ( S 2 + ω z2 ) H(s)= 2 2 S + (ω z / Q p ) s + ω p ωp=ωz Two complex poles(LHP) Two imaginary zeros ωs1 ωp1 ωp ωp2 ωs2 ω H ( jω ) dB ωz ω ωp>ωz High-Pass Notch filter (HPN) ωp<ωz Low-Pass Notch filter (LPN) (5)Low-Pass Notch (LPN) (6)High-Pass Notch H ( jϖ ) dB 0dB H ( jϖ ) dB 0dB ωp ωz ω ωz ωp ω .

14-3 CHUNG-YU WU (7)ALL-Pass (Delay Equalizer) H(S)= 2 S 2 − (ω p / Q p ) S + ω p 2 S 2 + (ω p / Q p ) S + ω p 0dB Gain -180o phase ωp ω Two complex poles (LHP) Two complex zeros (RHP) mirror-imaged §14-1. k=±integer base-band spectrum .2 Sampling Process § ideal impulse sampling: S(t)= S δ (t)= k = −∞ multiplier x(t) xd(t) ∑ S (t − kτ ) ∑ δ (t − kτ )= ∞ ∞ τ: sampling period xd(t)=x(t)S δ (t)=x(t) remember: K = −∞ k = −∞ ∑ x(t )δ (t − kτ ) ∞ S(t)=Sδ(t) for ideal impulse sampling ∫ ∞ ∞ −∞ δ (t − kτ )dt = 1 δ (t − kτ ) =0 for t ≠ kτ => xd(t)= ∑ x(kτ )δ (t − kτ ) k = −∞ Fourier transformation of S δ (t): SF(t)= ∑ ck e jkω st k = −∞ ∞ ωs ≡ 2π τ Where Ck ≡ τ∫ ∞ 1 τ 2 τ − 2 s(t) e jkω st dt= s 1 τ =>xd(t)=x(t)SF(t)= ∑ Ck x(t )e jkω t k = −∞ F[xd(t)]=F[ ∑ Ck x(t )e k = −∞ ∞ k = −∞ ∞ jkω s t ]= k = −∞ ∑ C F [ x(t )e k ∞ jkω s t ] = ∑ C k X(jω-jkωs) where F[x(t)] ≡ X(jω).

Reconstruction filter is also required to recover x(t). spec H ( jω ) Transition band Pass band −ωs+ωc −ωc 0 ωc ωs-2ωc The smaller the ωs-2ωc (TB). τ instants apart( τ = 2π / ws ) 2ωc: Nyquist rate. Anti-aliasing filter is required.14-4 CHUNG-YU WU X(jω) Aliasing: introduces an ambiguity into X(jω-jkωs) and prevents the eventual recovery of X(jω) −ωc 0 ωc X(jω-jkωs) ω ωs<2ωc −ωs−ωc 0 ωc ωs X(jω-jkωs) no aliasing 2ωc ω ωs>2ωc −ωs −2ω c −ωc 0 ωc 2ωc ωs ω Sampling Theorem: A function x(t) that has a Fourier spectrum X(jω) such that X(jω)=0 for ω ≥ ω s 2 is uniquely described by a knowledge of its values at uniformly spaced time instants. the higher the filter order! Stop band ωs-ωc ω .

sampled data (or discrete-time) system: y(k τ ) + ∑ bn y[(k-n) τ ] = ∑ an x[(k-n) τ ] n =1 n =0 N M M. linear. time-invariant. we have sin α / α envelope onto X (jω-jkωs) α ≡ kω s a / 2 Pulse Amplitude Modulation (PAM) τ 2τ §14-1.N: non-negative integers .3 Z-Transformation xd(t)= ∑ x(kτ )δ (t − kτ ) k = −∞ ∞ 3τ 4τ t Laplace Transformation=> Xd(s)=L[xd(t)]= ∑ x(kτ )e −ksτ k = −∞ ∞ Let z=es τ S=jω z=e jωτ => X(z)= ∑ X (kτ )z −k two-sided z-transform k = −∞ ∞ ∞ X(z)= ∑ X (kτ )z −k k =0 ∞ K =0 one-sided z-transform 1 1 − z −1 z >1 1 1− e − aτ example 1: x(t)=u(t)=>x(k τ ) = 1 =>X(z)= ∑ Z −k = ∞ example 2: x(t)=e-atu(t)=>x(k τ ) = e − akτ =>X(z)= ∑ e -akzz-k= k =0 for z >e-a τ z −1 For single input/output.14-5 CHUNG-YU WU § Finite -Pulse Sampling (non-ideal sampling): Sp(t)= ∑ [u (t − kτ − ) − u (t − kτ + )] a>0 k = −∞ ∞ a 2 a 2 a 1 Ck= τ∫ 1 τ 2 τ − 2 Sp(t) e − jkω st dt e − jkω t dt = s = τ∫ 1 a 2 a − 2 a Sin(kω s a / 2 τ kω s a / 2 τ 2τ 3τ 4τ xd(t) t Now.

. - ∞ <σ< ∞ => overlap on Z-plane ∠Z = π → 3π 2 2 * ω=ω1..(1 − α N Z −1 ) Mapping between Z-plane and S-plane: z=esτ s=σ+jω => z=eστ ejωτ τ= 2π z=αi: poles z=βi: zeros ωs ωs ≤ ω ≤ ω s / 2 is 2 For ωs>2ω0... - ∞ <σ< ∞ => all Z-plane ∠Z = −π → π 2 ω 3ω − s ≤ ω ≤ − s .− sufficient to determine X(jω) for all ω. * − ωs ≤ ω ≤ ω s / 2 ..... - ∞ <σ< ∞ => a straight line from z=0 to z= ∞ with angle ω1τ * jω axis => σ=0 => z =1 unit circle *σ>0 *σ<0 z >1 for all ω => RHP → outside the z = 1 circle z <1 for all ω => LHP → inside the z = 1 circle ...14-6 CHUNG-YU WU Two cases:(1) bn = 0 for all n => nonrecursive system M+1 tap transversal filter Finite-Duration Impulse Response(FIR)Filter (2) bn ≠ 0 for n ≥ 1 => Nth-order recursive system Infinite Impulse Response(IIR) Filter z-transform: Y(z)(1+ ∑ bn Z −n ) =X(z) ∑ a n z −n n =1 n =0 N M Y ( z) H(z)= = X ( z) ∑a n =0 N n =1 M n z −n 1 + ∑ bn z pulse transfer function −n ao (1 − β 1 Z −1 )(1 − β 2 Z −1 ).. - ∞ <σ< ∞ => overlap on Z-plane ∠Z = −3π → −π 2 2 ωs 3ω ≤ ω ≤ s .. the base-band response X(jω) over the range.(1 − β N Z −1 ) = (1 − α 1 Z −1 )(1 − α 2 Z −1 ).

diverging unstable (2)a=1 sequence of 1's unstable stable (3)a ≥ 0 a<1 (4)-1<a ≤ 0 (5)a=-1 (6)a<-1 stable σ<0. ω=0 - ∞ <σ<+ ∞ => Real Z axis (positive) jω First-order transfer function: H(z)= 1 Z=a is the pole 1 − az −1 ω1 τ2 h(kτ) k=0. 1. 2. z=a=eστejωτ (1)a>1. ωτ=±π ωkτ=±kπ unstable unstable τ1 0 σ stable region ImZ τ2 ω 1τ τ1 Z =1 Ro Z G(ω)=20log[ H (Z ) z=ejωτ ] dB φ(ω)=tan-1 Re H ( Z ) Im H ( Z ) magnitude phase z=ejωτ rad The magnitude and phase can be determined graphically in the same way as those determined from the s-plane poles & zeros. 3.14-7 CHUNG-YU WU * S=0 z=1 .……. §14-1.4 Sample and Hold Circuit Zero-order hold or S/H function: Ho(s)= 1 − e − sτ sτ sin(ωτ / 2) Ho(jω)=e-jωτ/2 ωτ / 2 .

gain amps or infinite gain OP amps. should be considered as & second order effects. & non-ideal cap. . ideal switches & sampled-data voltage inputs. * The input may be a continuous one. non-ideal OP amps. §14-2 Switched-Capacitor Network System General Switched-Capacitor Network (SCN): ideal capacitors. indep. not multiple. * The effects of non-ideal switches. * Typically. the sampled-data voltage input is only single.u(t-τ) τ τ 1 1 t π ωS − 2ω S 2ω S −ωS ω x(t ) τ x(k ) xr(t) xr(t)=x(t) h0(t) t −π * may serves as a reconstruction circuit Xr(jω)=Xd(jω)Ho(jω) * The different between Xr(jω) & Xd(jω) at ω ≅ ±ωc can be eliminated by setting ωs/ωc>>1. ideal voltage-controlled-voltage sources (VCVS's). VCVS: freq.14-8 CHUNG-YU WU X d ( jω ) h0(t) 1/τ X r ( jω ) H 0 ( jω ) Impulse response − 2ω S −ωS − ωC + ωC ∠H O ( jw) ωS 2ω S ω τ ho(t)= u(t).

Analysis thus can be performed. SCN is time-variant since the network topology is different in the case of φe and φ°.14-9 CHUNG-YU WU Block diagram: (S/H)i Continuous Anti-aliasing Filter φ φ SwitchedCapacitor Network (S/H)o Continuous Reconstruction Filter φ φ φ φ Switched-Capacitor Network (Two-phase clock) (can be multi-phase) General symbols: φe φo e o e V2 ( kT ) o V1 ( kT ) C ≡ V1 (kT ) C V2 (kT ) ≡ V1 (kT ) C V2 ( kT ) φ e even clock Tc Tc 1T 2T 3T t odd clock Tc<T to avoid overlapping of φe and φ° φ o Tc Tc τ: sampling period τ=2T t * Generally. if we separate the input/output sampled-data voltage into one even component and one odd component and separate the whole SCN into one even part and one odd part. then we have two time-invariant networks coupled together. However. .

14-10 CHUNG-YU WU Sampled-Data Waveforms 1. Return-to-zero waveforms va e va ≡ 0T 0T 1T 2T 3T 4T 5T t 1T 2T e 3T 4T 5T t va o V (t ) + − o Va (t ) 0T 1T 2T 3T 4T 5T t e V (t ) + − o Vb (t ) Va(z)=Vae (z ) + Va0 ( z ) = Vae (z ) Similarly. we have Vd(z)= Vde (z)+Vd0 (z) . Full-clock-period (Full-cycle) sample-and-hold waveforms vc vc (t) o vc 1 T 2T 3T e 1T 2T 3T 4T 5T t 4T 5T t 1T 2T 3T 4T 5T t Vc(z)= Vce (z)+ Vc0 (z) V (z)=Z 0 c − 1 2 Vce (z) (Q Vc0 (kT)= Vce [(k-1)T]) Similarly. we have Vb(z)= Vbe (z ) +Vb0 ( z ) = Vb0 ( z ) Va0 ( z ) =0 Vbe (z ) =0 2.

vd − Full-cycle S/H circuit §14-3 Filter Design Process 1. Specification (1) Low-Pass Filter Specification: H ( jω ) TransitionBand TB S Stopband SB Start S : PB _ ripple Specification Gain dB Passband PB SB attenuation No Satisfied ? ωO ω S Cutoff − frequency Actual − filter − response ω Yes Approximation Stopband − frequency Satisfied ? No Yes delay sec Realization Satisfied ? No Yes Stop actual − delay − function ωC ω .14-11 CHUNG-YU WU V (z)=Z Vd0 (z) φ or φ e d − 1 2 V (t ) + + C − vc .

Realization Two methods: (1) Realization of the biquad (2nd order filter)and the first-order filter=>cascade or couple them to form a high-order filter.14-12 CHUNG-YU WU (2) Band-Pass Filter SB H SP TB L PB TB H ω SL ω CL ω CHω SH ω 2. Elliptic d.Approximation (1) Classical approximation a. (2) Realize H(s) using LC network=>replace L by some integrated-circuit simulator or simulate the LC network using integrators. * Low-sensitivity. Bessel (2) Modern approximation 3. Chebyshev c. high-performance . Butterworth b.

14-13 CHUNG-YU WU §14-4 SC Integrators via OP AMPS §14-4. C1=10PF => R=1MΩ =>SC simulated positive resistor Switch realizations: φo orφe φo orφe φo orφe ⇒ − VSS E/D NMOS or + V DD − VSS φo orφe The inverting SC integrator vin R C − + vout ⇒ vin φe φo C1 φe φo C2 − + vout Operation: (1)φo phase .1 SC Inverting Integrator φo(φe): Vc1=0 φe(φo): Vc1=V1 -V2 ∆Q=C1(V1-V2) φ e (φ o ) i V1 φ o (φ e ) + VC1 − φ e (φ o ) V − V2 V − V2 ∆Q ≡ i = C1 1 = C1 f (V1 − V2 ) ≡ 1 T T R 1 f: clock frequency =>R= C1 f C1 V2 φ o (φ e ) f=100KHz.

14-14 CHUNG-YU WU + + − − C2 vin − C1 + vout (2)φe phase + + + + vin + + C1 − − − − − C2 − − + vout φe n −1 n n +1 t φo t vin + 1V t vout 0V vout (Tn ) vout (Tn+1 ) { vout (Tn −1 ) t { { C1 (1V ) C2 .

14-15 CHUNG-YU WU "Ideal OP AMP" Vout(Tn)=Vc2(Tn)=Vout(Tn-1)=> C1 Vin(Tn) C2 Vout (Tn ) − Vout (Tn −1 ) C 1 = − 1 Vin (Tn ) = − Vin (Tn ) T TC 2 R1C 2 d 1 1 1 Vin Vout = − Vin = − Vin = − 1 dt R1C 2 C 2 )( 1 ) C2 ( C1 f C1 f High-precision integrator time constant RC= C2 1 C1 f => Z-domain Expression: Vout (z)=Vout(z)Z-1- =>H(z) ≡ C1 Vin(z) C2 Vout ( z ) (C C ) = − 1 −21 (1 − Z ) Vin ( z ) 1 − Z −1 T Backward Euler Transformation: S→ H(S)=- 1 1 =− (C 2 / C1 )TS R1C 2 S Parasitic-Free structure: vin C P1 φe φo C1 φe CP4 C2 − + C P 2 C P3 φo vout C P6 C P5 .

14-16 CHUNG-YU WU §14-4.2 Non-inverting SC Integrator φe(φo) : Vc1=+V1 φo(φe) : Vc1=-V2 ∆Q=C1(-V1-V2) V + V2 ∆Q = i = −C1 1 T T −CV +V If V2=0 =>i= 1 1 = 1 T R 1 T => R=- = − C1 C1 f i φ e (φ o ) V1 φ o (φ e ) + VC1 − φ o (φ e ) C1 V2 φ e (φ o ) => SC simulated negative resistor! The non-inverting SC integrator: −R C − + vin vout ⇒ vin φe φo C1 φo φe C2 − + vout Operations: (1)φe phase C2 − − (2) φo phase − − vin + + − + C1 vout vin + + C1 − − C2 + + − + vout Vout (Tn)=Vout(Tn-1)+ d 1 Vout = Vin dt R1C 2 C1 Vin (Tn−1 ) C2 => => Vout 1 1 = (s) ≡ H (s) = Vin R1C 2 S C 2 1 S C1 f .

** Need common-mode feedback or common-mode bias circuit . φe V BIAS φo C vin + αC + − + vout vout − + V BIAS − αC vin − C * Better noise rejection * Better CMRR and PSRR * Better Frequency response * Better slew rate ** More components (switches. OP AMPs) ** Thermal noise ↑ due to the added components and switching operations.14-17 CHUNG-YU WU Z-domain expression: C1 ) Vout ( z ) C2 = H(z) ≡ Vin ( z ) 1 − Z −1 Z −1 ( Forward Euler Transformation: S→ H(s) ≡ + ( 1 C2 )TS C1 =+ 1 R1C 2 S 1 − Z −1 TZ −1 Simpler non-inverting integrator! §14-5 Fully Differential-Type SC Integrators Using OP AMPs. capacitor.

14-18 CHUNG-YU WU §14-6 SC Differentiators Using OP AMPs R C1 − + Vin Vout Inverting: φo C Vin φe C1 − + V'out φe Vout ' Vout(Tn)=Vout (Tn)=- C1 [Vin (Tn ) − Vin (Tn −1 )] C =>H(z)=- C1 (1-Z-1) C 1 − Z −1 T 1 R= cf Backward-Euler Transformation: S→ H(S)=-S Noninverting: C1 C 1 T = − S 1 = − SRC1 C C f φo 1 φo CC − CC + C Vin φe C1 − + Vout .

14-19 CHUNG-YU WU φo 2 C φe C1 − + + v out v out − + − C H(z)=+ C1 (1 − Z −1 ) C φo Differential-Type SC Differentiator: φo vin vin − + φe φe C1 C1 C − + + vout v out − + − C φo Characteristics of SC differentiators: 1. No high-frequency-noise problem as in continuous-time differentiators.sc-24. Can be used to design filters as SC integrators. 4. No dc instability problem as in SC integrators. 1989. Parasitic-free structure. 2. 3. . pp. Ref: IEEE JSSC vol.177-180.

[(K1+K2S)Vin+( 1 S 1 S S 2 + ω 0 ) • Vout Q Wo ) • Vout+ ωo • V1) Q where V1= [(Ko/ωo) • Vin+ωo • Vout] − ω0 Vin − K0 1 − S V1 K1 + K 2 S ω0 ω0 Q − 1 S Vout ω0 Step2: Active-RC design CA = 1 − 1 Vin − ω0 ω0 1 Q ω0 K0 − + 1 K1 ω0 CB = 1 − + Vout K2 .1 Low-Q SC Biquads Step 1: Flow diagram generation. S2Vout=-[K2S2+K1S+Ko] Vin-(ωo =>Vout=.14-20 CHUNG-YU WU §14-7 The Design of SC Biquads (Second-Order Filter) H(S)= − (K 2 S 2 + K 1 S + K o) S2 + ωo S + ω 02 Q = Vout (s) Vin (s) §14-7.

change to Z-domain diagram) -C2Z-1 C4 Vin -C1Z-1 -1/CA 1-Z-1 C1'+C1"(1-Z-1) C3 -1/CB 1-Z-1 Vout .14-21 CHUNG-YU WU Step 3: SCF C2 CA=1 φ2 Vin φ1 C1 φ2 C4 OP1 + C1' C1" C3 φ2 φ1 φ2 CB=1 φ2 φ1 - φ1 OP2 + - φ2 Vout C1 = T * Ko/ωo= Adc * ωo * T= Adc C2 = C3=ωo * T= C4 = (ωo * T/Q)= 1 x 1 x Adc ≅ Ko ωo 2 C 1 Q = A (not suitable for high Q) => Qx ω oT C 4 1 C1'= K1 * T =K1 C1" = K2 1 CA/C2= ω oT X= 1 ω oT ωo x => fo= fs fo: center (cutoff) frequency 2πx Step 4: refinement Z-domain block diagram (If the accuracy is not good.

each op-amp and its feedback capacitor (CA or CB) is replaced by its voltage-to-charge transfer function.g. the exact transfer function is Vout ( z ) (C1 '+C1 " ) z 2 + (C1C3 − C1 '−2C1 " ) z + C1 " = − Vin ( z ) (1 + C 4 ) z 2 + (C 2 C3 − C 4 − 2) z + 1 As compared to H(z) specifications. Qout ( z ) V ( z) ⋅ C − 1 / Cf = = out −1 1− z Vin ( z ) Vin ( z ) Here Cf is the feedback capacitor. C3. Similarly. C2) -C * z From the block diagram.a1=-a2 C1=C1'=0 K0=K1=0 a0=a2= C1'=0 K1=0 a2=a0 a1 2 . C * (1-z-1) for an unswitched capacitor (e.14-22 CHUNG-YU WU C1" = a0 C1' = a2-a0 C1 = 1/C3 * (a0+ a1+ a2)= 1 (2C1"+C1'±a1) C3 C4 = b2 -1 C2 * C3 = b1 + b2 + 1 C2=C3 In this diagram. C1") C for a non-inverting capacitor (C1'. a 2 * z 2 + a1 * z + a0 H(z) = b2 * z 2 + b1 * z + 1 TYPES L-P CASE B-P CASE H-P CASE NOTCH CASE COEFFICIENTS C1'=C1"=0 K1=K2=0 a0=a2=0 C1=C1"=0 K0=K2=0 a0=0. C4) -1 for an inverting capacitor (C1. the capacitances can be determined.

2 High-Q SC Biquads ω0 K1 ω0 S -ω0 1 1 S Q Vin 1 K0 ω0 -1 S 1 -1 S 1 Vout K2S V1 Vout =- [K2SVin-ω0V1] Where V1=- [( 1 S 1 S K0 2. SCF C2 φ1 C1 ' C4 CA = 1 CB = 1 φ2 vin φ2 φ1 C1 φ1 φ2 − + φ2 C1 '' C3 φ1 φ2 φ1 − + vout .14-23 CHUNG-YU WU §14-7. Active-RC design 1 Q ω0 + ω0 K1 S )Vin + (ω 0 + S )Vou t ] Q K1 ω0 CA = 1 − 1 ω0 CB = 1 Vin ω0 − K0 + OP1 − 1 − + ω0 OP 2 Vout K2 3.

14-24 CHUNG-YU WU C1=K0 T/ω0 = ( C2 ≅ C3 ≅ ω0T C4 ≅ 1 Q K0 ω0 2 )ω oT = Adc ω 0T (instead of Q ) ω 0T C1' ≅ K1/ω0 C1" ≅ K2 4. Z-domain block diagram of a high-Q biquad: C2 + C1 (1 − Z −1 ) '' C 4 (1 − Z −1 ) + + − C 3 Z −1 −1 CA 1 − Z −1 V1 C1 (1 − Z −1 ) '' Vin C1 + −1 CB 1 − Z −1 Vout C1 " Z 2 + (C1C3 + C1 ' C3 − 2C1 " ) Z + (C1 "−C1 ' C3 ) H(Z)= − Z 2 + (C 2 C3 + C3C 4 − 2) Z + (1 − C3C 4 ) Choose C2=C3 Coefficient matching: C1"= a2 b2 ao a − ao ) / C3 = 2 b2 b2 c3 C1'=(C1"- C1=(a1/b1-C1'C3+2C1")/C3=(a0+a1+a2)/(b2c3) C4=(11 ) /C3 b2 C32=C22=(b1/b2-C3C4+2)=(b1+b2+1)/b2 .

2 S + 1 A fc: CENTER FRE.2 S + 1 fc: CENTER FRE.2 f s f = c 2 •π • C A Example 2: Low-Q Bandpass SCF Biquad C2 C4 CA CB φ1 φ2 vin φ2 φ1 φ2 φ1 − + φ2 C ' 1 C3 φ1 4 φ1 φ2 − + vout CA=CB=6. C2=1 C3=1 C4=1.3 C1'=2 H (S ) = S 2 + 1 .3 C1=4 H (S ) = S 2 + 1. fs: SAMPLING FRE.3 Design Examples Example 1: Low-Q Lowpass SCF Biquad C2 C4 φ1 φ2 CB CA vin φ2 φ1 C1 φ2 φ1 − + φ2 C3 φ1 4 φ1 φ2 − + vout CA=CB=6.14-25 CHUNG-YU WU §14-7. fs: SAMPLING FRE. C2=1 C3=1 C4=1.2 f s f = c 2 •π • C .

14-26 CHUNG-YU WU Example 3: High-Q Low-pass SCF Biquad C2 φ1 φ2 φ2 Vin C1 CA C4 C3 CB φ2 φ1 φ1 + φ2 φ1 φ2 φ1 + Vout CA=CB=6. fs: SAMPLING FRE. .2 f s fc = 2 •π • C A fc: CENTER FRE.3 C '1=2 H (S ) = 2S S 2 + 1.2 S + 1 C2=1 C3=1 C4=1.25 C2=1 C3=1 C4=1.2 f s fc = 2 •π • C A fc: CENTER FRE.3 C1=4 H (S ) = 4 S S2 + +1 5. fs: SAMPLING FRE. φ1 φ2 Example 4: High-Q Band-pass SCF Biquad C2 C'1 CA C4 C3 CB Vin φ2 φ1 + φ2 φ1 φ2 φ1 + Vout CA=CB=6.

6 Hz CALCULATED ○ COMPUTED BY SWITCH CAP × EXPERIMENTAL .14-27 CHUNG-YU WU Frequency response of low-Q Low-pass SCF biquad CENTER FREQUENCY: 1K Hz SAMPLING FREQUENCY: 39.

6 Hz ○ COMPUTED BY SWITCH CAP × EXPERIMENTAL .14-28 CHUNG-YU WU Frequency response of low-Q Band-pass SCF biquad CALCULATED CENTER FREQUENCY: 1K Hz SAMPLING FREQUENCY: 39.

14-29 CHUNG-YU WU Frequency response of High-Q Low-pass SCF biquad CALCULATD CENTER FREQUENCY: 1K Hz SAMPLING FREQUENCY: 39.6 Hz ○ COMPUTED BY SWITCH CAP × EXPERIMENTAL .

6 Hz ○ COMPUTED BY SWITCH CAP × EXPERIMENTAL .14-30 CHUNG-YU WU Frequency response of high-Q Band-pass SCF biquad CALCULATED CENTER FREQUENCY: 1K Hz SAMPLING FREQUENCY: 39.

Flow diagram ω0 Vin K0 + -1/S Vout K1S 2. SCF φ1 φ1 C2 C'1 φ2 CA φ1 φ2 C1 ≅ K1 C1' ≅ TK0 C2 ≅ ω0T fc= fs 2πx Vin φ2 C1 Vout + . Active-RC design 1/ω0 1/K0 Vin K1 CA=1 Vout + 3.14-31 CHUNG-YU WU §14-8 First-Order SCFs Ha(s)=- K1 S + K 0 S + ω0 H(z)=- a1 z + ao b1 z + 1 1.

Z-1 Vout §14-9 Switched-Capacitor Ladder Filters §14-9. Z-domain block diagram H(z)= Vout (C + C1 ' ) z − C1 =- 1 Vin (1 + C 2 ) z − 1 C'1 + + C2 Vin C1(1-Z-1) -1 / CA 1 .1 Approximate Design of SC Ladder Filters (1) Third-order low-pass filter without finite transmission zeros RS V1 1 L2 I2 -V1=- -I2= 1 Vin − V1 ( − I2 ) SC1 RS V3 3 Vin −1 (V1 − V3 ) SL2 V 1 (− I 2 + 3 ) SC 3 RL ~ + RL Vout - C1 C3 V3= − LCR prototype circuit Loss (no loss) transmission zero => ∞ Vin 1/RS + +1 -I2 -1 SC1 -1 -1 SL2 -V1 + -1 +V3 ωp Loss response ω +1 + -1 SC3 Flow diagram 1/RL .14-32 CHUNG-YU WU 4.

error still exists which may be refined by the z-domain analysis.14-33 CHUNG-YU WU RS RS Vin 1 -I2 + L2 C1 -V1 -1 + Vin Active-RC realization CS φ2 φ1 φ1 φ2 CS 1 C3 + -1 C1 + φ2 φ1 C L2 Vout C RL φ1 C φ2 + φ1 φ2 SCF C C3 φ1 φ2 + φ2 φ1 Vout SCF realization equations: C= T R T Rs ωT<<1 CL => Cs ≅ C≅T CL ≅ T / RL Due to the approximation made in finding C values. .

14-34 CHUNG-YU WU (2) Third-order low-pass filter with transmission zeros ωa1=-ωa2= 1 L2 C 2 -V1= -I2= Vin − V1  −1 + sC 2V3 − I 2 . sL2  V3  −1  − sC 2V1 − I 2 + s (C 2 + C 3 )  RL  IC2 +V3= LCR Prototype circuit: C2 RS V1 1 L2 I2 V3 3 Vin ~ + RL Vout - C1 C3 1/RS Vin 1/RS + -1 s(C1+C2) -V1 Flow diagram: SC2 -1 -I2 -1 SL2 + -1 SC2 + -1 S(C2+C3) +V3 Vout 1/RL . s (C1 + C 2 )  Rs   −1 [V1 − V3 ].

CB=L2. CA=C1+C2.RS 14-35 CHUNG-YU WU Active-RC Realization: RS Vin CA=C1+C2 -V1 + R CB= L2/R2 -R -RI2 C2 C2 R + CC=C2+C3 -R + V3 Vout RL CS Vin φ2 φ1 φ1 φ2 CS SCF: CA + φ2 φ1 C C CB φ1 C2 C2 C φ2 φ1 φ2 + C CC φ2 φ1 Cs ≅ T / Rs. CL ≅ T / RL . Vout φ1 φ2 + CL . Cc=C2+C3. C≅ T.

sL1 − V1 + V3 .14-36 CHUNG-YU WU (3) Fourth-order Bandpass filter C2 I2 I1 C1 L1 L3 RS 1 V1 L2 V3 I3 C3 3 Vin ~ 1/RS + RL Vo - LCR Prototype Circuit 1/RS Vin + -I1-I2 -1 s(C1+C2) -V1 -V1= -1 -V1  Vin − V1 −1 + sC 2V3 − I 1 − I 2 . sL3  V3  −1 − sC 2V1 + I 3 − I 2 +  s (C 2 + C 3 )  RL  C V3= -I2 SC2 I3 -1 SL3 -1 V3 + I3-I2 + -1 S(C2+C3) V3 Vout 1/RL . sL2 SC2 VB VA VC A B I3= -I2 -1 SL2 -1 + VD D V3 .  s (C1 + C 2 )  RS  + -I2 -I1 -1 SL1 -I1= -I2= − V1 .

=> Saturation occurs How to solve this problem? Don't model the inductor loop currents separately. HAB→0. I2. Only two inductive currents I and I entering nodes 1 and 3 are modeled. I =I1+I2 I =I2-I3 1 3 New flow diagram: . I =0 and I =0 1 2 =>No any instability at dc. Due to inductor loops! VB VA VC VD HAB = Circuits below A and B disconnected − sL1 S L1 (C1 + C 2 ) + SL1 / Rs + 1 2 HCD = Circuits below C and D disconnected − sL3 S L3 (C 2 + C 3 ) + SL3 / RL + 1 2 When S→0. HCD→0 => There will be no dc feedback paths around the center integrator which provides -I2. I3. I1.14-37 CHUNG-YU WU ** The circuit has a stability problem at dc. i. i. 1 3 => Vin =0 and S→0. Treat only two inductors as independent inductors. => OP AMP will be in the open-circuit status with A→∞.e.e.

− V3 + L1 + L2   -I(3) ∆ I3-I2= 3 Where L12 ∆ L1 L2 = L1 L2 /( L1 + L2 ) .  R s (C1 + C 2 )   s −1 sL12  L1V3  V1 − .14-38 CHUNG-YU WU -V1= Vin − V1  −1 + sC 2V3 − I (11)  . L1 + L2   -I(1) ∆ − ( I 1 + I 2 ) = 1 V3=  V3  −1 3 . − sC 2V1 − I (3) + s (C 2 + C 3 )  RL  −1 sL12  L1V1  .

14-39 CHUNG-YU WU .

14-40 CHUNG-YU WU SCF: .

The signs of the voltage and current variables must be chosen such that inverting and noninverting integrators alternate in the implementation. . A doubly terminated LC two-port is designed from the SCF specifications can be prewarped using the relation: ωT 2 Wa = sin( ) T 2 which represents the frequency transformation due to the LDI transformation implicit in the design produce. If inductor loops exit. Inverting SC integrator + Noninverting SC integrator −1 (C1 / C 2 ) inv (C1 / C 2 ) noninv z H(z)=- 1 − z −1 1 − z −1 −K − Kz −1 = = 1 1 −1 2 − (1 − z ) (z 2 − z 2 )2 Ton z=ejωT => H(ejωT)= +K 4 sin 2 (ωT / 2) LDI mapping (Lossless discrete integrator): 1 Sa= ( z − z −1 ) 2T 1 − 1 1 T 2 If is used => Sa= ( z − z 2 ) 2 T 1 T => ωa= Sin(ω ) T /2 2 2.14-41 CHUNG-YU WU General Procedures for the approximate design of SC ladder filter : 1. the inductive node currents can be used.The state equations of the LCR circuit are found.

− s a C 2 V1 − I 2 + s a (C 2′ + C 3)  RL  LCR Prototype Circuit: . 5. additional circuit transformations can be performed to improve the response of SCF. '  Rs S a (C1 + C 2 )    1  [V1 − V3 ] . The block diagram or signal flow graph (SFG) is constructed from the state equations. It is then transformed (directly or via the active-RC circuit) into the SCF. -I2=  s a C L 2 − s a L2    V3=  V3  −1 ′ . If necessary.1 Third-order SCF (Low-pass with finite transmission zero) C2'=C2+CL2 -CL2= -V1= −T 2 4L2  V1 + Vin  −1 ′ − + s a C 2 V3 − I 2 . §14-10 Exact Design of SC Ladder Filters * Ladder synthesis based on the bilinear Sa-to-z transformation ☆ Sa= 2 T z −1 z +1 (1)jωa─axis=>unit circle (2)preserves the flatness of PB and SB §14-10.14-42 CHUNG-YU WU 4.

Five different blocks: (a) The input branch 1 Rs . (2) Transforming the Q-V relations into the z-domain. (3) Realizing the transformed z-domain equations into SC circuits.14-43 CHUNG-YU WU Flow diagram The center block has the transfer function: 1 − S a L2 C L 2 1 − ( S a T / 2) 2 1 =− = H(Sa)=SaCL2S a L2 S a L2 S a L2 2 Transformation of the blocks into SC circuits: (1) Finding Q-V relations of all blocks and branches in the Sa domain.

14-44 CHUNG-YU WU Qin (Sa)= 1 1 Vin Rs Sa Qin (z)= T z + 1 Vin ( z ) 2 z − 1 Rs T (1+z-1)Vin(z) 2 Rs Cs [Vin(tn)+Vin(tn-1)] 2 => (1-z-1)Qin = qin(tn)-qin(tn-1)= SC realizations: CS/2 φ2 Vin CS CP φ1 φ1 Optional. (c)The branches SaC Q 1 = CS a =C V Sa (d) The blocks 1 SaC Q = −C V Only a C is required. . 1 R s L Vin -CS/2 φ2 φ1 CS φ2 φ2 φ1 Virtual ground − Cs C : − s [Vin (t n ) − Vin (t n −1 )] 2 2 Cs: CsVin(tn) ⇓ Cs [Vin(tn)+Vin(tn-1)] 2 * Stray insensitive. Cp + Cs not Cs (b) The feedback branch 1 R . => OP with a feedback capacitor C. To guarantee the charge flow only when φ1=1 Cs Cs : [V in (t n ) − V in (t n −1 )] 2 2 Cs : Cs Vin (tn-1) Virtual ground * Not stray insensitive.

C * The negative capacitor − s has been merged into the feedback capacitors 2 CA and CB. + . C C CB=C2'+C3 − s CA=C1+C2' − s 2 2 * Why C2'.14-45 CHUNG-YU WU (e) The center block 1 − ( S a T 2) 2 -I2=(V1-V3) S a L2 1 − ( S a T 2) 2 − I2 =− (V1-V3) Q(Sa)= 2 Sa S a L2 4C L 2 Z Q( z ) 1 − [( z − 1) /( z + 1)]2 => =− =− 2 2 V1 ( z ) − V3 ( z ) (4 L2 / T )[( z − 1) /( z + 1)] ( z − 1) 2 ∆ Q(z)=(1-z )Q(z)= -1 4C L 2 (V3 − V1 ) z −1 − 4C L 2 / C 2 ∆Q( z ) 4C L 2 z −1 −1 )(C ) = = (−Cz )( V3 − V1 1 − z −1 1 − z −1 Realizations: -V1 ψ1 C ψ1 C ψ1 ψ2 ΔQ Virtual ground V3 ψ2 ψ1 ψ2 ψ2 Virtual ground C2/4CL2 ψ2 ψ1 C ψ1 C ψ2 The final realization is shown in the next page. -CL2 ? To create a block which is realizable by SC circuit. * This circuit is not fully stray insensitive. respectively.

14-46 CHUNG-YU WU SCF: ψ2 CS / 2 Vin ψ1 ψ2 CS CA CS ψ1 ψ2 ψ2 ψ1 C C'2 C'2 C CC ψ1 ψ2 ψ2 CL Vout The complete bilinear ladder circuit equivalent to the LCR circuit + - ψ1 ψ2 + CB + C ψ1 ψ2 C ψ1 .

2 SL1 SL3 SL2 Note that 1 − ( S a T 2) 2 is realizable ! Sa L =>I2(S)=S[(C1+CL1)V1+(C1+C3+CL1+CL3)(-V2)+(C3+CL3)V3] +( − 1 S T 2s ) [Γ1V1+(Γ1+Γ2+Γ3)(-V2)+ Γ3V3] 4 1 T2 . Γi= Where CLi ≡ Li 4 Li First Term: Q2'(S)=(C1+CL1)V1+(C1+C3+CL1+CL3)(-V2)+(C3+CL3)V3 Can be realized by unswitched capacitors. Second Term: T z +1 2 T 2 ) − ] [Γ1V1+(Γ1+Γ2+Γ3)(-V2)+ Γ3V3] Q2"(Z)=[( 2 z −1 4 T 2 z −1 = [Γ1V1+(Γ1+Γ2+Γ3)(-V2)+ Γ3V3] (1 − z −1 ) 2 .14-47 CHUNG-YU WU §14-10.2 Bandpass LCR filters C1 LC prototype Circuit: V 2 I2 L1 C2 V2 IL2 L2 IL3 L3 C3 V3 1 -V2 can be produced as: I2 - + C2 I2 -V2 I2=(SC1+ V 1 1 ) (V1-V2)+(SC3+ ) (V3-V2).

( ∆Q2 " / V1 . ∆Q2 " / V3 ) C 4C7 T 2 CC 1 1 1 = = 4C L1 . ∆Q2 " /(−V2 ). c8 arbitrary c7 c8 Vb .14-48 CHUNG-YU WU The same as before but now three functions are superposed together. 5 7 = T 2 ( + + ) = 4(C L1 + C L 2 + C L3 ) Conditions: C8 L1 L2 L3 C8 L1 C6C7 T 2 = = 4C L 3 C8 L3 Stage providing Q2”(z): V1 -V2 V3 LC prototype circuit: C1 V2 V1 L1 C2 L2 L3 C3 V3 C4 C5 C6 C8 C7 Q2"(z) Vitrual ground SC realization: Design equations: CL1=T2/(4Li) c1=C1+CL1 c2=C1+C2+C3+CL1+CL2+CL3 c3=C3+CL3 c4= 4 c8 C L1 c7 c4 c1 c3 V1 c2 Vt=-V2 c5 c6 V3 c c5= 4 8 (C L1 + C L 2 + C L 3 ) c7 c6= 4 c8 CL3 c7 c7.

Cs ∆ T Rs Cs . c7 arbitrary .14-49 CHUNG-YU WU LC prototype circuit with RS: RS C2 V2 Vin C1 L1 L2 SC realization: c1 Vin c8 c2 c3 c4 -V1 V2 c5 c9 Design equations: C Li ∆ c7 c6 T2 4 Li . c2=c3=C9 2 c4=C1+C2+CL1+CL2-CS/2 c1= c5=4 c6 (C L1 + C L 2 ) c7 c6 CL 2 c7 c8=C2+CL2 c9=4 c6.

CL ∆ RL 4 Li c2 c5 c1=C1+CL1 c2=4 c6 C L1 c7 c3=CL c4=C1+C2+CL1+CL2-CL/2 c c5= 4 6 (CL1+CL2) c7 c6.14-50 CHUNG-YU WU LC prototype circuit with RL: VN C1 VL L1 C2 L2 RL SC realization: c1 c3 c4 -VL VN Design equations: CL1 ∆ T2 T . c7 are arbitrary c7 c6 .

Vt= − [(C1C8 − C 4 C 7 / 4) S 2 + C 4 C 7 / T 2 ]V1 + V3 [(C 3C8 − C 6 C 7 / 4) S 2 + C 6 C 7 / T 2 ] (C 2 C8 − C 5 C 7 / 4) S 2 + C 5 C 7 / T 2 1 S S ( − )[(C 2 C 4 − C1C5 )V1 + (C 2 C6 − C3C5 )V3 ] Vb= T 2 (C 2 C8 − C5C7 / 4) S 2 + C5C7 / T 2 * The phase shift between Vt and V1.14-51 CHUNG-YU WU Z-domain verifications: Upper OP AMP: C1(1-z-1)V1+C3(1-z-1)V3+C2(1-z-1)Vt+C7Vb=0 Lower OP AMP: -C4z-1V1-C6z-1V3-C5z-1Vt+C8(1-z-1)Vb=0 => Vt=N 1V1 + N 3V3 D z −1 (1 − z −1 )[(C 2 C 4 − C1C5 )V1 + (C 2 C6 − C3C5 )V3 ] Vb= C8 D where N1(z)=C1C8[(1-z-1)2+ C 4 C7 −1 z ] C1C8 C6 C7 −1 z ] C 3 C8 N3(z)=C3C8[(1-z-1)2+ D(z)=C2C8[(1-z-1)2+ C5C7 −1 z ] C 2 C8 * All poles and zeros of the transfer functions Vt/V1. =>Can simulate a lossless LC with the same low sensitivity. . and Vb/V3 are located on the unit circle. as well as between Vt and V3 are either 0° or 180° for s=jω =>The same as for the LC prototype regardless of the element values Ci. Vt/V3. After the bilinear s-to-z transformation. Vb/V1.

=>unstable. .e. V1 C1 V2 L2 C2 C3 V3 High-pass L1 L3 L2 C2 Low-pass Vt=-V2 => V2= (aS 2 + b)V1 + (cS 2 + d )V3 eS 2 + f * High-Pass Case : At Z=ejωT =-1 ω c 2π / T = 2 2 If the loss is zero (i. input termination) is a problem! * Inductor loop is O. passband). Rs input (i.K.e.e. i.14-52 CHUNG-YU WU * It can also simulate the behavior of any LC ladder section which has a T configuration. . ω= =>(1-z-1)Qin(z)= T (1+z-1)Vin(z) 2 Rs =0 Qin(z)=0. but loss is zero =>The other part of the circuit should have an infinite gain.

K. (2) Low-pass. Why scaling? (1) Improve the actual performance. (3) Can't realize high-pass or band-reject filters.14-53 CHUNG-YU WU §14-10. But they are not fully stray insensitive. . §14-11 The Scaling of High-Order SCF's. (2) Reduce the silicon area V1 F1 ∆Q1 F7 V2 F2 ∆Q2 ∆Q4 F4 Vj F5 ∆Q5 V3 F3 ∆Q3 Vi OAj F8 OAi F6 A ∆Q6 OAk Vk SC filter section. (4) Some modifications are proposed.3 Comparisons LDI Realizations of Ladder Filters using SC Integrators (1) Prewarping is required (2) Inductor loop exists =>Modified design =>Component sensitivity ↑ Bilinear Realizations of Ladder Filters using SC Integrations (1) Prewarping is not required. But they are not fully stray insensitive. band-pass ladder filters are O. => Instability exists.

F5. This can be achieved simply by multiplying all capacitors in these branches by ki. . max Ap: passband gain. all other voltages or changes are not affected.∆ Q1(z). => V2.'(z)= ∆ Q4(z)/[kiF4(z)]=Vi(z)/ki The new output voltage of OAi The old output voltage of OAi Vi→Vi/ki due to scaling.∆ Q2(z).∆ Q3(z) remains at its original value. ∆ Q5'=F5'(z)Vi'(z)=kiF5(z) Vi ( z) =F5(z)Vi(z)= ∆Q5 ( z ) ki Voltage scaling does not change charge flowing from the scaled branch to the rest of the circuit. =>Only Vi/ki. and F6 are multiplied by a positive real constant factor k. Optimization of the dynamic range using scaling F1 V1 V2 F2 F4 Vj F5 OAn F3 F6 A Vn Vout V3 Vin OAi Vn Vmax/Ap ≥ Vin. Since the input branches and their voltages were left unchanged. the change flowing in the feedback branch is ∆ Q4(z)=.14-54 CHUNG-YU WU Let all branches connected to the output terminal of OAi be modified such that their ∆Q / V transfer functions F4.

we choose Vin. It is not good to choose k2(k3)> VP2/VP5(VP3/VP5)because the noise will be increased. max=Vmax/Ap Similarly. V2'(ω)=V2(ω)/k2 k2=VP2/VP5 =>V2' has a peak value of VP2' which is equal to VP5. k1=VP1/VP5<1. k3=VP3/VP5. => dynamic range ↓. CONCLUSION: For maximum dynamic range. =>Vin. max=Vmax/A2 A2= V p 2 / Vin . . all op-amp outputs should be scaled such that each (at its own maximum frequency) saturates for the same input voltage level. k4=VP4/VP5<1. max= Vmax Vmax VP 5 Vmax = < A2 AP VP 2 AP since VP5/VP2<1 =>Maximum Vin ↓=> Dynamic range ↓ Reducing V2 by scaling.14-55 CHUNG-YU WU OA2 will saturate before OA5 because V2 > V5 for ω~ω2. Ap= V p 5 / Vin A2=Ap VP 2 / VP 5 Vin. Now.

min among all capacitors contained in these four branches is located. n=1. (c) Multiply all capacitors connected or switched to the output terminal of op-amp i by ki=Vpi/Vi. Scaling for Maximum Dynamic Range (a) Set Vin(ω) to the largest value for which the output op-amp does not saturate. and scaling for minimum capacitance afterwards. =>Effective in reducing the cap. 3.Scaling for Minimum Capacitance (a) Divide all capacitors in SCF into nonoverlapped sets. 2. (d)Repeat for all internal op-amps. * Scaling for optimum dynamic range should be performed first. Only the charges in the scaled branches get multiplied by mi.max is the saturation voltage at the output. F2.14-56 CHUNG-YU WU Let the transfer functions Fj(z) ≡ ∆Q j / V j of all branches connected to the input terminal of OAi be multiplied by a positive real constant Mi => Ci→mCi ∆Qn . 2.max where Vi. min => The smallest capacitance becomes Cmin and all op-amp voltages remain unaffected. Record Vin(ω) and Vi. 1. F3. max (b) Calculate Vpi for all internal op-amp output Vpi usually occur near the passband edges. spread and the total capacitance of a SCF. =>All capacitors contained in these four branches are multiplied by mi=Cmin/Ci. 4 → ∆Qn ' =mi ∆Qn F1. Ci. Capacitors in the ith set Si are connected or switched to the input terminal of . F4 Vi'= ∆Q4 ' mi ∆Q4 ∆Q4 = = = Vi F4 ' mi F4 F4 Vi unchanged! The output charges ∆Q5 and ∆Q6 also remain the same =>The above scaling by mi leaves all op-amp output voltages in the SCF unchanged.

additional circuit transformations can be performed to improve the response of SCF. 4. * Scaling for optimum dynamic range may also reduce the sensitivity to finite op-amp gain effects.. 3.. The block diagram or signal flow graph (SFG) is constructed from the state equations.14-57 CHUNG-YU WU op-amp i. (b) equivalent circuits. (c) Repeat for all sets Si. Y Y1 Y2 Y3 Y0 A vout V1 V2 V3 (a) (Y+Y0+Y1+Y2+Y3+.)/A Y Y1 Y2 Y3 vout 8 V1 V2 V3 (b) The influence of finite op-amp gain: (a) actual circuits. It is then transformed (directly or via the active-RC circuit) into the SCF. min. . (b) Multiply all capacitors in Si by mi=Cmin/Ci. If necessary.

5KHz to fc/2 Minimum stopband loss αs ≥ 38dB (Maximum allowable gain value) fc= =50KHz 1 T Stopband: Sampling frequency: Design Procedures: 1.82815049.068 )( 2 ) Ĥ(Sa)=( ˆ S a + 0.128006731. â2=-0.100351473.96934556S a + a1 2 + b1 2 ˆ ˆ ˆ (-2 a1 ) (. b 1=0.14-58 CHUNG-YU WU §14-10 Design Examples on Cascaded SCF and LDI Ladder SCF §14-10.a 0 ) 2 ( Sa 2 ˆ Sa + ω 2 ) 2 ˆ2 ˆ ˆ − 2a 2 S a + a2 + b2 2 2 ˆ where â1=-0.4667 rad/s T 2 s ωas= 2 tan ω T T 2 Selectivity parameter k≡ ω ap ≅ 0. ŵ1=1.05dB (Maximum allowable passband gain variation) fs ≤ 1.6656 ω as Elliptic filter is chosen to minimize the filter order. Results: ˆ k ˆ S 2 a + ω1 0.78140011 S a + 0.S-domain transfer function H(s) Frequency prewarping ωap= ωT 2 tan p =6291.48467278.5514948.32131474 . ŵ2=2.1 Cascaded SCF Filter Specification Passband: 0 to fp=1kHz passband ripple αp ≤ 0. ˆ b 2=1.

8719271×10-3. f H(ejωT) 0≦f≦fc/2 . e1= -1.044dB. b1=5.04930266×103.46044744×104. f1=0. C1= -1. do=-0.871739343. k =0. frequency denormalization and z-domain transfer function H(z) Denormalization: Sa→S/ωp Ĥ(Sa) →H(S) ( S 2 + ω1 )( S 2 + ω 2 ) H(S)=K 2 2 2 2 ( S − a0 )( S 2 − 2a1 s + a1 + b1 )( S 2 − 2a 2 s + a2 + b2 ) 2 2 Where K=428.21028124×103 a2=-805.247646. f2=0.916465445. Check: H (e jωT ) satisfies specifications.949416807.91615278×103 a1=-3. α p=0.350086.49448 rad/s.968447477. ˆ ˆ α s=39.962247471. 1 H(ejωT) fc/2 fp 1 vs.76117788×103. ŵas=1. b2=6.14-59 CHUNG-YU WU => filter order=5 ˆ ŵap=1 rad/s. e2=-1.88543246. C2= -1. ao=-4. ω2=1.92282466×103 2 z −1 z −1 Bilinear transformation: S→ = 10 5 T z +1 z +1 H(s) →H(z) z + 1 z 2 + C1 z + 1 z 2 + C 2 z + 1 )( )( ) H(z)=(C z + d o z 2 + e1 z + f1 z 2 + e2 z + f 2 Where C=3.669 => The specifications are satisfied with Ĥa(0)=1 2.906284158. ω1=9.57dB.

0937 Vin CS φ1 A1 Vout z 2 + C1 z + 1 (2) H1(z)= (1 / f1 ) z 2 + (e1 / f1 ) z + 1 The SCF is shown on P. C1'=a2-a0=0.99 Low-Q C2=C3= b1 + b2 + 1 = (e1 + 1) / f1 + 1 ≅ 0.14-60 CHUNG-YU WU 1 H(ejωT) vs. (a + b1 ) Q1= 1 2 a1 2 2 1 2 ≅ 0. SC realization (1) H0(z)= z +1 z − 0.9063 .14-21.12436. . CD=0.9063 CD -1/CE 1-Z-1 H0(z)=Vout Vin + CS 2 + (1+Z-1) Cs / 2 z +1 × C D + C E z − C E /(C D + C E ) φ1 CS/2 φ1 φ2 φ2 φ2 CD CE φ2 Cs=2 arbitrarily chosen =>CE=0. f 0 ≦ f≦ f p fp 3. The component values are: C1"=a0=1.

The antialiasing filter preceding the SCF has a lower requirement. CA=CB=1.30358. The component values are: C1 " = a 2 / b2 = f 2 ≅ 0. (3) H2(z)= z 2 + C2 z + 1 ( 1 ) z 2 + ( e2 f 2 ) z + 1 f2 (a + b2 ) Q2= 2 2 a2 2 2 1 2 ≅ 4.13795.33 =>High-Q The SCF is shown on P. C1=(a0+a1+a2)/b2C3=(2+c2)f2/C3 ≅ 0.22873.14-61 CHUNG-YU WU C1=(a0+a1+a2)/C3 ≅ 0. C4=b2-1=1/f1-1 ≅ 0.14-23.58645.12939. f 2 + e2 + 1 ≅ 0. (4)Overall SCF * Ho (low-pass linear section) is placed first =>High-frequency out-of-band signals and input noise can be attenuated. * H2 (high-Q section) is placed to the center=>good signal-to-noise ratio CD CS/2 Vin φ1 CS φ2 φ1 φ2 A1 φ1 φ2 φ2 C1 φ1 φ1 φ2 CA A2 C2 C4 φ1 C3 φ2 C1" φ1 CB φ2 A3 φ1 φ2 CE A SECTION 1 SECTION 2 (HIGH Q) C2 φ1 C4 φ1 A4 φ2 A φ2 CA C1 φ1 φ2 C3 φ2 φ2 φ1 CB A5 φ2 φ2 φ1 Vout C 1" SECTION 3 (LOW Q) .96845 C 2 = C 3 = (1 + b1 + b2 ) / b2 = C1 ' = (a1 − a 0 ) / b2 c3 = 0. C4=(1-1/b2)/C3=(1-f2)/C3 ≅ 0.

666. C2 ≅ 1.3036.9926. Elliptic ladder filter is chosen(fifth-order).07kHz =>CB. CB ≅ 8. C2. and CA at the input node of op-amp A2 are scaled to make C1=1 =>C1=1. C4 ≅ 3.80=>CB ≅ 180.354. (O.345.7286 C1 ≅ 1.C2.9926.518 (Multiplying all capacitors connected or switched to the output node of op-amp A1 by 21.144 (4) Similarly.672.14 Thought the same procedures. C3 ≅ 1. (2) Vp3 ≅ 180. The same filter specification.2dB/1% C1 ≅ 6.5pF => C=1 op amp: gain 70dB bandwidth 3 MHz passband sensitivity to capacitance variation ≅ 0. C1"20. C4 ≅ 41. (The input of A3) 3) Vp4 ≅ 503.14-62 CHUNG-YU WU 4. C3 ≅ 24. C2 ≅ 12. we have C A ≅ 17.1815.) 2) Vp2 (peak output voltage of op-amp A2) occurs around fp2=1.K. =>Ho(1)→-1 => CD=CS=2. (3) Minimize total capacitance=>C1.10kHz (1) Vp2 ≅ 177. C 2 = 1 C3 ≅ 2.80. CA ≅ 14.3085 " §14-12. C2 ≅ 24. C B ≅ 7.941.80 at 1.345 (1)We want an overall passband gain of 1.7466. Scaling 1) Vp1=occurs at dc where H0(1)=-CS/CD=-21.2 Bilinear Ladder SCF Design 1.424.05=> CA ≅ 177.05 for Vin=1 Reducing Vp1/Vin to 1 =>CA and C3 are multiplied by 177.345) (2)All capacitors at the input node of A1 should be scaled so that the smallest ( Cs 2 ) equals 1.1116. and C4 are multiplied by 180. C1"=1. CE ≅ 19.05.57 and Vp5 ≅ 230. C4. The result is . C 4 = 2 5 Final Design Cmin is chosen as 0.

58945×10-4 3.15367.4667rad / s T fc 2 Multiplying each resistor by z0. each inductor by L0=z0/ωap. sC ' 3 .48438 C4=0.85535 C2=0. L2=1. C4=0.46265 L4=0. C5=0.89794×Lo=2.63702 ŵap=1 rad/s 2. C0=1 is chosen => z0= 1 ω ap and L0= 1 2 ω ap We have the denormalized element values as: C1=0. z0 50Ω Usually choose z0=real source and termination resistance 100Ω 600Ω Here.89794 C5=0.26851×10-8.20763 C3=1. Rs=RL=z0=1. sC '1 RS 1 − sC L 2 ) (V1-V3).14-63 CHUNG-YU WU L2 RS L4 Vin C1 C2 C3 C4 C5 RL Normalized component values: Rs=RL=1 C1=0. and each capacitor by C0= 1 ωap.63702.46265.48438. sL2 1 (− I 2 − sC ' 2 V1 − sC 4 'V5 + I 4 ).15367 L2=1. SC realization Using the exact design technique of SC ladder filter (Section 14-10). Frequency prewarping and denormalization ωap ≅ ωT πf 2 tan p = 2 f c tan p ≅ 6291. C2=0. the state equations are -V1= − -I2=-( V3= 1 1 ( (Vin − V1 ) − I 2 + sC ' 2 V3 ).05090×10-8.20763×Lo=3.85535. C3=1. L4=0.

C1 1/RL SCF: arbitrarily chosen C=CL2=0.10839.003278. sL4 V −1 ( I 4 + sC ' 4 V3 − 5 ).12583.1258293. C'5=C5+C'4=1.0008195. RL CE A5 φ2 Co8 φ1 CL Vout . Rs Vin φ1 φ2 φ2 φ1 Co1 φ2 CA A1 C2 C φ2 φ1 C'=CL4=0. 4 L2 2 sC'2 -I'2 1-(sT/2)2 sL2 V3 -1/sC'3 I4 sC'4 C'2=C2+CL2=0.003278 Cs= T = 0.s = 0.0044082.10408.46706. sC ' 5 RL Vin The signal flow diagram is: 1/RS 1/RS -1/sC'1 -V1 sC'2 -V5= where CL2= T = 0. 2 CB= C C = L 2 = 0. 4C L 4 4 C41 C42 φ1 φ1 φ2 Co7 φ2 C CE=C'5.01230.L = 1. C'1=C1+C'2=1. 4 L4 1-(sT/2)2 sL4 sC'4 -1/sC'5 -V5 C'4=C4+CL4=0.004408 C21 C22 φ1 Co2 φ2 Co3 CC A3 Co5 Co6 CD A4 φ1 φ2 CB A2 φ1 φ2 C CA=C1+C2+CL2.001102.14-64 CHUNG-YU WU I4=( 1 − sC L 4 )(V3 − V5 ). T2 CL4= = 0.041165. CD= C C '2 = L 4 = 0.94938. C'3=C3+C'2+C'4=2. 4C L 2 4 2 Co4 φ2 φ2 φ1 φ1 Cc=C'3=2. 2 T CL= = 0.10839.15695.

09575 C42=5.14-65 CHUNG-YU WU 4.C01. and C03 multiplied by Vp2 Vp1 ≅ 0. for dynamic range scaling minimum-capacitance scaling: C A Cs 2 C1=1. Vp3 ≅ 0. OP amp: 70dB 3 MHz =>Passband ripple: 0.Scaling Vin=1V.87171 C05=1.86V.20028µH.00000 C04=1.45734µF. C2=24.24641µF.13318µF.38488µH. sL4 V 1 ( I 4 + sC 4V3 − 5 ).3 LDI Ladder SCF Design 1.00000 C2=1.06dB minimum stopband loss ≅ 39.43078 CL=1.90667 5.29480 C22=1.00000 CE=8.00000 C41=2. L2=192. s (C 4 + C 5 ) RL -V5= − .5dB Maximum sensitivity: 0.67396 C21=1. V3= − s (C 2 + C 3 + C 4 ) I4= V3 − V5 . 1 ( − I 2 − sC 2V1 − sC 4V5 + I 4 ).92V.20275 C03=1.52861 C07=2.14172 C06=1. Frequency prewarping and denormalization ωap ≅ ωp (for simplicity) z0=1Ω => C0= 1 (2π 10 ) 3 F.46156 =13.00000 CA=13. 2.27441 CD=14. sL2 C3=236.764V. ( 1 + sC 2V3 − I 2 ). -V1= s (C1 + C 2 ) Rs C1=136.C21.00000 CB=11. C5=101. C4=73.11901 Cc=14. LCR prototype circuit Fifth-order elliptic LC ladder filter with the same lowpass specifications. L4=142.5V. RL=1 Ω . Vp2 ≅ 34V.02212 C08=1.633034µF.C2.Final design Cmin . Vp4 ≅ 28. and C02 multiplied by Vp1 A2: C3.77112 C02=1. we have: A1: CA.91159µH.05dB % §14-12. L0= 1 H (2π 10 3 ) The denormalized element values: State equations: − V + Vin 1 Rs=1Ω.87171 C01=1. Vp5 ≅ 0. V −V -I2= 3 1 .83854 C3=2.

5dB OP amp: 70dB. C2=13. 3MHz Maximum passband sensitivity: 0. 5.59µF. C5B=1.71203. C2A=1.66885. The SCF is shown on P.105 V at 1.Final design Cmin Passband ripple: 0. C3A=1.76379. C1C=1.29263. C2B=1. C5=8. for A2:Vp2=1.857V at 1. C1+C2=160. T 1 4.044dB Minimum stopband loss: 40.927 V at 1. SCF: Element values: C1=8.08dB % .501 V at 967 kHz.75121.08053.29664.14-? whereas the active-RC circuit is given on P.SCF design The flow diagram is shown on P.07930.14-?.198 V at 1. CS= T =20µF. C5C=6. C4B=1.182kHz.14-? where T=20µs is chosen and the component values are C2+C3+C4=334. C3B=1. C5A=2. C3D=1. C3C=1.42236.Scaling Dynamic range scaling with Vpi listed: followed by minimum-capacitance scaling for A1:Vp1=0.14-66 CHUNG-YU WU 3.20614.13212.97271.34µF.02540.095dB>0. C3=12. CL= T =20µf RL C= =20µF. C4A=1. C1A=1. C1D=1. C4=15. C1B=1.03214. Rs C4+C5=175.121 kHz.061 kHz.08390.018µF. for A3:Vp3=0.061 kHz. for A4:Vp4=1. for A5:Vp5=0.

14-67 CHUNG-YU WU §14-13 Nonideal Effects in Switched-Capacitor Filters 1. V1(t)=V1(nT)=Vin(nT)(1-e −T 2 R C ) 1 1 Assume φ1 and φ2 are activated for T 2 . Switch Turn-On Resistance The turn-On resistance of a MOSFET can be written as Ron= φ 1 2 uco w (VG S − VT ) 2 L Vin signal voltage -Vss C * Nonlinear behavior The Ron effect on the simple SC integrator: C2 φ 1 φ 2 φ1 Vin C1 + Vout φ2 t=nT C2 t=(n+1)T φ1 R1 R2 + Vin V1 C1 + φ2 Vout t=nT nT+T/2 (n+1)T At t=nT . T ∆Q (nT+ ) = C1V1(nT )(1-e −T / 2 R2C1 )=[Vout(nT+T)-Vout(nT)]C2 2 Let R1=R2=R − (1 − e −T 2 RC ) 2 C1 C 2 => H(z)= z −1 C C Ideal: H(z)=.1 2 z −1 1 .

R ≤ 250Ω ? 2. * As soon as the clock feedthrough error voltage does not . C1=5pF R ≤ 20 KΩ .Clock Feedthrough Noise * All switches directly connected to the integrating node generate clock feedthrough noises. φ1 m φ2 T n * All clock feedthrough noises are proportional to the sampling frequency.1%(cap.05 =RC1fc ≤ T 2 ln 20000 20 20 fc or RC1 ≤ T (= 1 ) fc=500KHz. They may have a dc component. C1=2pF. 2e −T / 2 RC ≤ 10 −4 => RC1 1 ≅ 0. fc=100MHz.14-68 CHUNG-YU WU Error: ε=1-(1-e −T / 2 RC ) 2 ≅ 2e −T / 2 RC 1 1 1 Usually ε<0. ratio error) is acceptable.

max is about 25KHz in this case to avoid significant errors. 4. Finite Gain of the OP AMP.Junction Leakage * Worst-case (100°C or 125°C) leakage at the integrating node: 5µm×5µm junction => 400 pA leakage ~10 nA/mil2 * fs. * The leakage cause dc offset voltages. 3. it can be eliminated at the output by reconstruction filters(LPF).14-69 CHUNG-YU WU saturate the OP AMP. DC offset Voltage of the OP AMP + pratical op amp + + ideal op amp Voff C2 φ2 φ2 C1 + Vout + Voff = 5~20mv * Vout=(1+ C1 ) Voff C2 Voff * Integrator-based design may have a dc offset problem if no other negative feedback paths exist. C2 5. * The dc component cause offset voltage problems. 1 Vout(nT)=Vc2(nT). * Too-low-frequency operation is not good.Vout(nT) AO φ2 C1 φ1 φ1 φ2 + A0 Vout C2[Vc2(nT)-Vc2(nT-T)] +C1[Vin(nT)+ 1 Vout(nT)]=0 AO Vout ( z ) − (C1 C 2 )[1 + (1 + C1 C 2 ) / AO ]−1 z = =>H(z)= Vin ( z ) z − (1 + 1 ) /[1 + (1 + C1 C 2 ) / AO ] AO .

θ→0. Ao >1000 . AoωT>>1 f 1 = s AoT Ao => m and θ are very small.1% Similarly m(ω)=-e-k1[1-KcosωT] θ(ω)=-e-k1KsinωT k= C2 C1 + C 2 k1 ≡ K woT/2 If ωoT/2=πωo/ωc >>1 => m→0. Finite Bandwidth of the OP AMP. A(s)= −1 1 / Ao + S / ω o single-pole response Ao>1000=>0.14-70 CHUNG-YU WU H(ejωT)=Hi(ejωT) 1 1+ ( 1 AO )(1 + C1 / 2C 2 ) − j (C1 / C 2 ) / 2 AO tan(ωT 2) F(ω) m(ω)= − C1 / C 2 C 1 (1 + 1 ) θ(ω)= AO 2C 2 2 Ao tan(ωT / 2) − (C1 / C 2 ) z −1 1 F(ω)= 1 − m(ω ) + jθ (ω ) Hi(z)= F (ω ) = 1 (1 − m) + θ 2 2 ≅ 1 1− m ≅ 1+m C1 / C 2 AoωT relative magnitude error ≅ −θ ∠ F(ω)=-tan 1 − m ≅ tan-1θ ≅ θ -1 θ<<1 relative phase error θ<<1 m<<1 ωT<<1 . C1/C2 normal value. But for ω<2/AoT . ** ωo ≅ 5ωc is adequate. * The unity-gain bandwidth ωo of the OP AMP should be (at least) five times as large as the clock frequency ωc. θ is large. .1% Ao>100=>1% <0. ω>> 6.

Finite Slew Rate of the OP AMP * The output voltage of the OP AMP must be settled down with the clock active duration. or the noise aliasing effect becomes serious the antialiasing and smoothing filters must be too selective and too complex. ωc should be chosen low enough so that the OP AMPs have enough time to settle. Noise Generated in SC Circuits (1) Clock feedthrough noise (2) Noise coupled directly or capacitive from the power. Overall considerations: For an integrator settling error of 0.14-71 CHUNG-YU WU ωo vs ωc: (1) Given ωo. we must have Ao ≥ 5000 ωo/ωc ≥ 4 T/RonC1 ≥ 40 10. ground lines. and raises the dc power and chip area requirements of the op-amps. ωo should be just high enough to assure that the stage can settle within each clock phase. fp1=10KHz choose fc=2MHz. 9. But ωc should not be too low. and from the substrate.e. fo=10MHz. (3) Ao=1000 (60dB). tslew + t settle<T2 * May cause nonlinear distortion. C1:input cap. . 8. ωoT≒ 1 4 7.1% or less. Nonzero OP AMP Output Resistance 2Ro ( C1C 2 1 + C L ) ≅ T1 < TΦ 2=1 C1 + C 2 7 C2: feedback cap . Any higher value worsens unnecessarily the noise aliasing effect. clock. and f<40 KHz Typically f/fc ≅ 48 i. (2) Given ωc. CL: load cap.

=> ωo>>ωc is not suitable. * Thermal noise will be sampled and held with the OP AMP as a frequency limiting element. ↑ . Thermal and flicker ( 1 f ) noise: * Internal sampling and holding=>If 1 f noise has no aliasing=>It can be eliminated. * The circuit noise ↓ if the circuit cap.14-72 CHUNG-YU WU (3) Thermal and flicker ( 1 f ) noise generated in the switches and op-amps.

Infinite-gain Operational Transconductance Amp. =>Might not be needed if process-independent design is used and reasonable tolerance is allowed.15-1 CHUNG-YU WU CH 15. 2. Gm. AI. Continuous-Time Filters in CMOS §15-1 Categories of continuous-time filter ICs Amplifier Types Voltage OP AMP AV Current OP AMP AI Finite-gain voltage amp Finite-gain current amp. . =>Extra overhead and higher cost. Need tuning to accommodate the process variations on filter characteristics if high accuracy is required. Not parasitic free =>Greater tolerance in performance. Rm Finite-gain Transimpedance Amp. or Rm amplifier Mixed Gm and Rm Amplifiers Mixed AV. (OTA) Gm Finite-gain OTA or gm amplifier Infinite-gain Operational Transimpedance Amp. 3. and Rm Amplifiers RF amplifier Ο ∆ • × ? : : : : : well developed less developed but with great potential much less developed not explored to be developed with potential Continuous-Time Filter Types Ο (Voltage-mode) Active RC filters ∆ (Current-mode) Active RC filters ∆ (Voltage-mode) Active RC filters • (Current-mode) Active RC filters × Ο (Voltage-mode) Gm-C filters × ∆ (Current-mode) Rm-C filters ? ? ∆ Integrated LC filters Common characteristics of continuous-time filters: 1. No switches or clocks =>Lower noise (clock-induced) or simpler circuit.

Ri → ∞ V- ideal equivalent circuit V+ Ri Vgm(V+ . 5. §15-2 Gm-C or OTA-C (Operational-Transconductance-Amplifier-C) Filters §15-2.: IEEE Circuits and Device Magazine.15-2 CHUNG-YU WU 4.V-) Ro=0 Nonideal characteristics: gm is not linearly proportional to IABC or VABC. Could achieve GHz operation if deep submicron CMOS is used.20-32. Voltage amplifiers Gm or op amp + resistors. 1. (a) Basic inverting (b) Basic noninverting . V+ Gm amp or OTA symbol V+ Vgm Io IABC or VABC Io gm(V+ . Ro=0 h(h') is a constant. Could achieve higher-frequency operation in the VHF or UHF range if finite-gain amplifiers are used. pp. March 1985.V-) Ro Io §15-2. Ri and Ro are finite.2 Basic OTA building blocks Ref.1 Transconductor or OTA characteristics Ideal characteristics: gm=hIABC or h'VABC Io=gm(V+-V-) Ri→ ∞ .

15-3 CHUNG-YU WU (c) Feedback amplifier (d) Noninverting feedback amplifier (e) Buffered amplifier (f) Buffered VCVC feedback (g) All OTA amplifiers .

Controlled impedance elements 1 2 (a) Single-ended voltage variable resistor (VVR) (b) Floating VVR (c) Scaled VVR (d) Voltage variable impedance inverter (e) Voltage variable floating impedance (f) Impedance multiplier .15-4 CHUNG-YU WU 2.

* Can be used in voltage-controlled oscillator (VCO) (h) FDNR (Frequency Dependent Negative Resistance) R S=jω Zin(jω)=- 2 ω * Gyrator +super inductor. Integrators Gm or OTA + R or C (a) Simple (b) Lossy .15-5 CHUNG-YU WU (f) Super inductor (f) FDNR (d) Variable Impedance Inverter (VIC) or Gyrator * ZL is a capacitor=> Zin is a inductor=>active inductor. 3.

adjustable pole |H| Vi gm Vo gm↑ H(s)= Vo sc = Vi sc + g m gm/C ω .3 Gm-C or OTA-C filters (first-order) (a) First-order lowpass voltage-controlled filter. fixed pole. fixed high-frequency gain. fixed dc gain. pole adjustable Vi gm Vo |H| 1 gm↑ gm/C H(s)= Vo gm = Vi sc + g m ω (b) Lowpass. adjustable dc gain |H| Vi gm H(s)= Vo gm↑ Vo gm = Vi sc + 1 R 1/RC ω (c ) Highpass.15-6 CHUNG-YU WU gm1 C gm2 Vo/Vi=gm1/(sC+gm2) Vo (b) Adjustable §15-2.

fixed high-frequency gain. adjustable zero |H| gmR>1 H(S)= Vi gm Vo R( sc + g m ) = Vi sRC + 1 Vo gmR=1 gmR<1 1/RC ω (e) Shelving equalizer. fixed pole. adjustable pole and zero C2 Vi gm |H| H(s)= gm ↑ Vo sc2 + g m = Vi s (c1 + c2 ) g m Vo C1 gm/(C1+C2) ω (g) Shelving equalizer. fixed high-frequency gain. fixed zero.15-7 CHUNG-YU WU (d) Shelving equalizer. adjustable pole Vi gm |H| Vo gmR<1 gmR=1 H(s)= Vo g m (1 + sRC ) = Vi sc + g m gmR>1 1/RC ω (f) Lowpass filter. independently adjustable pole and zero C Vi gm1 gm2 |H| Vo 1 H(s)= gm1>gm2 gm1<gm2 Vo sC + g m1 = Vi sC + g m 2 gm1=gm2 ω .

4 Second-order Gm-Cor OTA-C filters (a) V01= S 2 C1C 2VC + SC1 g m 2VB + g m1 g m 2V A S 2 C1C 2 + SC1 g m 2 + g m1 g m 2 .15-8 CHUNG-YU WU (h) Lowpass or highpass filter. adjustable zero and pole. adjustable with gm C Vi gm1 gm2 R gm1/(gm1+gm2) gm1/(gm1+gm2) < C2/(C1+C2) ω H(s)= H Vo 180o 90o 0o Vo sC − g m1 = Vi sC + g m1 g m 2 R gm2R=1 gm↑ ω gm1/C §15-2. fixed ratio or independent adjustment C2 Vi gm1 gm2 |H| gm1/(gm1+gm2) gm ↑ Vo C1 C2/(C1+C2) gm1/(gm1+gm2) > C2/(C1+C2) |H| C2/(C1+C2) gm ↑ ω g m1 + sC 2 V H(s)= o = Vi s (C1 + C 2 ) + g m1 + g m 2 (i) Phase shifter.

the poles can be moved in a constant-Q manner. highpass. * If gm3 is adjusted with gm1 and gm2 fixed. Q= C1C 2 g m3 R C1 g m 2 * Can implement lowpass. * If gm3 is fixed and gm1=gm2=gm is adjusted. and notch. (c) S 2 C1C 2Vc + SC1 g m 2VB + g m 2 g m1V A Vo3= S 2 C1C 2 + Sg m 3C1 + g m1 g m 2 ωo= g m1 g m 2 g g C . bandpass. the pole movement in a constant-ω0 manner. Q= ( 2 ) m1 m 2 C1C 2 C1 g m3 .15-9 CHUNG-YU WU Transfer functions for the biquadratic structure (a) Circuit Type Input Conditions Transfer Function g m1 g m 2 Vi=VA ωo Adjustable 2 Lowpass VB and VC Grounded s C1C 2 + SC1 g m 2 + g m1 g m 2 sc1 g m 2 Vi=VB ωo Adjustable Bandpass VA and VC Grounded s 2 C1C 2 + SC1 g m 2 + g m1 g m 2 s 2 C1C 2 Vi=VC ωo Adjustable Highpass VA and VB Grounded s 2 C1C 2 + SC1 g m 2 + g m1 g m 2 ωo Adjustable Notch (b) Vi=VA=VC VB Grounded s 2 C1C 2 + g m1 g m 2 s 2 C1C 2 + SC1 g m 2 + g m1 g m 2 If gm1=gm2=gm ωo Q (fixed) gm C1C 2 gm C1C 2 gm C1C 2 gm C1C 2 C2 C1 C2 C1 C2 C1 C2 C1 ωo= g m1 g m 2 C 2 g m1 1 .

* The voltage-controlled amplifier of Fig.15-10 CHUNG-YU WU * ωo can be adjusted linearly with gm1=gm2=gm and gm3 constant => constant-bandwidth movement. and gm3 are adjusted simultaneously. gm2. =>Cascading these second-order blocks with interstage unity-gain buffers. The transconductance gain of the two OTAs in the .15-3 can be inserted between x and x'. All gm's are made equal and adjusted simultaneously. constant-Q pole movement. constant gain response. (e) Elliptic biquadratic filter x x' VA gm1 gm2 C1 Vo C2 C3 Vo S 2 + g m1 / C1C 2 C2 )( ) H(s)= = ( Vi C 2 + C3 S 2 + Sg m 2 /(C 2 + C3 ) + g m1 g m 2 / C1 (C 2 + C3 ) * Can be applied to the realization of high-order voltage-controlled elliptic filters. * If gm1. * Interchanging "+" and "-" terminals of gm1 and gm2 and setting VA=VB=VC=Vi. Q= g m3 C1C 2 g m1 g m 2 C 2 C1 * The adjustment of the bandpass version with gm1=gm2=gm will result in a constant bandwidth. and making gm1=gm2=gm3=gm => 2nd-order gm adjustable phase equalizer. (g) on p. (d) Vc C1C 2 S 2 + VB g m 3 sC1 + g m1 g m 2V A V04= S 2 C1C 2 + SC1 g m 3 + g m1 g m 2 C1 gm 2 C2 VC VB gm 3 gm 1 VA Vo4 ωo= g m1 g m 2 1 .

15-11 CHUNG-YU WU amplifier can be used as the control variable to adjust the ratio of the zero location to pole location. General first-order filter H(s)= Vout K1 S + K o = Vin S + ωo SCx + Gm1 = S (C A + C X ) + Gm 2 S( Gm1 Cx )+ C A + Cx C A + Cx Gm 2 S+ CA + CX H(s)= =>Cx=( K1 )C A .5 Fully Differential Gm-C or OTA-C Filters 1. Gm2=ω0(CA+CX) 1 − K1 . Gm1=Ko(CA+CX). §15-2. the ωo and Q for the poles and zeros can be adjusted by gm's to any desired value. (g) General biquadratic structure S 2 C1C 2Vc + SC1 g m 4VB + g m 2 g m 5V A Vo= S 2 C1C 2 + SC1 g m 3 + g m 2 g m1 * when Vi=VA=VB=VC.

15-12 CHUNG-YU WU 2. General biquadratic filter -ω0 -ω0/Q K0/ω0 Vin(S) + 1/S ω0 + 1/S Vout(S) K1+K2S H(s)= Vout ( s ) K 2 S 2 + K1 S + K o = ω 2 Vin ( s ) S 2 + ( o )S + ω o Q H(s)= Vout ( s ) = Vin ( s ) S2( G m 2 Gm 4 Gms GX ) + S( )+ C X + CB C X + CB C A (C X + C B ) Gm 3 Gm1Gm 2 )+ S 2 + S( C X + CB C A (C X + C B ) CX=CB( K2 ) where 0 ≤ K 2 <1 1− K2 Design equations: Gm1=ωoCA Gm2=ωo(CB+CX) Gm3= ω o (C B + C X ) Q Gm4=(KoCA)/ωo Gm5=K1(CB+CX) .

* Gm= 1 1 where rds3=rds4= rs1 + rs 2 + (rds 3 || rds 4 ) 2 K 3 (VGS 1 − Vtn ) rs1=rs2= I 1 1 = VGS1-Vtn= 1 g m1 2 K 1 (VGS1 − Vtn ) K1 . * Q5/Q6 are feedback devices to set the drain voltages of Q1/Q2.15-13 CHUNG-YU WU §15-3 CMOS Transconductor or OTA 1. * Gm can be adjusted by Vgs9 and scaled by the current mirrors Q3/Q7 and Q4/Q8. CMOS transconductor using triode transistor * Q9: operated in the triode region. CMOS transconductor using varying bias-triode transistors. 2. * Q3 and Q4 are in the triode region.

CMOS bias-offset cross-coupled transconductor. 4. CMOS differential-pair transconductor with floating voltage supply. Conceptual circuit: Real circuit: (iD1-iD2)= 4 K eq I B (V1 − V2 ) Gm=4 K eq I B * 30~50 dB linearity.15-14 CHUNG-YU WU 3. (i1-i2)=2KVB(V1-V2) Gm=2KVB *30~50dB linearity .

Aug. 1132-1138. 1986 2. Circuits and Systems. Nov. VL=VB=0 NLP: VL ≠ 0 . IEEE Trans. 1988 1.: 1. Gm-C biquad (general) 5 VL L 1 3 4 V2 2 VB C1 C2 VH V3 Q 6 6 Vo − C1 g m SN BP + C1 g m S 2 N HP + g m N LP + (C1C 2 g m S 2 + g m L g m ) N BR H(s)= 3 C1C 2 g m S 2 +C1 g m ( g mQ − g m ) S + g m 2 2 NBP: VB ≠ 0 . VL=VH=0 NHP: VH ≠ 0 . p 2 L Tunable gm amplifier symbol: VG4 M4 VSS 2. VH=VB=0 NBR: VL=VH=VBR.15-15 CHUNG-YU WU §15-4 Design Example of Gm-C or OTA-C Filters Ref. pp. pp.987-996. VB=0 .p= (u eff cox × ) n . IEEE JSSC. CMOS linear transconductance amplifier (CMOS inverter-based complementary differential-pair transconductor) VDD gm=2keff (VG1+ VG 4 − ΣVT) VG1 M1 ΣVT=VTn1+VTn3+ VTP 2 + VTP 4 M2 Vin Vout M3 keff = kn k p ( kn + k p )2 1 W kn.

2 Vpp 1 MHz 40% 1.5 dB 1mV @ Gain ≈ 50 §15-5 MOSFET-C Filters * MOSFET-C filters are slower than Gm-C filters ∵Miller integration. * Smaller speed ∵The load of op amps is resistive * Straightforward design methodology .5 MHz unlimited 75dB Manual 0.5% 1.5Vpp) Max.15-16 CHUNG-YU WU Experimental results on BP filter: Center frequency 4MHz TABLE I EXPERIMENTAL FILTER DATA Control Passband ripple Stopband attenuation Bandwidth S/N in passband Distortion (for 0. signal level Frequency control range Q-control range Offset (reference inverter) Automatic 1 dB >60 dB 800 KHz ≈40dB 0.

15-17 CHUNG-YU WU 1. Two-transistor integrators.General biquadratic MOSFET-C filter Active-RC circuit: MOSFET-C biquadratic filter: . (a) Active-RC integrator R1 ≡ R p 1 = Rn1 R 2 ≡ R p 2 = Rn 2 ino − i po SC1 (b) Two-transistor MOSFET-C integrator Vdiff ≡ Vpo-Vno= = = (i p1 + i p 2 ) − (in1 + in 2 ) SC1 1 1 (V p1 − Vn1 ) + (V p 2 − Vn 2 ) SR1C1 SR2 C1 2.

15-18 CHUNG-YU WU GG C1 2 G2 )S + ( )S + 1 3 V ( s) C CB C AC B = B H(S)= o GG G Vi ( s ) S 2 + ( 1 )S + 3 4 GB C AC B ( 3. Four-transistor integrators Vdiff ≡ Vpo-Vno = 1 srDS 1c1 (V pi − Vni ) + 1 srDS 2 c1 (Vni − V pi ) where rDS1= u n cox ( 1 W )1 (Vc1 − V x − Vt ) L rDS2= 1 W u n cox ( ) 2 (Vc 2 − V x − Vt ) L All four transistors are matched =>Vdiff= 1 srDS c1 (V pi − Vni ) 1 u n cox ( W )(Vc1 − Vc 2 ) L where rDS= .

VLSB. i.16-1 CHUNG-YU WU CH 16. Oversampling Advantage H( f ) 0 fs 2 f 1 x(n) fo quantizer N-bit fs y(n) y (n) 2 H(f) filter − fs 2 -fo fo fs 2 f f 2 fo Oversampling ratio OSR ≡ . Quantization noise modeling e(n) x(n) Quantizer y(n) x(n) + y(n) e(n) ≡ y(n) − x(n) * e(n) can be approximated as an independent random variable uniformly distributed between ± ∆ where ∆ is the difference between two adjacent 2 quantization levels. ∆2 * The quantization noise power = = Pe 12 * The quantization noise power is independent of the sampling frequency fs. Se(f) is white and all its power is within ± s . 2 ∫ fs 2 fs − 2 S e2 ( f )df = ∫ fs 2 fs − 2 ∆2 2 2 K x df = K x f s = 12 Se(f) Height Kx =>Kx=( ∆ 1 ) 12 f s − fs 2 2. f * The spectral density of e(n).e.1 Oversampling without noise shaping 1. Oversampling Data Converters §16-1 Fundamental Concept §16-1.

5 bits 2 Ps 3 ) = 10 log( 2 2 N ) + 10 log(OSR) Pe 2 =6. SNR improvement of 3 dB/octave or 0.000 GHz! * The advantage of a 1-bit DAC is that it is inherently linear. Ps remains the same since the signal's frequency content is below fo.16-2 CHUNG-YU WU Assume that the input signal is a sinusoidal wave between 0 and ∆2N.2 Oversampling with noise shaping 1. or 0. The system architecture of a ∆Σ oversampling ADC is shown in the next page . 1-bit converter with fo=25 KHz can obtain a 96-dB SNR(16 bits) if the sampling frequency fs=54. * Theoretically. Vout always linear 0 1 Bin §16-1.76+10log(OSR) =>SNR enhancement obtained from oversampling: 10log(OSR).5 bits/octave 3. but it does not improve linearity. but the quantization noise power Pe becomes Pe= ∫ S ( f ) H ( f ) df = ∫− fo K x df = 2 e 2 fs 2 fs − 2 2 fo 2 f o ∆2 ∆2 1 = ( ) f s 12 12 OSR OSR ↑×2 => Pe ↓ SNRmax=10log( 1 or -3dB.02N+1. The signal power Ps is ∆2 2 2 ) = Ps=( 8 2 2 ∆2 N 2 N With H(f).The advantage of 1-bit D/A converter * Oversampling improves the SNR.

16-3 CHUNG-YU WU Oversampling Delta-Sigma Analog-to-Digital Converters: T Analog Signal fs >> 2fo Delta-Sigma Delta-Sigma A-to-D Converter A-to-D Converter (Modulator) (Modulator) Decimation Filter 1-bit stream fs >> 2fo DSP DSP Decimation Decimation Chip Chip 2 fo = .First-order noise shaping: Y ( z) H ( z) = U ( z) 1 + H ( z) Y ( z) 1 = E( z) 1 + H ( z) . Multi-Bit Output 1 (OSR)T Minimum Anti-Aliasing Filter Analog Delta-Sigma Modulator Nyquist Rate PCM f0 Digital Low-Pass Filter OSR Down Sampler e(n) 2. . Noise-shaped ∆Σ modulator u(n) X(n) + - H(Z) 1-bit Quantizer y(n) u(n) + - H(Z) X(n) + y(n) DAC 1-bit DAC 1-bit Two independent inputs: U(z) and E(z) Signal Noise Signal transfer function STF(z) ≡ Noise transfer function NTF(z) ≡ =>Y(z)=STF(z)U(z)+NTF(z)E(z) If H (z ) → ∞ for 0<f<fo => S TF ( z ) → 1 and N TF ( z ) → 0 => Quantization noise ↓ and signal unchanged. . 3.

5bits/octave Without noise shaping: SNRmax ↑ by 3dB/ octave or 0.e. OSR>>1.17+30 log(OSR) Double OSR => SNRmax ↑ by 9dB or 1.16-4 CHUNG-YU WU z −1 (Noniverting Forward-Euler SC integrator) 1 − z −1 H ( z) = z −1 =>STF(z)= 1 + H ( z) H(z)= NTF(z)= 1 jωT j2πf/fs = (1 − z −1 ) z=e =e 1 + H ( z) NTF(f)=1-e-j2πf/fs=sin ( πf ) × (2 j ) × (e − jπ f / fs ) fs N TF ( f ) = 2 sin( πf ) fs The quantization power noise power over 0 to fo is ∆2 1 πf Pe= ∫− fo S ( f ) N TF ( f ) df = ∫− fo ( ) [2 sin( )]2 df fs 12 f s fo 2 e 2 fo Since fo << fs.76-5.02N+1. sin( πf πf )≅ fs fs ∆2 π 2 2 f 3 ∆2π 2 1 3 => Pe ≅ ( )( )( ) = ( ) 12 3 f s 36 OSR P 3 3 ∆2 2 2 N Ps= => SNRmax=10 log( s ) = 10 log( 2 2 N ) + 10 log[ 2 (OSR) 3 ] 8 π Pe 2 => SNRmax=6. i.5bits/ octave. Y=Z-1U+E(1-Z-1) Block diagram: U E z −1 H ( z) = 1 − z −1 + - + Y = UZ −1 + E (1 − Z −1 ) .

75 . 5 Control signal -. 5 -0.25 -. First-order noise shaping with 2-bit ADC and 2-bit DAC U + - z −1 1 − z −1 2-bit A/D Y 2-bit D/A 0. 5 -1 Can be eliminated by connecting the node A Directly to the node A'. 5 + ㆒ + 0 ㆒ Y 1 .25 -. 5 -0 .5 0 2 H(Z) C 1 2 phase 2 Reset Quantizer(1-bit ADC ) 1-bit DAC A 0. 5 ㆒ 0 MUX -1 Control line .16-5 CHUNG-YU WU SC implementation: C 2 1 1 A′ C + _ 2 Comparator 1 + _ U Latch (2) Y 1 .5 + .75 -.

5 bits/Octave General formula of SNRmax with k-order noise shaping: 2k + 1 ) + (2k + 1) 10log(OSR) SNRmax=6.5(2k+1)bits/Octave Noise-shaping transfer functions: N TF (f) Second-order First-order No noise shaping f 0 f 0 f s 2 f s The SC implementation of the second-order ∆Σ modulator is shown in the next page.16-6 CHUNG-YU WU 4. Second-order noise shaping H1 U + + H2 + E Y Quantizer - 1 + −1 1− z z −1 1 − z −1 DAC STF(Z)=Z-1 N TF ( f ) = [2 sin( NTF(Z)=(1-Z-1)2 Y=Z-1U+(1-Z-1)2E πf 2 )] fs ∆2π 4 1 5 ( ) => Pe ≅ 60 OSR SNRmax=10log( Ps 3 5 ) = 10 log( 2 N ) + 10 log( 4 ) + 10 log(OSR) 5 Pe 2 π =6. * Single-ended structure * Can be converted into fully differential structure for better noise rejection and .02N+1.10log( 4 π OSR×2=> SNRmax↑by 3(2k+1)dB/Octave or 0.9+50log(OSR) OSR×2 => SNRmax↑ by 15dB/Octave or 2.76.76-12.02N+1.

* The capacitor and switches in the feedback path to OP2 can be reduced as shown on page 16-5. SC implementation: Single-Ended type circuit diagram C 2 1 C 2 1 U C 2 1 1 2 OP +1 C 2 1 2 C 1 OP +2 1 + C 2 Preamplifier V+ Control signal 1-bit DAC COMP-1 V- Latch (2) Y Comparator as quantizer or 1-bit ADC .16-7 CHUNG-YU WU linearity.

.. f n 0 f (ω ) π f s x dsm x lp (n) 2π(f0/fs) π/6 2π ωTs 123. 12 n ωT0 π 2π 4π 6π 8π 10π 12 π π 2π ω T 6 s * The decimation process does not result in any loss of information. 6 . Architecture x in (t ) x (t ) c x Sampleand-hold sh (t ) x ∆∑ Mod dsm (n) Digital low-pass filter x lp (n ) x (n) s Antialiasing filter f s f s f OSR s 2 f 0 2. since the bandwidth of the original signal was assumed to be fo... n x lp (ω ) 2π x (n) s π/6 π 2π(f0/fs) = OSR OSR=6 ωTs x (ω ) s 16-bit resolution in 16-bit ADC 3.... The spectral information is spread over 0~ π in Xep and 0~π in Xs.16-8 CHUNG-YU WU §16-2 System Architecture of Oversampling ∆Σ ADC 1.000000K 3 12 4.. Signals and spectra Analog Digital Decimation filter X c (t ) X sh (t ) t x (f) c f 0 f sh f s x (f) x dsm (n) = ±1.

.. n x lp (ω ) ( 2πf ) 0 f s 2π ωTs x dsm (n ) x da (t ) x n....(1) n π π 2π 4π 6π 8π 10π 12 ωT0 x x lp s2 (ω ) (n) (2π f 0 ) f s 2π ωTs 123.. Signals and spectra x (n) s x (2) s2 (n ) x (ω ) s (3) 123. Architecture x (n) s x OSR s2 (n ) x lp (n ) x Mod dsm (n ) 1-bit D/A s x da (t ) x (t ) c 2 f 0 f s Interpolation (low-paaa) fs filter ∆∑ f Analog low-pass filter OSR ≡ f 2f s () Digital Analog 2.16-9 CHUNG-YU WU §16-3 System Architecture of Oversampling ∆Σ DAC 1.t dsm (ω ) ( 2πf ) 0 f (f) s 2π ωTs x da X c (t ) f 0 f c f s t Time x (f) f 0 Frequency f f s .

Usually aliased by sampling 1/f op-amp noise. U + - z 1 − z −1 −1 Q1 + Y 1 = UZ −1 + Q (1 − Z 1 −1 ) z −1 + Q1 Q1 + z 1 − z −1 −1 Q + (1 − z −1 ) - Y + YZ −1 §16-5 Design Considerations = Q1 Z −1 + Q (1 − Z −1 ) Y = UZ −1 − Q (1 − Z −1 )2 §16-5. Noise Thermal noise in resistors.16-10 CHUNG-YU WU §16-4 High-Order Modulators Multi-stAge noise SHaping (MASH) architecture: To use a cascade-type structure where the overall higher-order modulator is constructed using lower-order ones. op-amps. ground and substrate noise clock feedthrough noise clock jitter noise quantization noise leakage . => The stability could be maintained. conducing switches. dc offset Supply.1 Limitations on accuracy and linearity A.

2. => low-frequency input signal dependent The clock jitter could be a function of the low-frequency input signals. -1. -1. -1--3 Va (t ) = Vb(t ) = A1 + AO δ 1 + δ 2 + 2 2 2 A1 + AO δ 1 + δ 2 + 3 3 Average Vc(t ) = A1 + 2 AO δ 1 + δ 2 + 3 3 . The two output levels somehow become functions of the low-frequency signals=> Linearity limitation Power supply voltage are changed for different low-frequency signals to cause distortion. 1. => must be well-regulated. 1. δ2: The area difference of the present binary state with different past states. 1.1.: -1. 1.The memory between output levels also causes severe linearity limitation. The clock feedthrough of the input switches is also dependent on the gate voltage and thus the supply voltage.16-11 CHUNG-YU WU B. Nonlinear effects R&C nonlinearities Amplifier nonlinearities Finite op-amp slew rate Signal-dependent clock feedthrough noise Signal-dependent sampling aperture noise Internal A/D and D/A nonlinearities Linearity of 1-bit DAC: 1..1 : 1. 1--3 1 Average .. -1. Typical Ideal V2 V1 Binary 1 1 1 1 1 1 1 Area for A1 A0 +δ 2 A 0 A1 +δ 1 A0 +δ 2 A1 +δ 1 A1 +δ 1 symbol δ1. 1→-1: δ2 -1→1: δ1 Average 0 : 1. -1. -1. -1. -1.

1. return-to-zero (RTZ) coding scheme. 1. 1. dc level fs . 1. 1. δ1=-δ2 : To match falling and rising signals => Very difficult to achieve. 1. -1.16-12 CHUNG-YU WU Ideal case: δ1=δ2=0.e. -1. SCF or SC circuits are memoryless if enough time is left for settling on each clock phase.. 1. Idle tones phenomena 1-bit DAC dc level 1 => y(n)={1. 1. The use of memoryless coding scheme. Every 1 has the same area. 1. 1. 2. -1. 1. How to improve this nonlinearity? 1. -1. 1. 1. 3. i. -1. -1…. 1. Every -1 has the same area. Typical Ideal V2 V1 Binary Area for symbol 1 1 1 -1 1 -1 1 A 1 -1 A 0 1 A A A 0 A 0 A 1 1 : -1→1 and 1→1 -1 : -1→-1 => Better linearity. Basically.} 3 periodic pattern with the power concentrated at dc and After low-pass filter=> only dc level remains. 3 1 1 3 + = => y(n)={1.……} . -1. practical case: δ 1 ≠ δ 2 ≠ 0 =>Three averages do not lie on a straight line=>Nonlinear. 3 24 8 1. -1. 1.

as above) . The dithering signal breaks up the tones so that they never occur. §16-6 Advantages and Applications Advantages of Delta-Sigma Converters: Low-Complexity Analog. To add the dithering signal to the modulator just before its quantizer. They exist even in high-order modulators. 8-bit linearity (u/A-Law). Add about 3-dB extra in-band noise Require rechecking the modulator's stability. 16 => lowpass filter => dc level 16 3 and f s tone 8 16 (∵fo= f s is assumed and lowpass filter will not attenuate fs/16 signal) => Low-frequency tones cannot be filtered out by the lowpass filter and can lead to annoying tones in the audible range. Dithering technique to reduce idle tones. There tones might be a signal varying over some frequency range in a random-like fashion. The dithering signal has a white-noise type spectrum and is a random (psuedo-random) signal. High-Complexity Digital High-Resolution Conversion Low-Precision Analog (no trimming) Simple Anti-Aliasing Filters No Sample & Hold Needed Can be Built Completely In CMOS Overall Small Chip Area in Fine-Line Technology Can be Integrated on Chip With Other DSP Functions Ideally Suit for Rates up to and Including Audio Band Commercial Applications Well-Suited for Delta-Sigma ADC Standard Voice Band Telephony 13-bit dynamic range.16-13 CHUNG-YU WU periodic pattern with 16 cycles and some power at dc and f s . 8KHz Sampling rate Digital Mobile Radio (same req.

80kHz Sampling rate. 0. DAT. 16kHz Sampling rate ISDN U-Interface 13-bit dynamic range. stereo (2)) 16-18-bit (18-20 bit) resolution. 3-4kHz BW. 48kHz Sampling Rate 5 1/2 Instrumentation A/D Converter 20 bit resolution.722) 13-bit dynamic range.1-10Hz BW with Self-Calibration Circuit Integration with Digital Signal Processors Ideally Suited for Rates up to and Including Audio Band A variety of applications from voice-band through audio-band §16-7 Examples 2nd-order ∆Σ modulator implemented by fully differential SC circuit. 12-bit linearity.32 9600-Baud Modems) 14-15 bit dynamic range. . 160kb/s Transmission Rate Audio-Band (CD. 9600 Sampling rate ISDN Wideband Speech (CCITT G.16-14 CHUNG-YU WU High-Precision Voice-Band (CCITT V. 14-16 bit)(15-16bit) linearity.

.16-15 CHUNG-YU WU Testing Environment: Digital-to-Analog Converter Precision Function Generator . . Low-noise cable Pure test Pattern Good Transmission Line ADC ∆Σ Mearurement Chip under test *Develop design-for-testability ADC and environment The measured SNR versus input signal level.

Clock recovery in communication and digital systems. Applications of PLLs: 1. => Vcntl= ωi n − ω f r K osc . 2. Vpd=KM Ein Eosc [sin(φ d ) + sin( 2ωt − φ d )] 2 Since the lowpass filter is to remove the high-frequency (2ω) term. 2. its output voltage Vpd can be written as Vpd=KMVinVosc=KM Ein Eoscsin(ωt)cos(ωt-φd) where φd is the phase difference between the input signal Vin and the output Vosc of the VCO. Demodulation of FM signals. the signal Vcntl is given by E E Vcntl=KlpKM in osc sinφd 2 E E E E ≅ KlpKM in osc φd=KlpKpdφd where Kpd ≡ K M in osc 2 2 The frequency of VCO can be expressed as ωosc=KoscVcntl+ωfr where ωfr is the free-running frequency of the VCO with its control voltage Vcntl=0. 3.Basic PLL architecture: Vin + Phase detector Vpd Low-pass filter V Hlp(s) Loop filter Vcntrl Gain lp Klp Output voltage Average voltage proportional to phase difference VOSC VCO Voltage-Controlled Oscillator If the phase detector is of analog-multiplier type. Frequency synthesizer used in televisions or wireless communication systems to select different channels.17-1 CHUNG-YU WU CH 17 Phase-Locked Loops (PLLs) §17-1 General architecture and Operational Principle 1.

* Different PLLs => Different Hlp(s).Linearized small-signal analysis When a PLL is in lock. => φd= ω in − ω f r Vcntl = K l P K pd K l P K pd K osc 3. If a lead-lag lowpass filter is used in Hlp(s). Kpd.17-2 CHUNG-YU WU where ωin is the frequency of the input signal. which is equal to the frequency of VCO output when the PLL is in the locked state. as long as these changes are slow and small about their operating point. A signal-flow graph for the linearized small-signal model of a PLL when in lock: φin ( s ) + Kpd KlpHlp(s) Vcntl φosc ( s ) 1/s Vcntl(s)=KpdKlpHlP(s)[φin(s)-φosc(s)] dφ (t ) dt Kosc φosc(s)=Kosc(Vcntl(s)/s) (∵ω(t)= => φ ( s) = ω ( s) s ) SK pd K lP H lP ( s ) Vcntl ( s ) = φ in ( s ) S + K pd K lP K osc H lP ( s ) ∗ General transfer function applicable to almost every PLL. we have Hlp(s)= 1 + sτ z 1 + sτ p τz<<τp 1 S (1 + sτ z ) Vcntl ( s ) K osc = => Η(s) ≡ s 2τ p φ in ( s ) 1 1 + S( +τz) + K pd K lp K osc K pd K lp K osc * H(s)=0 as s→0 => ∆φin=0 leads to ∆Vcntl=0 . Kosc. its dynamic response to input-signal phase and frequency changes can be well approximated by a linear model.

577 → maximally flat group delay = 0.17-3 CHUNG-YU WU 1 S (1 + sτ z ) Vcntl ( s ) K osc = s 2τ p ω in ( s) 1 1 + S( +τz) + K pd K lp K osc K pd K lp K osc * Vcntl ( s ) ω in ( s ) s =0 = 1 K osc K pll The above second-order s-domain transfer functions have ωo and Q as ωo= K pd K lp K osc τp = τp = Q= τP 1 + τ Z K pd K lp K osc K pd K lp K osc τP 1 + τ Z K pll K pll * Q= → good settling behavior Q= Q= 1 3 1 2 = 0. when ωo<<ωfr.707 → maximally flat amplitude response 1 2 * Usually Q= 1 is recommended in PLLs 2 In most cases. we have τZ>> 1 2 K pll => Q ≅ τP τ z K pll ω oτ Z 2 τP 2 = K pll ω o = 1 = 1 2 => τZ = The transient time constant τpll of the complete loop for small phase or frequency changes can be expressed as τpll ≅ 1 ωo .

Solution: 1. the PLL remains in lock over a range as long as the input signal's frequency ωin changes only slowly. sweeping is disabled and PLL is activated. To add a frequency detector that detect when ωin-ωosc is large.Choose τZ to obtain the desired Q of the loop Ιf τZ =0.17-4 CHUNG-YU WU Design considerations: 1. When ωin-ωosc is small. the acquisition time tacq is tacq ≅ Q(ω i n − ω osc ) 2 ωo 3 * If a PLL is designed to have a narrow loop bandwidth ωo. This range is the lock range.Choosing Kpd and Kosc based on practical considerations 2. which is much larger than the capture range.Choose τp to achieve the desired loop settling time 3. 2. Lock : ωo↓ increase noise rejection. Capture range and acquisition time Capture range: The maximum difference between the input signals' frequency and the VCO free-running frequency where lock can eventually be attained. ωo= K pll Q 2 = K pd K osc Q (Klp=1) 4. Then drive the loop toward lock much more quickly. 3. When ωosc→ωin. Acquisition time: The time required to attain lock If the initial difference between the input signal's frequency and the VCO frequency is moderately large. Vcntl-max=Klp KM Ein Eosc =KlpKpd 2 => ωlck = ± KoscKlpKpd . To sweep the VCO's frequency range during acquisition with the PLL disabled. The capture range is on the order of the pole frequency of the lowpass filter. 5. Initial acquisition: ωo↑ speed up acquisition. => Q= τ P Kpll. To design the lowpass filter with a programmable pole frequency ωo. the frequency detector and the driver are disabled. Lock range Lock range: Once lock is attained. tacq can be quite large and lock is attained too slowly.

Also a sequential circuit actually. Sequential circuits (e. EXOR and Flip-Flop PDs): Operate on the information contained in the zero-crossings of the input signal to aid acquisition when the loop is out of lock. Also a sequential circuits actually.g. * The loop could lock to harmonics of the input signal. §17-2. Phase-frequency detector: Provide a frequency sensitive signal to aid acquisition when the loop is out of lock. =>False lock * ω1=ω2 is required. Analog phase detectors (PDs) or multipliers: Rely on the DC component when multiplying two sinusoidal waveforms of the same frequency. 2 2 * The multiplier PD is especially useful in applications where the reference frequency is too high and where the loop bandwidth is sufficiently narrow so that the filtering of the undesired components can be effective. 3. ω1=ω2 => Vpd= KM Ein Eosc [sin(θ1-θ2)+sin(2ωt+θ1+θ2)] 2 After the lowpass filter. §17-2. 2. we have Vpd=KlpKM Ein Eosc sin (θ1-θ2)=KM Ein Eosc sinθd ∝ θd if θd is small.1 Multiplier PD Vpd =KMEinsin(ω1t+θ1)Eosccos(ω2t+θ2) =KM Ein Eosc {sin[(ω1-ω2)t+θ1-θ2]+sin[(ω1+ω2)t+θ1+θ2]} 2 At phase lock.17-5 CHUNG-YU WU §17-2 Phase Detectors in PLLs Three categories: 1.2 EXOR PD (a) A B (b) τ A B T C C=A ⊕B .

This is a reference point.17-6 CHUNG-YU WU (c) Average value of C -1 -0. the output Vpd(c ) has ω=2ωin and 50% duty cycle. * False lock could occur * ω1=ω2 is required. . the most important harmonic is situated at the fundamental of the reference frequency as compared to the twice of reference frequency in the EXOR PD. Vpd ∝ θd for 0o<θd<180°. * At the center of the linear range of Vpd average. §17-2.5 1 τ T * when A(Vin) and B(Vosc) are 90° out of phase.5 0 0.5 1 τ T * The average value of Vpd or C has the shape of a saw tooth.3 Flip-Flop PD (a) A B S R Q C (b) A B C (c) Average value of C -1 τ T -0. with a linear range of a full cycle.5 0 0.

17-7 CHUNG-YU WU (a) EXOR PD Phase 0.4 Charge-pump PD VDD Ich Vin Vosc Sequential phase detector Pu Pd S1 S2 C1 C2 Vlp Ich R -VSS Charge-pump phase comparator Low-pass filter 1. Vin and Vosc are exactly in phase when the loops in lock. 2.5 Center of the linear range (b) Flip-flop PD 0 0.5 Center of the linear range 0 1 1 Average Fundamental 2nd Harmonic §17-2. 3. The PLL attains lock quickly even when ωin is quite different from ωfr. Desirable features: 1. It does not exhibit false lock. .

Small-signal analysis of a charge-pump PLL: The average charge flow into the lowpass filter is ∆φ Iavg= in Ich 2π Iavg=Kpd(φin-φosc)=Kpd∆φin I => Kpd= ch 2π For the lowpass filter R. Substituting Hlp(s) and Kpd into the transfer function we have Vlp ( s ) 1 = φ in ( s ) K osc φ in ( s ) S (1 + SRC1 ) S 2 C1 1 + SRC1 + K pd K osc C1 => ω o = Q= K pd K osc 1 1 1 2π = = RC1ω o R C1 K pd K osc R C1 I ch K osc . C1 has a transfer function Hlp(s) as Hlp(s)= Vin ( s ) 1 + SRC1 1 =R+ = I avg ( s ) SC1 SC1 Vlp ( s ) .17-8 CHUNG-YU WU Some typical waveforms of a charge-pump PD Vin Vosc ∆φin Pu 2π Pd Time 2.

Pu FF1 Pd FF2 Vin set1 Pu-dsbl FF3 Reset set2 Pd-dsbl FF4 Vosc set3 set4 * Basic operating principle: Assume the PLL is in lock with Vin leading Vosc Initial conditions: Pu=0. Vosc=0 inputs: 1001 . Reset=0 Vin=0. Phase/Frequency detector (PFD) * The most common sequential phase detector is the PFD. (2) ωo is chosen according to the desired transient settling-time constant τpll as ωo= 1 τ pll (3) C1 is chosen from the equation of ωo whereas R is chosen using the equation of Q. C2 => Q↑ => chosen Q value is smaller => Exact Q. R↑ => Q↓ (4) Add C2 to minimize glitches. The chosen Q value is slightly less than what is eventually desired. * 4 NOR-type RS flip-flops. * Asynchronous sequential logic circuit. Pu-dsbl=0. Pd-dsbl=0. * Can also be realized in NAND gates.17-9 CHUNG-YU WU 3. Design Considerations: (1) Choose Ich based on practical consideration like power dissipation and speed. Pd=0. C2 ≅ 1 ~ 1 of 8 10 C1 => Ηlp(s)= R 1 + 1 + SRC 2 SC1 4.

* Transfer characteristic of a charge-pumping PFD (a) Ref Div Up PFD Dn I IC I Zlf . Vin Vosc Pu Pd Pu-dsbl Pd-dsbl ωin>ωosc => Pu=1 => Charge pumping to increase ωosc until lock is achieved. => FF3 is reset and Pu-dsbl=0 It is only when Vin 1→0 Vosc 1→0 => FF4 is reset and Pd-dsbl=0 * The waveforms of a PFD when Vin is at a higher frequency than Vosc. Pd 0→1→0 Pu-dsbl=1 and Pd-dsbl=1 after two gate-delays.17-10 CHUNG-YU WU Vin→1 Vosc→1 => Pu=1 => Charge pumping starts and Vlp ↑=> ωosc↑ => Reset nor gate inputs: 0001→0000 => Reset 0→1 => Pu=0 and Pd=0 after one gate-delay . => Reset 1→0 after one gate-delay of Pu-dsbl→1 and Pd-dsbl→1 or after three gate-delays of Vosc→1. => Κeeping Pu=0 and Pd=0 => Νο charge pumping.

1 First-order PLL with zero-order loop filter Loop gain of the feedback structure with φin(s) and Vcntl(s) Loop gain=GH(s)=Kpd Klp KoscHlp(s) Zero-order loop filter: Hlp(s)=1 => GH(S)=KpdKlpKosc 1 s 1 s log GH ( ω ) Bode plots of GH(s): 0 ω c ω PLL with zero-order loop filter => First-order type-1 PLL SK pd K lp Vcntl ( s ) = φ in ( s ) S + K pd K lp K osc close-loop transfer function φ GH ( ω ) 0 -90 ω .17-11 CHUNG-YU WU (b) Ref Div IC (c) Average value of C -1 -0.5 0 0.5 1 τ T §17-3 Loop Filters and Loop Gains §17-3.

a compensating zero ωz must be introduced in order to keep the phase margin high enough. log GH ( ω ) 2nd-order loop filter: Hlp(s)= (1 + S / ω z ) (1 + S / ω p )(1 + S / ω a ) ωa ω z ωc => GH(S)= K pd K lp K osc (1 + S / ω z ) S (1 + S / ω p )(1 + S / ω a ) Bode plots of GH(S): 0 ωp ω => Third-order type-1 PLL S (1 + S / ω z ) K pd K lp Vcntl ( s ) = φ in ( s ) S (1 + S / ω p )(1 + S / ω a ) + K pd K lp K osc (1 + S / ω z ) φ GH ( ω ) If ωa=0 => Third-order type-2 PLL. 0 -90 -180 ω . a low-frequency pole ωa is introduced in the loop filter.17-12 CHUNG-YU WU §17-3. To compensate the extra phase shift.3 Third-order PLL with second-order loop filter To improve the transient characteristics of the PLL.2 Second-order PLL with first-order loop-filter First-order loop filter: Hlp(s)= K pd K lp K osc 1 1 + S /ω p log GH ( ω ) Bode plots of GH(s): => GH ( s ) = ω p K pd K lp K osc S (1 + S / ω p ) S 2 + ω pS = 0 ωc ωp ω PLL with first-order loop filter => 2nd-order type-1 PLL Sω p K pd K lp Vcntl ( s ) = 2 φ in ( s ) S + ω p S + ω p K pd K lp K osc φ GH ( ω ) 0 -90 -180 ω §17-3. => Extra phase shift of 90°.

low phase noise. Electrical tuning range The VCO must be able to cover the complete required frequency band of the application. including initial frequency offsets due to process variations. i.e. 3.17-13 CHUNG-YU WU §17-3. phase stability: The output spectrum of the VCO should approximate as good as possible the theoretical Dirac-impulse of a single sine wave. ω+∆ω ) units: dBc/Hz carrier power ∆ω: offset frequency ∆ω ωo VCO output 1Hz ω 2. the VCO gain Kosc should be .4 Third-order type-2 charge-pump PLL Hlp(s)= 1 + sτ z s (C Z + C p )[1 + sτ p ] τz= RzCz τp=Rz(Cz-1+Cp-1)-1 => GH(s)= K pd K lp K osc (1 + sτ z ) S 2 (C z + C p )(1 + sτ p ) Loop filter: Rz Cz Cp §17-4 Voltage-Controlled Oscillators (VCOs) Basic VCO specifications/requirements: 1. Tuning linearity To simplify the design of the PLL. The definition of phase noise: L{∆ω}=10 log ( noise power in a 1-Hz bandwidth at freq.

17-14 CHUNG-YU WU constant. * Power consumption ↑ linearly => phase noise↓ * Typical phase noise: -94dBc/Hz at 1 MHz offset from a 2. -83dBc/Hz at 100 KHz offset from a 900MHz carrier. pp.1386-1393. Frequency pulling The dependence of the center frequency 6. 4. Td: one inverter delay. Low cost §17-4. * High phase noise: ∵switching action introduces a lot of disturbances.23. * Tuning: varying the current of the inverters. §17-4.2GHz carrier.1 Relaxation oscillator as VCO * Multivibrator-based nonlinear oscillator. Differential two-stage ring oscillator + + . 5. Three-stage ring oscillator inverter 2. * Circuit structure 1. phase noise value of -90dBc/Hz at 500KHz offset.- + + . 1988.- . Frequency pushing (MHz/V) The dependency of the center frequency on the power supply voltage. Ref. * fosc~in the order of a few 100 MHz * In CMOS.2 Ring oscillator as VCO * Tosc=2n•Td n: number of inverters. vol. Dec.: IEEE JSSC.

7µm CMOS planar-LC VCO. §17-4. Design example: 0. 1-stage-delay ring oscillator Gm Gm Gm * fosc MHz ~ GHz Ref. pp. IEEE JSSC.331-334. 2.: 1. of IEEE 1995 Custom Integrated Circuits Conference (CICC). March 1996. * The realization of the inductor is the key point.3 LC-oscillator as VCO * Typically a 20dB better phase noise obtained over ring and relaxation oscillators. * High-speed operation is possible due to the simple working principle. pp. vol.331-334. Proc.17-15 CHUNG-YU WU 3.31. M4 L1 M3 L2 Vc Ibias Vout+ M1 C1 C2 VoutM2 .

. (Die size 750×750 µm2) L1 and L2 area consuming Inductors used in output buffers Measurement results: 1. Measured output spectrum for a carrier frequency of 1.81 GHz.2nH planar spiral inductors * p+ − n-well junction diodes C1 and C2 as varactors for frequency tuning by Vc.17-16 CHUNG-YU WU * Constant current => To limit power dissipation * M1 and M2: To provide a negative resistance for oscillation * L1=L2=3. C1=C2 ≅ 1pF * Different output voltage. Chip photograph of the VCO.

the diode varactors C1 and C2 have a larger leakage current => Phase noise ↑ 3dB.17-17 CHUNG-YU WU 2. . Measured frequency tuning characteristics * At Vc=0. frequency offset Phase noise: -116dBc/Hz at 600 KHz offset 3.r. Measured phase noise w.t.5V.

stacked with mixer 0. extra thick metal.8 [Based ESSC94] 1-um CMOS [Soyue 12-GHz JSSC96a] BiCMOS [Ali ISSCC96] 25-GHz Bip 1. tuning with 2 tanks Wide metal turns.* Relaxation oscillators [Banu JSSC88] 0.2-um CMOS CICC95] [Razav JSSC96] 0.4 30 ? 100 100 -118 @1MHz -110 @1MHz -90 -92 Tuning from low freq. Fast start-up Comparison of 3 designs Three-stage.56 50 100 -90 @500kHz -81 Tuning from 100kHz to1GHz Reference [Sneep JSSC90] 3-GHz Bip [Dobos 9-GHz Bip CICC94] Ring oscillators [Kwasn 1.89 @100kHz -97 -94 @1MHz -106 @2MHz -91 -96 [vd Tan 9-GHz BiCMOS 2. to 150MHz Tuning from 800kHz to 800MHz.0 2. planar inductors -101 @100kHz -110 *at 600 kHz offset from a 1.5 NA NA 6 NA 95 . differential gain stage Two-stage CCO.2 6.5-um CMOS 0.1 0.A.75-um CMOS 0.8-GHz carrier . Power Tuning Phase noise [dBc/Hz] [-] [GHz] [mW] [%] reported equiv. -88 @100kHz -95 @100kHz -92 @100kHz -104 -105 -110 High-ohmic substrate.9 70 16 50 10 10 0 0 N.74 2.4 Comparisons of Integrated VCOs Remarks Technology Freq.0 ISSCC97] LC-tuned oscillators [Nguye JSSC92] 10-GHz Bip 1.17-18 CHUNG-YU WU §17-4. high-ohmic substrate Complete PLL. substrate back-etched 4-level.4 0.

5-um BiCMOS 4.7-um CMOS 0.4-um CMOS 1. conductive substrate. standard CMOS -115 @ 200kHz -124 -116 @ 600kHz -116 -113 @ 200kHz -122 .6-um CMOS [Steya EL94] [Crani JSSC95] [Crani JSSC97] [Crani CICC97] 6-GHz Bip 0.0 [Razav ISSCC97] 0.17-19 CHUNG-YU WU Reference Technology [-] Freq.7-um CMOS 0.8 1.6 0..1 µm) and field oxide (11µm) Linear tuning. capacitor bank for extended tuning LC-tuned oscillators(cont'd) [Rofou ISSCC96] 1-um CMOS [Soyue JSSC96b] 0.1 1.2 1.6-um CMOS 1. enhanced LC-tank 2-level metal. Power Tuning Phase noise [dBc/Hz] Remarks [GHz] [mW] [%] reported equiv. 0. quadrature signals Thick metal (2. standard CMOS 2-level metal.5 [Janse ISSCC97] 15-GHz Bip [Parke CICC97] Presented designs 2. quadrature signals Hollow rectangular coils standard process High-Q MIS capacitor and varactor Full PLL circuit.8 1.8 [Dauph ISSCC97] 11-GHz BiCMOS 1.40 14 12 15 40 43 NA 9 7 10 11 12 -85 @ 100kHz -95 -106 @ 1MHz -109 -100 @ 500kHz -102 -105 @ 100kHz -119 -99 @ 100kHz -116 -105 @ 200kHz -114 Front-etched inductors.8 1 24 6 11 0 5 14 20 -75 @ 10kHz -106 Bonding wire inductor Bonding wire inductor.9 10.

2 GHz monolithic quadrature mixer oscillator for direct-conversion satellite receivers".a 1. 331-343. 31.9-2. 3. [Based ESSC94] P. December 1998. in Proc. 1386-1393. San Diego. [Kwasn CICC95] T. February 1997. in Proc.17-20 CHUNG-YU WU [Banu JSSC88] M. Zimmerman. Bouchet. San Fransisco. vol. March 1992. San Diego. no. and J. IEEE Journal of Solid-State Circuits. 8. Gaussorgues. Jensen. pp. M.1-4. USA. Abou-Seido. G. 692-698. M. [Sneep JSSC90] J.5-V monolithic LC oscillator in 1-µm CMOS". [Razav JSSC96] B. no. June 1990. vol. in Proc. 1. 88-89. Razavi.4. "A 1. Nguyen and R. of the IEEE 1994 Custom Integrated Circuits Conference. F. vol. "A 1-GHz. A. 6. 3. IEEE Journal of Solid-State Cir cuits. 27. Dobos and B. USA. M. 444-450. [Nguye JSSC92] N. "A 0. J. in ISSCC Digest of Technical Papers. "A new low-noise 100-MHz balanced relaxation oscillator". "A study of phase noise in CMOS oscillators". G. pp. Basedau and Q. van der Tang and D. 23. USA. of the IEEE 1995 Custom Integrated Circuits Conference. [Dobos CICC94] L. of the 1994 European . Meyer. "A versatile monolithic 800-kHz to 800-MHz phase-startable oscillator".8-GHz monolithic LC voltage controlled oscillator". Verhoeven. "Inductorless oscillator design for personal communication devices . March 1996. 327-330.2-µm CMOS process case study". IEEE Journal of Solid-State Circuits. [vdTan ISSCC97] J. pp. vol. Kasperdovitz. no. pp. Kwasniewski. Sneep and C. Huang. pp. pp. 25. May 1994. "MOS oscillators with multi-decade tuning range and gigahertz maximum speed". pp. 3. IEEE Journal of Solid-State Circuits. May 1995. no. Banu.

K. in ISSCC Digest of Technical Papers. pp. February 1996. A. Ewen. J. D. J. February 1996. J. . pp. San Fransisco. 390-391 [Janse ISSCC97] B.31.1 to 2. San Fransisco. Dauphinee. San Fransisco. Abidi. Ainspan. pp. Hulvey. [Soyue JSSC96b] M. in ISSCC Digest of Technical Papers. in ISSCC Digest of Technical Papers. pp. pp. no. Ponnapalli. "A balanced voltage-controlled oscillator with an integrated 1. USA. Canora. S. 392-393. USA. and P. in ISSCC Digest of Technical Papers. USA. December 1996. "A 2. IEEE Journal of Solid-State Circuits. E. September 1994. pp. Rofourgan. vol. Soyuer. USA. [Rofou ISSCC96] A. Negus. F. Tham. 31. [Razav ISSCC97] B. and D.5-GHz LC-resonator". J. Burghartz. 2042-2045. "A 1. 12.2. M. Pence. [Soyue JSSC96a] M. San Fransisco. N. Lee. USA. A. "A 900-MHz frequency synthesizer with integrated LC voltage-controlled oscillator". A. K. San Fransisco. Ali and L. "A 900-MHz CMOS LC-oscillator with quadrature outputs". Ulm. Jenkins. H.4-GHz silicon bipolar oscillator with integrated resonator". Jansen. 388-389.17-21 CHUNG-YU WU Solid-State Circuits Conference. Razavi. February 1997. N. M. [Ali ISSCC96] A. February 1996. Burghartz. pp.8-GHz CMOS voltage-controlled oscillator". Rofourgan. vol. Soyuer. Copeland. 392-393. Schvan. no. February 1997. 390-391. F. "A 3-V 4-GHz voltage-controlled oscillator with integrated resonator". K. pp. in ISSCC Digest of Technical Papers. J. IEEE Journal of Solid-State Circuits. 268-270. and M. Rael. [Dauph ISSCC97] L. and W. Jenkins.2 GHz with fully integrated tank and tuning circuits. "Silicon bipolar VCO family for 1. 172-175. and A. February 1997.

December 1995. "1. Parker and D. 1474-1482. 403-406. [Steya EL94] M. Steyaert.6-ghz CMOS PLL with on-chip loop filter".8-GHz low-phase noise CMOS VCO using optimized hollow inductors". of the IEEE 1997 Custom Integrated Circuits Conference. 30. USA. IEEE Journal of Solid-State Circuits. Craninckx. [Crani JSSC97] J. May 1997. pp. 4. USA. Craninckx and M. 12. "A 1. pp. of the IEEE 1997 Custom Integrated Circuits Conference. Steyaert and J. 736-744. Steyaert. no. IEE Electronic Letters. 407-410. 3rd February 1994. 30. no. [Crani JSSC95] J. pp. 3. Santa Clara. pp. in Proc. IEEE Journal of Soild-State Circuits. Ray. Craninckx and M. Craninckx and M. 32. Santa Clara. no. May 1997. "A fully integrated spiral-LC CMOS VCO set with prescaler for GSM and DCS-1800 systems".17-22 CHUNG-YU WU [Parke CICC97] J. May 1997. "A low-noise 1. pp. vol. "A 1. [Crani CICC97] J.8-GHz low-phase-noise voltage controlled oscillator with prescaler". 244-245. Steyaert. vol.1-GHz oscillator using bond-wire inductance". . vol. in Proc.

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