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DIGITAVID, Inc. Ahmed Abu-Hajar, Ph.D. email@example.com
What is Phase Locked Loop (PLL) Basic PLL System Problem of Lock Acquisition Phase/Frequency Detector (PFD) Charge Pump PLL Application of PLL
What is Phase Locked Loop (PLL) PLL is an Electronic Module (Circuit) that locks the phase of the output to the input. Vi(t) Phase Locked Loop Vo(t) .
Locked Vs. Unlocked Phase Example of locked phase Vi(t) Vo(t) Example of unlocked phase Vo(t) Vi(t) Phase Error ( ∆φ) .
detects ∆φ between the output and the input through feedback system Voltage Control Oscillator (VCO) adjusts the phase difference . Vi(t) VI ∆φ Phase Detector VCO Vo Phase Locked Loop Vo(t) The Phase Detector (PD).Basic PLL System PLL is a feedback system that detects the phase error ∆φ and then adjusts the phase of the output.
Implementation of PD Phase Detector is an XOR gate VI V1 Vo ∆φ ∆φ Phase Detector VCO Vo ∆ϕ Vo(t) 1 VI ≠ Vo = 0 VI = Vo Vi(t) Phase Error ( ∆φ) .
– That is why the module is called Voltage Control Oscillator VControl VCO ω ω ω0 VControl ω = ωo + KVCO VControl Vcontrol must be in the steady state for the VCO to operate properly .What is VCO ? VCO is a circuit module that oscillates at a controlled frequency ω. The Oscillating Frequency is controlled using Voltage VControl.
The control signal slows down or speeds up the VCO module. hence.Simple PLL Structure – – – – Phase Detector ( XOR ) that detects the phase error ∆φ Low Pass Filter ( to smooth ∆φ ) Voltage Control Oscillator (VCO) If VI and Vout are out of phase (unlocked). the phase is corrected (locked) VI Vout ∆φ Phase Detector LPF VControl ∆φ VCO Vout Basic Idea . then the PD module detects the error and the LPF smoothes the error signal.
Locked Condition – Locked Condition d (ϕin − ϕout ) = 0 dt – This implies that ωin = ωout VI Vout ∆φ Phase Detector LPF VControl ∆φ VCO Vout .
ω ω1 The PLL is in the Locked state ω0 V1 VControl VControl V1 φ0 .Example: In the UNLOCKED State VI and Vout has ∆φ at the same Vi(t) frequency ω1 Vo(t) The phase detector must Phase Error produce VI ( ∆φ) Hence. VCO is dynamically changing and PD is creating VControl VControl to adjust for the phase difference.
In the UNLOCKED State For Simplicity and by using Fourier Series Let VI = VA cos (ω1t ) Vout = VB cos (ω1t + ϕo ) Due to ∆φ. PD creates Vcontrol VCO will change ωout = ω1 + KVCO VControl The output voltage becomes Vout = VB cos (ω1t + ϕo − ∆ϕ (t ) ) .
Dynamics of Simple PLL PLL is a feedback system – – – PD is a gain amplifier LPF be first order filter ( as an example) VCO is a unit step module The transfer function of the feedback system is given as: 2 Φ out ωout ωn H ( s) = ( s) = ( s) = 2 2 ωin s + 2ςωn s + ωn Φ in H ( s) = K PD KVCOωLPF s 2 + ωLPF s + K PD KVCOωLPF LPF PD φin 1 KPD VCO 1+ s ωLPF KVCO s φout .
Transient Response to PLL The unit step response to second order system – – – – – – Overdamped Critically damped Underdamped Settling time Vs. ripple of Vcontor Stability of the system Lacks performance in ICs ωi Problems with this PLL t ωout 2 Φ out ωout ωn H ( s) = ( s) = ( s) = 2 ωin LPF s + 2ςωn s + ωn2 Φ in PD φin 1 KPD VCO t φout 1+ s ωLPF KVCO s .
Problem of Lock Acquisition When PLL is turned on. PD LPF1 VCO Vin ωin FD LPF2 Vout ωout . the output frequency is far from the input frequency It is possible that the PLL would never lock Modern PLL uses FREQUENCY DEDECTOR (FD) in addition to the PD.
QB changes its state and QA remains unchanged A B QB QA A B QB QA .Phase/Frequency Detector (PFD) One Module that detects both frequency and phase differences This module senses the transition in A or B Initially A leads B A 0 0 1 XX A 0 0 0 0 1 0 0 B 0 0 1 XX B 0 0 1 QA 0 0 1 1 0 QA 0 0 0 0 0 QB 0 0 0 0 0 QB 0 0 1 0 0 A B PFD QA QB Initially B leads A If A leads B. QA changes its state and QB remains unchanged If B leads A.
QB = “1” momentarily The AND gate RESETs Both to Qs “0” D Q A VDD CK QA If B leads to “1” QB = “1” – – D Q B CK QB When A becomes “1”. QA = “1” momentarily The AND gate RESETs Both to Qs “0” .Hardware Implementation of PFD Uses two Edge Triggering modules using D-FF If A leads to “1” QA = “1” – – VDD When B becomes “1”.
Hardware Implementation of PFD VDD A B QB QA RES D Q B CK QB A VDD D Q CK QA RES A B QB QA RES The Vout is the average of (QA – QB) is used to detect the phase and the frequency difference .
ripple Vcontrol.. Use Charge Pump PLL VCO D Q Vout φout ωout CK QB .The Basic Block diagram VDD Structure – PFD – LPF Vin – Differential φin Amplifier ωin – VCO – Negative Feedback V DD D Q CK QA Disadvantage: Sensitive to noise and offset voltages. .
Charge Pump PLL Structure – PFD – Two switches controlled by QA and QB – Capacitor VDD VDD D Vin φin ωin VDD Q CK QA IC = C d VC dt d VC I = C dt C VCO D Q – – – VCO Negative Feedback It charges or discharges the capacitor indefinitely Vout φout ωout CK QB .
Charge Pump PLL The capacitor is replaced with a LPF (Cp and Rp) to improve the phase margin for stability The transfer function of the system is approximated as follows: VDD VDD D Vin φin ωin VDD Q CK QA I P KVCO ( RPCP s + 1) 2π CP H (s) = I I K s 2 + P KVCO RP s + P VCO KVCO 2π 2π CP Rp slows down the system VCO CP D Q RP QB Vout φout ωout CK .
Application of PLL Frequency Multiplications – – The feedback loop has frequency division Frequency division is implemented using a counter VI PFD ∆φ LPF VControl ∆φ Counter (Frequency Division) VCO Vout Clock Skew Reduction Buffers are used to distribute the clock Embed the buffer within the loop .
Application of PLL Clock Skew Reduction – – VI PFD Vout ∆φ LPF VControl ∆φ VCO Vout Buffers are used to distribute the clock Embed the buffer within the loop Buffer Jitter Reduction .