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Verilog Two-Day Introductory Course Slides

# Verilog Two-Day Introductory Course Slides

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This contains the instructor material for the authors two-day course on the Verilog language. The course presentation is posted elsewhere on Scribd.
This contains the instructor material for the authors two-day course on the Verilog language. The course presentation is posted elsewhere on Scribd.

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08/12/2015

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## Sections

• Schedule
• Some Hardware Terminology
• Some Software Terminology
• The Verilog Module
• Outline of a Module
• Example of a Module
• Lab 1: Minilab Flip-Flop
• Basic Verilog Data Types
• Bits and Vectors: Bits
• Bits and Vectors: Vectors
• Bits and Vectors: Width Rules
• reg Variables
• reg Variable Example
• wire Variables
• wire Variable Connection
• wire Variable Example
• wire Variable Contention Example
• integer Variables
• integer Variable Example
• End Verilog Variables
• Basic Verilog Operators
• Logical Operators
• Bitwise Operators
• Unary Bitwise Operators
• Arithmetic Operators
• Relational Operators
• Shift Operators
• Conditional Operator
• End Basic Verilog Operators
• Sequential RTL
• RTL Procedural Control: if
• RTL Procedural Control: case
• RTL Procedural Control: for
• RTL Expressions & Statements
• Expressions & Statements in RTL Mux
• Expressions & Statements in RTL Flip-Flop
• RTL Last Statement Wins
• RTL Blocking Assignment
• Blocking Assignments in a Testbench
• D Flip-Flop Testbench Example
• D Flip-Flop Testbench, Clock Disentangled
• RTL NonBlocking Assignment
• NonBlocking Assignment in a Flip-Flop
• NonBlocking Assignment in a Clock Generator
• RTL Last Statement Wins, Again
• End Basic RTL
• Lab 2: Sequential Device
• More on Verilog Operators
• Operator List (complete)
• Operator Precedence Table
• The Concatenate Operator
• End Verilog Operators
• Sensitivity Lists
• always Block Sensitivity
• always Block Change Control
• always Block Edge Control
• initial Block Sensitivity
• Continuous Assignment (assign) Sensitivity
• Primitive Instantiation Sensitivity
• End Simulation Control and Sensitivity
• Latch Inference
• Avoid Synthesis of Latches
• A Good Transparent Latch Model
• Latches and Muxes
• Latching By Mistake
• End Synthesis Issues
• Lab 3: ALU Schematic
• Lab 3: ALU Function Table
• Day 2
• Delays and Synchronization
• Whence That Delay?
• Blocking and Nonblocking Statements
• Undelayed Blocking and Nonblocking Statements
• Example of Undelayed Statements
• Effect of Clocking by Nonblocking Assignment
• Delayed Blocking and Nonblocking Statements
• Clocks and Asynchronous Controls
• Clock Inference
• Asynchronous Control Priority
• End Delays and Synchronization
• Structural Design
• Structural Design Port Mapping
• Port Mapping by Name
• Port Mapping by Position
• Port mapping by position:
• Verilog Primitive Gates
• Verilog Logic Gate Examples
• Verilog Buffer Gate Examples
• Multivalue Delays
• Simulation of wire Delays
• Timing Triplets
• Timing Triplet:
• End Delays
• Shift Registers
• Verilog Shifting
• Shift Register Schematic
• Lab 4: Structural and RTL Shift Registers
• Lab 4: Structural Shift Register
• Lab 4: RTL Shift Register
• Verilog Comments, Strings, and Messages
• Compiler Directives (Macroes)
• `define Compiler Directive Example
• Timescale Compiler Directive
• Verilog Simulator Strings
• Verilog Message Format Specifiers
• Numerical Format Width Specifiers
• End Comments, Strings, and Messages
• Vectors Again
• Vector Selects
• Vector Bit-Reversal
• Arrays
• Array Example: Simple RAM
• End Vectors and Arrays
• Modelling Sequential Logic
• Review: Verilog Rules of Thumb
• Lab 5: Counter-Decoder Design
• Lab 5: Decoder Basics
• The Lab 5 Decoder
• Wrap-up Lecture: The Value of Synthesis
• Wrap-up Lecture: Constructs Not Covered
• That's It

# Slides for

Essentials of Verilog
A Si l i con Val l ey Techni cal I nsti tute Workshop
by J ohn Michael Williams
2010-06-24
Copyright ÿ ÿÿ ÿ 2010, J ohn Michael Williams.
Licensed free to Silicon Valley Technical Institute for training-course use. All other
rights reserved.
jmmwill@comcast.net
2010-06-24 Essenti al s of Veri l og
List of Slides
Essenti al s of Ver i l og .................................................................................................................................................................................... 1
Schedul e....................................................................................................................................................................................................... 2
Some Har dwar e Ter mi nol ogy...................................................................................................................................................................... 3
Some Softwar e Ter mi nol ogy........................................................................................................................................................................ 4
The Ver i l og Modul e ..................................................................................................................................................................................... 5
Outl i ne of a Modul e ..................................................................................................................................................................................... 6
Exampl e of a Modul e ................................................................................................................................................................................... 7
Lab 1: Mi ni l ab Fl i p-Fl op............................................................................................................................................................................. 8
Basi c Ver i l og Data Types ............................................................................................................................................................................ 9
Bi ts and Vector s: Bi ts ............................................................................................................................................................................... 10
Bi ts and Vector s: Vector s.......................................................................................................................................................................... 11
Bi ts and Vector s: Wi dth Rul es.................................................................................................................................................................. 12
r eg Var i abl es.............................................................................................................................................................................................. 13
r eg Var i abl e Exampl e ................................................................................................................................................................................ 14
wi r e Var i abl es ............................................................................................................................................................................................ 15
wi r e Var i abl e Connecti on .......................................................................................................................................................................... 16
wi r e Var i abl e Exampl e .............................................................................................................................................................................. 17
wi r e Var i abl e Contenti on Exampl e ........................................................................................................................................................... 18
i nteger Var i abl es ....................................................................................................................................................................................... 19
i nteger Var i abl e Exampl e.......................................................................................................................................................................... 20
End Ver i l og Var i abl es................................................................................................................................................................................ 21
Basi c Ver i l og Oper ator s............................................................................................................................................................................. 22
Logi cal Oper ator s ...................................................................................................................................................................................... 23
Bi twi se Oper ator s ...................................................................................................................................................................................... 24
Unar y Bi twi se Oper ator s........................................................................................................................................................................... 25
Ar i thmeti c Oper ator s................................................................................................................................................................................. 26
Rel ati onal Oper ator s ................................................................................................................................................................................. 27
Shi ft Oper ator s .......................................................................................................................................................................................... 28
Condi ti onal Oper ator ................................................................................................................................................................................. 29
End Basi c Ver i l og Oper ator s ..................................................................................................................................................................... 30
Sequenti al RTL .......................................................................................................................................................................................... 31
RTL Pr ocedur al Contr ol : i f ....................................................................................................................................................................... 32
RTL Pr ocedur al Contr ol : case .................................................................................................................................................................. 33
RTL Pr ocedur al Contr ol : for ..................................................................................................................................................................... 34
RTL Expr essi ons & Statements ................................................................................................................................................................ 35
Expr essi ons & Statements i n RTL Mux.................................................................................................................................................... 36
2010-06-24 Essenti al s of Veri l og
Expr essi ons & Statements i n RTL Fl i p-Fl op ............................................................................................................................................ 37
RTL Last Statement Wi ns ......................................................................................................................................................................... 38
RTL Bl ocki ng Assi gnment......................................................................................................................................................................... 39
Bl ocki ng Assi gnments i n a Testbench....................................................................................................................................................... 40
D Fl i p-Fl op Testbench Exampl e................................................................................................................................................................ 41
D Fl i p-Fl op Testbench, Cl ock Di sentangl ed.............................................................................................................................................. 42
RTL NonBl ocki ng Assi gnment .................................................................................................................................................................. 43
NonBl ocki ng Assi gnment i n a Fl i p-Fl op ................................................................................................................................................... 44
NonBl ocki ng Assi gnment i n a Cl ock Gener ator ....................................................................................................................................... 45
RTL Last Statement Wi ns, Agai n ............................................................................................................................................................. 46
End Basi c RTL ........................................................................................................................................................................................... 47
Lab 2: Sequenti al Devi ce .......................................................................................................................................................................... 48
Mor e on Ver i l og Oper ator s ........................................................................................................................................................................ 49
Oper ator Li st (compl ete)............................................................................................................................................................................ 50
Oper ator Pr ecedence Tabl e ....................................................................................................................................................................... 51
The Concatenate Oper ator ........................................................................................................................................................................ 52
End Ver i l og Oper ator s............................................................................................................................................................................... 53
Sensi ti vi ty Li sts ......................................................................................................................................................................................... 54
al ways Bl ock Sensi ti vi ty............................................................................................................................................................................ 55
al ways Bl ock Change Contr ol .................................................................................................................................................................... 56
al ways Bl ock Edge Contr ol ........................................................................................................................................................................ 57
i ni ti al Bl ock Sensi ti vi ty ............................................................................................................................................................................. 58
Conti nuous Assi gnment (assi gn) Sensi ti vi ty ............................................................................................................................................ 59
Pr i mi ti ve I nstanti ati on Sensi ti vi ty ........................................................................................................................................................... 60
End Si mul ati on Contr ol and Sensi ti vi ty ................................................................................................................................................... 61
Latch I nfer ence.......................................................................................................................................................................................... 62
Avoi d Synthesi s of Latches........................................................................................................................................................................ 63
A Good Tr anspar ent Latch Model ............................................................................................................................................................. 64
Latches and Muxes .................................................................................................................................................................................... 65
Latchi ng By Mi stake ................................................................................................................................................................................. 66
End Synthesi s I ssues ................................................................................................................................................................................. 67
Lab 3: ALU Schemati c.............................................................................................................................................................................. 68
Lab 3: ALU Functi on Tabl e ...................................................................................................................................................................... 69
Day 2............................................................................................................................................................................................................... 70
Del ays and Synchr oni zati on...................................................................................................................................................................... 70
Whence That Del ay?.................................................................................................................................................................................. 71
Bl ocki ng and Nonbl ocki ng Statements ..................................................................................................................................................... 72
Undel ayed Bl ocki ng and Nonbl ocki ng Statements ................................................................................................................................... 73
2010-06-24 Essenti al s of Veri l og
Exampl e of Undel ayed Statements ........................................................................................................................................................... 74
Effect of Cl ocki ng by Nonbl ocki ng Assi gnment ........................................................................................................................................ 75
Del ayed Bl ocki ng and Nonbl ocki ng Statements ....................................................................................................................................... 76
Cl ocks and Asynchr onous Contr ol s ........................................................................................................................................................... 77
Cl ock I nfer ence .......................................................................................................................................................................................... 78
Asynchr onous Contr ol Pr i or i ty.................................................................................................................................................................. 79
End Del ays and Synchr oni zati on .............................................................................................................................................................. 80
Str uctur al Desi gn ...................................................................................................................................................................................... 81
Str uctur al Desi gn Por t Mappi ng............................................................................................................................................................... 82
Por t Mappi ng by Name ............................................................................................................................................................................. 83
Por t Mappi ng by Posi ti on .......................................................................................................................................................................... 84
Ver i l og Pr i mi ti ve Gates ............................................................................................................................................................................. 85
Ver i l og Logi c Gate Exampl es .................................................................................................................................................................... 86
Ver i l og Buffer Gate Exampl es................................................................................................................................................................... 87
Mul ti val ue Del ays ..................................................................................................................................................................................... 88
Si mul ati on of wi r e Del ays ......................................................................................................................................................................... 89
Ti mi ng Tr i pl ets .......................................................................................................................................................................................... 90
End Del ays................................................................................................................................................................................................. 91
Shi ft Regi ster s ........................................................................................................................................................................................... 92
Ver i l og Shi fti ng.......................................................................................................................................................................................... 93
Shi ft Regi ster Schemati c ........................................................................................................................................................................... 94
Lab 4: Str uctur al and RTL Shi ft Regi ster s .............................................................................................................................................. 95
Lab 4: Str uctur al Shi ft Regi ster ............................................................................................................................................................... 96
Lab 4: RTL Shi ft Regi ster ......................................................................................................................................................................... 97
Ver i l og Comments, Str i ngs, and Messages ............................................................................................................................................... 98
Ver i l og Comments ..................................................................................................................................................................................... 99
Compi l er Di r ecti ves (Macr oes)................................................................................................................................................................ 100
`defi ne Compi l er Di r ecti ve Exampl e ....................................................................................................................................................... 101
Ti mescal e Compi l er Di r ecti ve ................................................................................................................................................................. 102
Ver i l og Si mul ator Str i ngs........................................................................................................................................................................ 103
Ver i l og Messagi ng System Tasks ............................................................................................................................................................ 104
Ver i l og Message For mat Speci fi er s ......................................................................................................................................................... 105
Numer i cal For mat Wi dth Speci fi er s ....................................................................................................................................................... 106
End Comments, Str i ngs, and Messages .................................................................................................................................................. 107
Vector s Agai n........................................................................................................................................................................................... 108
Vector Sel ects........................................................................................................................................................................................... 109
Vector Bi t-Rever sal .................................................................................................................................................................................. 110
Ar r ays ...................................................................................................................................................................................................... 111
2010-06-24 Essenti al s of Veri l og
Ar r ay Exampl e: Si mpl e RAM................................................................................................................................................................. 112
End Vector s and Ar r ays .......................................................................................................................................................................... 113
Model l i ng Sequenti al Logi c ..................................................................................................................................................................... 114
Revi ew: Ver i l og Rul es of Thumb ............................................................................................................................................................ 115
Lab 5 I ntr oducti on ................................................................................................................................................................................... 116
Lab 5: Counter -Decoder Desi gn ............................................................................................................................................................. 117
Lab 5: Decoder Basi cs ............................................................................................................................................................................. 118
The Lab 5 Decoder ................................................................................................................................................................................... 119
End of Ver i l og Cour se.............................................................................................................................................................................. 120
Wr ap-up Lectur e: The Val ue of Synthesi s ............................................................................................................................................. 121
Wr ap-up Lectur e: Constr ucts Not Cover ed............................................................................................................................................ 122
Wr ap-up Lectur e: Par ti ng Advi ce .......................................................................................................................................................... 123
That's I t ................................................................................................................................................................................................... 124
2010-06-24 Essenti al s of Ver i l og Sl i de 1
Essenti al s of Veri l og
Introduction
A two-day workshop teachi ng basi c veri l og for si mul ati on and synthesi s.
About a 50-50 mi x of l ecture and l ab.
Not adequate ful l y to understand someone el ses code.
Adequate to do desi gn wi th the subset taught.
Organization
Take a break anyti me duri ng l ab.
Pl ease, l eave cel l phones OFF duri ng l ecture:
Communi cati on i nhi bi ts l earni ng!
2010-06-24 Essenti al s of Ver i l og Sl i de 2
Schedul e
Day 1 09:00 - 09:30 Lecture
09:30 - 10:00 MiniLab 1 & break
10:00 - 11:00 Lecture
11:00 - 11:10 Break
11:00 - 12:00 Lecture
12:00 - 12:30 Lunch
12:30 - 13:30 Lab 2 & break
13:30 - 14:30 Lecture
14:30 - 14:40 Break
14:40 - 15:30 Lecture
15:30 - 17:30 Lab 3 & break
Day 2 09:00 - 10:00 Lecture
10:00 - 12:00 Lab 4 & break
12:00 - 12:30 Lunch
12:30 - 13:30 Lecture
13:30 - 17:00 Lab 5; Lab revi si ts
17:00 - 17:30 Wrap-up Lecture
2010-06-24 Essenti al s of Ver i l og Sl i de 3
Some Hardware Termi nol ogy
library. A gate-l evel , unconnected col l ecti on of rel ati vel y smal l components.
netlist. A col l ecti on of l i brary components connected accordi ng to a desi gn.
Usual l y l i sted i n an ASCI I fi l e. SPI CE deck; EDI F.
logic. Di gi tal desi gn or HDL functi onal i ty; the structural functi onal i ty of a
netl i st.
sequential logic. Logi c the output of whi ch can not be predi cted from the
current i nput state. Usual l y i s cl ocked. Flip-flop or latch.
combinational logic. Output ful l y determi ned by current i nput. and gate.
hardware description language (HDL). Veri l og HDL or other l anguage
used to defi ne di gi tal functi onal i ty.
register-transfer logic (RTL). Logi c i n an HDL not speci fyi ng i ndi vi dual
netl i st components. ("Regi ster-Transfer Level ")
structural logic. Contrasted wi th RTL; l ogi c usi ng component i nstances
wi red together.
Any desi gn i n an HDL may be si mul ated. RTL veri l og conversi on to a
netl i st usual l y i s done by a software synthesi zer.
Veri l og i s software used to desi gn and i mpl ement di gi tal hardware.
2010-06-24 Essenti al s of Ver i l og Sl i de 4
Some Software Termi nol ogy
requirements. Speci fi cati ons. The project manager's or customer's
prescri pti on of the resul t.
design. A pl an or outl i ne defi ni ng how to meet the requi rements.
implementation. Si mul atabl e code i n HDL ful fi l l i ng the desi gn.
declaration. An i mpl ementati on whi ch reserves a name.
expression. An i mpl ementati on whi ch expresses a val ue.
operator. An i mpl ementati on whi ch defi nes the l ogi c of an expressi on by
operati ng on one or more decl ared objects or l i teral val ues.
statement. An i mpl ementati on whi ch changes somethi ng by assi gni ng the
val ue of an expressi on to i t.
procedural statements. Statements read i n order (procedure) by the
si mul ator. More than one are grouped between begin and end.
concurrent statements. Statements whi ch al l ow the si mul ator to read and
execute them i n any order.
Sequenti al l ogi c i n veri l og usual l y i s i mpl emented usi ng procedural
statements. Combi nati onal l ogi c may be i mpl emented ei ther i n
procedural or concurrent statements.
2010-06-24 Essenti al s of Ver i l og Sl i de 5
The Veri l og Modul e
The module i s the pri mary user-defi ned construct i n veri l og:
• The fundamental uni t of constructi on of any veri l og desi gn.
• The smal l est veri l og construct whi ch can be si mul ated or
synthesi zed.
Decl are the modul e fi rst; then i nstanti ate i t.
The fi rst part of a modul e, up to the fi rst semi col on, i s cal l ed the modul e
We shal l use onl y the modern, verilog-2001 syntax for a modul e header.
2010-06-24 Essenti al s of Ver i l og Sl i de 6
Outl i ne of a Modul e
The modul e el ements whi ch concern us:
module module_name (
output list_of_outputs
, inout list_of_bidirectionals
, input list_of_inputs
);
local variable declarations (reg and wire)
...
concurrent statements:
assign statements (connecti on to wires, onl y)
initial bl ocks (procedural assi gnment to regs)
always bl ocks (procedural assi gnment to regs)
component instances (module or pri mi ti ve i nstances)
...
endmodule
} }} }
2010-06-24 Essenti al s of Ver i l og Sl i de 7
Exampl e of a Modul e
`timescale 1ns/100ps
module ShifterCounter
( output[3:0] CountBus, ShiftBus
, output Overflow
, input Clock, Reset, input[3:0] LoadBus
);
reg[3:0] CountBusReg, ShiftBusReg; // reg's for procedural modification.
reg OverflowReg;
//
assign #2 CountBus = CountBusReg; // Wire the procedural values to output ports.
assign #1 ShiftBus = ShiftBusReg;
assign #1 Overflow = OverflowReg;
//
always@(posedge Clock) // A concurrent block containing procedural statements.
if (Reset==1'b1) // The reset is synchronous to Clock.
begin
CountBusReg <= 4'h0;
end
else begin
CountBusReg <= CountBusReg + 4'h1;
ShiftBusReg <= ShiftBusReg<<1;
end
//
always@(negedge Clock) // Another concurrent block.
if (Reset!=1'b1 && CountBusReg==4'h0)
OverflowReg <= 1'b1;
else OverflowReg <= 1'b0;
//
endmodule
2010-06-24 Essenti al s of Ver i l og Sl i de 8
Lab 1: Mi ni l ab Fl i p-Fl op
Thi s i s a qui ck exerci se to rei nforce the meani ng of a modul e and i ts
contents.
We'l l enter a ti ny desi gn consi sti ng of one fl i p-fl op and simulate i t
usi ng a previ ousl y prepared testbench. One i nstance of the fl i p-fl op
modul e wi l l be i nstanti ated i n the testbench modul e.
We'l l then synthesize the fl i p-fl op usi ng a previ ousl y prepared
synthesi s scri pt.
Thi s i s meant to be our fi rst l ab experi ence i n the materi al presented
on the overal l structure of a veri l og modul e.
2010-06-24 Essenti al s of Ver i l og Sl i de 9
Basi c Veri l og Data Types
I n a modul e, users may decl are vari abl es or assi gn constants.
vari abl es:
reg or integer (procedural ).
wire (nonprocedural ).
constants:
l i teral s (no name).
parameters (named constants; not i n thi s Workshop).
Names are case-sensi ti ve:
May contai n al phanumeri c characters, pl us underscore ('_').
May not begi n wi th a numeral .
2010-06-24 Essenti al s of Ver i l og Sl i de 10
Bi ts and Vectors: Bi ts
A bi t assumes one of four l evel s; '1', '0', 'z', or 'x'.
• '1' means hi gh or true.
• '0' means l ow or false.
• 'z' means di sconnected or turned off (for a three-state gate).
Wi re never i ni ti al i zed.
Loses any contenti on.
• 'x' means ei ther '1' or '0' -- but the si mul ator can't determi ne whi ch.
Procedural val ue never i ni ti al i zed.
Confl i ct among '1' and '0' and 'x'.
Stored i n 1-bi t vari abl es decl ared as reg or wire.
Expressed i n 1-bi t l i teral constants.
One-bi t l i teral s are wri tten 1'b1, 1'b0, 1'bz, or 1'bx.
2010-06-24 Essenti al s of Ver i l og Sl i de 11
Bi ts and Vectors: Vectors
Bi ts may be col l ected i nto a vector.
A vector i s an ordered, one-di mensi onal set of bi ts.
Most-Si gni fi cant Bi t (MSB) of every vector i s on the l eft.
Vector vari abl es have a decl ared wi dth, i ndi cated by an i ndexed range:
reg [left_index : right_index] declared_name(s);
wire [left_index : right_index] declared_name(s);
Vector l i teral wi dth i s speci fi ed when i t i s wri tten:
8'hff == 8'b1111_1111 == 8'd255.
3'h3 == 3'b011 == 3'd3.
An underscore ('_') may be i nserted i n a l i teral for readabi l i ty.
2010-06-24 Essenti al s of Ver i l og Sl i de 12
Bi ts and Vectors: Wi dth Rul es
Vari abl es and l i teral s treated the same way:
• Desti nati on wi dth i n the statement determi nes expressi on-wi dths.
¦ Unsi gned expressi ons wi dened by fi l l wi th '0'.
¦ Si gned expressi ons wi dened by fi l l wi th si gn-bi t val ue.
• Wi dth adjustment occurs before expressi on eval uati on.
• Truncati on or wi deni ng al i gnment i s al ways on the LSB.
Vector exampl es:
reg[7:0] ByteReg1, ByteReg2; // 8-bit reg vectors.
wire[2:0] Wire3bit; // 3-bit wire vector.
reg[0:7] Rbyte; // 8-bit reg vector with MSB in bit 0.
...
ByteReg1 = 6'h9; // result = 8'b0000_1001
ByteReg2 = 12'b1011_0011_0011; // result = 8'h33
Wire3bit = ByteReg1; // result = 3'h1
//
// Wire3bit widened to 8'h1 before summing:
Rbyte = Wire3bit + ByteReg2; // result = 8'h34
2010-06-24 Essenti al s of Ver i l og Sl i de 13
reg Vari abl es
reg: A bi t or vector whi ch may be changed procedural l y duri ng si mul ati on.
Hol ds i ts val ue unti l i t i s assi gned a new val ue i n a subsequent statement.
May represent storage i n a sequenti al gate.
May represent a fi nal combi nati onal val ue.
The procedure, not the reg, determi nes whi ch.
2010-06-24 Essenti al s of Ver i l og Sl i de 14
reg Vari abl e Example
reg Clk, Rst, Q, Z;
reg[1:0] D;
//
always@(posedge Clk, posedge Rst)
begin
if (Rst==1'b1) // In this sequential block,
Q <= 1'b0; // the Q reg stores a value.
else Q <= D[0]; // This block models a flip-flop.
end
//
always@(Clk, D)
begin
if (Clk==1'b1) // In this combinational block,
Z = D[0]; // the Z reg can't store a value.
else Z = D[1]; // This block models a mux.
end
2010-06-24 Essenti al s of Ver i l og Sl i de 15
wire Vari abl es
wi re: A vari abl e whi ch represents connecti vi ty on chi p.
Can not be assi gned a val ue procedural l y.
May be attached to an expressi on or another wire, or a reg.
Attachment by conti nuous assi gnment statement.
Conti nuous assi gnments are the wi ri ng statements of RTL veri l og.
Good desi gn decoupl es l ogi c compl i cati ons from wi ri ng:
Do the compl i cated l ogi c procedural l y. Resul t i n a reg.
Wi re the l ogi c usi ng conti nuous assi gnment. Resul t i n a wire or
output port.
2010-06-24 Essenti al s of Ver i l og Sl i de 16
wire Vari abl e Connecti on
Do the compl i cated l ogi c procedural l y. Resul t i n a reg.
Wi re the l ogi c usi ng conti nuous assi gnment. Resul t i n a wire or
output port.
2010-06-24 Essenti al s of Ver i l og Sl i de 17
wire Vari abl e Example
A compl ete procedural mul ti pl exor (mux) modul e:
module Mux(output Z, input A, B, input[1:0] Sel);
//
reg Q;
// ----------------------
// Continuous assignments are nonprocedural,
// wire-connection statements:
//
assign Z = Q; // Wire the reg Q to port (wire) Z.
// --------------------------
// These blocking assignments are procedural
// and do most of the work:
//
always@(Sel, A, B) // Here is the procedural code.
if (Sel==2'b01)
Q = A;
else Q = B;
//
endmodule
2010-06-24 Essenti al s of Ver i l og Sl i de 18
wire Vari abl e Contention Example
A si mpl e exampl e of contenti on, usi ng conti nuous assi gnments:
module Contender (output Z, input A, B);
assign Z = A;
assign Z = B;
endmodule
The Contender modul e woul d perform these operati ons:
2010-06-24 Essenti al s of Ver i l og Sl i de 19
integer Vari abl es
i nteger: Procedural l y assi gned, l i ke a reg, but:
• Val ue i s stored si gned (2's compl ement).
• Al ways exactl y 32 bi ts wi de, i ncl udi ng si gn bi t (MSB).
Useful i n two contexts:
• Rel ati onal expressi on may i ncl ude a negati ve val ue (esp. -1).
• Operati on represents si gned ari thmeti c.
Veri l og bi nary operators (e. g., '>', '+') al ways do unsi gned
compari sons or ari thmeti c unl ess both operands are si gned types.
2010-06-24 Essenti al s of Ver i l og Sl i de 20
integer Vari abl e Example
integer I;
reg[31:0] R1, R2;
...
R1 = -10; // unsigned = 32'hff..f6; signed = -32'h7f..f6
I = -5; // unsigned = 32'hff..fb; signed = -32'h7f..fb
R2 = 10; // unsigned = 32'h00..0a; signed = +32'h00..0a
...
always @(whatever)
begin
if (I>R1) true_branch;
else false_branch;
//
if (I>R2) true_branch;
else false_branch;
//
if (R1>R2) true_branch;
else false_branch;
end
Unsi gned eval uati on ranks the val ues I>R1>R2; si gned eval uati on ranks
them R2>I>R1. The R's are unsi gned, so al l the true branches wi l l be
executed.
2010-06-24 Essenti al s of Ver i l og Sl i de 21
End Veri l og Vari abl es
Begi n Basi c Veri l og Operators
2010-06-24 Essenti al s of Ver i l og Sl i de 22
Basi c Veri l og Operators
Fi ve mai n ki nds of operator:
Logi cal : Bi nary. Express true as 1'b1 or false as 1'b0.
Unary. (same)
Bi twi se: Bi nary. Express a bi t or vector.
Unary. Express a bi t.
But: inversion i s unary and expresses a vector or a bi t.
Ari thmeti c: Bi nary. Express a bi t or vector.
Rel ati onal : Bi nary. Express true or false as 1'b1 or 1'b0.
Shi ft: Bi nary. Express i ts l eft operand vector, shi fted.
Al so, a uni que Condi ti onal operator:
Tri nary. Sel ects one of two expressi ons, based on true or false
val ue of a thi rd expressi on.
2010-06-24 Essenti al s of Ver i l og Sl i de 23
Logi cal Operators
These operators can express '1', '0', or 'x':
Two bi nary operators: && for l ogi cal and; || for l ogi cal or
One unary operator: ! for l ogi cal i nversi on (negati on; not).
Logical values:
Veri l og 1'b1 means l ogi cal l y true.
Veri l og 1'b0 means l ogi cal l y fal se.
Onl y an al l -0 vector i s i nterpreted as false.
Any operand bi t of val ue 'z' or 'x' means that the operand val ue i s 'x'
and that the expressi on may be 'x'. BUT, by l ogi cal necessi ty:
x && 0 expresses false.
x || 1 expresses true.
2010-06-24 Essenti al s of Ver i l og Sl i de 24
Bi twi se Operators
We shal l study:
& for bi twi se and
| for bi twi se or
~ for bi twi se inversion (unary, onl y)
^ for bi twi se exclusive-or ("xor")
Bi twi se means that vectors are al i gned by LSB and correspondi ng bi ts are
operated upon i ndi vi dual l y. For exampl e,
wire[7:0] A, Z;
wire[4:0] B;
assign A = 8'b0011_1110;
assign B = 8'b0111_1001; // B gets 5'b1_1001.
//
assign #1 Z = A & B; // Z gets 8'b0001_1000.
I nversi on (negati on) i nverts every bi t i n a vector; 'x' or 'z' i s i nverted to 'x'.
2010-06-24 Essenti al s of Ver i l og Sl i de 25
Unary Bi twi se Operators
Unary bi twi se operator: &vector, |vector, ^vector.
• Wri tten i n front of the vector to be reduced.
• Acts l i ke a l ogi c gate wi th the vector bi ts i ts i nputs.
• Reduces the vector to one bi t.
For exampl e,
reg [7:0] Zwide;
reg [1:0] Znarrow;
wire[3:0] A, B, Z;
//
assign #5 Z = &(B[3:1]); // Unary &.
assign #50 A = 4'b1111;
assign #80 B = 4'b0101;
//
always@(A,B) Zwide = B|A; // always@(*) better.
always@(A,B) Znarrow = B&A; // always@(*) better.
At ti me 0, Z = 4'bxxxx; at 5 ns, Z = 4'b000x; at 85 ns, Z = 4'b0000.
2010-06-24 Essenti al s of Ver i l og Sl i de 26
Ari thmeti c Operators
We shal l study:
- for subtraction (al so used to denote a negati ve val ue)
* for multiplication
% for modulo division
Cal cul ati ons are unsi gned unl ess both operands are si gned types.
For exampl e,
wire [5:0] A, Z1, Z2, Z3, Z4;
// ...
assign A = 4'h3; // At 0 ns, A is 6'b00_0011.
assign #1 Z1 = A + 1'b1; // At 1 ns, Z1 -> 6'b00_0100.
assign #2 Z2 = A + 4'h1; // At 2 ns, Z2 -> 6'b00_0100.
assign #3 Z3 = A + 1; // At 3 ns, Z3 -> 6'b00_0100.
assign #10 Z4 = Z3 + 1; // At 13 ns, Z4 -> 6'b00_0101.
I t's best to use onl y l i teral s of the same wi dth as the other operand(s).
assign A = 6'h3, and so forth.
2010-06-24 Essenti al s of Ver i l og Sl i de 27
Rel ati onal Operators
These al l are bi nary. They express true when:
< l eft operand i s less than ri ght operand
> l eft operand i s greater than ri ght operand
== l eft operand i s equal to ri ght operand
!= l eft operand i s not equal to ri ght operand
Otherwi se, they are false or 'x'.
Operands are eval uated as unsi gned unl ess both are si gned types.
2010-06-24 Essenti al s of Ver i l og Sl i de 28
Shi ft Operators
These are bi nary. The ri ght operand gi ves the di stance to be shi fted:
>> shi ft ri ght (down; away from MSB)
<< shi ft l eft (up; toward MSB)
Bi ts shi fted i n al ways are '0'. For exampl e,
reg[15:0] ShiftRegister;
reg[7:0] InByte;
reg InBit;
// ...
always@(posedge Clk, posedge Rst, posedge Barrel)
if (Rst==1'b1)
ShiftRegister <= 'b0; // Omit width to fill with 0.
else if (Barrel==1'b1) // Barrel means shift in a byte.
begin
ShiftRegister <= ShiftRegister<<8;
ShiftRegister[7:0] <= InByte;
end
else begin // Just shift one bit:
ShiftRegister <= ShiftRegister<<1;
ShiftRegister[0] <= InBit;
end
2010-06-24 Essenti al s of Ver i l og Sl i de 29
Condi ti onal Operator
(decision_expression)? true_expression : false_expression
Expresses the true_expression i f the deci si on i s true; otherwi se, the
false_expression. I f the deci si on i s 'x', i t expresses the bi twi se or of the
al ternati ves.
Exampl es:
reg MuxReg;
wire MuxWire;
...
always@(*)
MuxReg = (sel==1'b1)? InBit1 : InBit2; // A procedural mux.
...
assign
MuxWire = (sel==1'b1)? InBit1 : InBit2; // Nonprocedural.
2010-06-24 Essenti al s of Ver i l og Sl i de 30
End Basi c Veri l og Operators
Begi n Regi ster-Transfer Control (RTL)
2010-06-24 Essenti al s of Ver i l og Sl i de 31
Sequenti al RTL
Sequenti al l ogi c usual l y requi res procedural veri l og:
• Successi ve assi gnment statements change reg or integer
vari abl es.
• Assi gnments must be i n an always or initial bl ock.
• Assi gnments depend on control constructs.
Three mai n procedural control statements:
if for rel ati onal or very si mpl e choi ces.
case for enumerated choi ces.
for for ordered successi ons of choi ces.
Any statement under these control s may be a bl ock of statements between
begin and end.
2010-06-24 Essenti al s of Ver i l og Sl i de 32
RTL Procedural Control : if
• Al l ows control by l ogi cal or rel ati onal expressi ons.
• Accepts opti onal else statement.
• Best for two or three mutual l y excl usi ve condi ti ons.
• Makes si mpl e pri ori ty easy to see.
if (expr1) statement1;
else if (expr2) statement2;
else statement3;
2010-06-24 Essenti al s of Ver i l og Sl i de 33
RTL Procedural Control : case
• Al l ows control by numerous speci fi c val ue-matches.
• Al l ows match of 'z' or 'x' as di sti nct bi t-l evel s.
• No control by rel ati onal or l ogi cal expressi on.
• Good for a tabl e l ook-up (decode or encode) or a smal l memory
model .
Uses an expressi on to choose the fi rst matchi ng al ternati ve expressi on;
otherwi se, executes the default statement:
case (expr)
alternative_expr1: statement1;
alternative_expr2: statement2;
... ...
default: default_statement;
endcase // Thi s del i mi ti ng keyword i s requi red.
The veri l og case breaks after one statement; i t does not "fal l through" l i ke
the C l anguage switch.
Never omi t the default of a case statement.
2010-06-24 Essenti al s of Ver i l og Sl i de 34
RTL Procedural Control : for
• Same syntax as C l anguage for l oop.
• Al l control vari abl es shoul d be decl ared before the for.
• Use var=var+n or var=var-n to update a l oop vari abl e.
for (loop var init; loop reentry expression; loop var update)
statement;
For exampl e,
for (i=0; i<=31; i=i+1)
begin
case (DBus[i])
1'bx: DBus[i] = 1'b0;
1'bz: DBus[i] = 1'b0;
default: DBus[i] = DBus[i] ^ Mask[i];
endcase
DBus[i] = 1'b1;
else DBus[i] = 1'b0;
end
2010-06-24 Essenti al s of Ver i l og Sl i de 35
RTL Expressi ons & Statements
Expressions express a val ue:
• Bi t val ue.
• Vector val ue (bi t pattern).
• Numeri cal val ue (of an i nteger).
• Logi cal val ue (true or false).
Expressions may appear:
• On ri ght-hand si de of an assi gnment.
• I n a procedural or concurrent control .
Statements state a change by assi gni ng an expressi on.
• Procedural (bl ocki ng or nonbl ocki ng assi gnment to reg or integer).
• Concurrent (conti nuous assi gnment to wire).
A veri l og pri mi ti ve component may state a change to an output wire, but
thi s i s not RTL.
2010-06-24 Essenti al s of Ver i l og Sl i de 36
Expressi ons & Statements i n RTL Mux
reg Q1, Q2, Zreg1, Zreg2;
wire A, B, C, D, Sel;
...
assign Sel = Q1 ^ Q2;
//
always@(Sel, A, B) // Procedural mux using case statement.
case (Sel)
1'b0: Zreg1 = A;
1'b1: Zreg1 = B;
default: Zreg1 = 1'bx;
endcase
//
always@(Sel, C, D) // Procedural mux using if-else.
if (Sel==1'b0)
Zreg2 = C;
else Zreg2 = D;
exclusive-or val ue -> conti nuous assi gnment statement -> Sel val ue.
Sel val ue -> mux control expressi ons.
A, B, C, D val ues -> mux assi gnment expressi ons.
mux bl ocki ng assi gnment statements -> Zreg val ues.
2010-06-24 Essenti al s of Ver i l og Sl i de 37
Expressi ons & Statements i n RTL Fl i p-Fl op
reg Q1, Q2, Q3, Q4, Zreg1, Zreg2;
wire A, B, Clk, RstN;
...
assign Clk = Q1 ^ Q2;
assign RstN = Q3 & Q4;
always@(posedge Clk, negedge RstN)
begin
case (RstN) // FF with clear, using case statement.
1'b0: Zreg1 <= 1'b0;
default: Zreg1 <= A;
endcase
if (RstN==1'b0) // FF with clear, using if-else statement.
Zreg2 <= 1'b0;
else Zreg2 <= B;
end
exclusive-or val ue -> conti nuous assi gnment statement -> Clk val ue.
bi twi se and val ue -> conti nuous assi gnment statement -> RstN val ue.
RstN val ue -> fl i p-fl i p control expressi ons.
A, B val ues; l i teral constant 1'b0 val ue -> fl i p-fl op assi gnment expressi ons.
fl i p-fl op nonbl ocki ng assi gnment statements -> Zreg val ues.
2010-06-24 Essenti al s of Ver i l og Sl i de 38
RTL Last Statement Wi ns
Maybe the desi gner made a mi stake i n an attempt to model a fl i p-fl op?
always@(posedge Clk, posedge Rst)
begin
if (Rst==1'b1)
Q <= 1'b0;
Q <= D; // "else" omitted.
end
General i ti es: Wi thi n thi s bl ock, because there i s no del ay expressi on,
1. The bl ock i s synthesi zabl e.
2. The nonbl ocki ng statements are executed i n the same order as woul d be
bl ocki ng statements.
3. I f D i s control l ed by an external bl ocki ng assi gnment (combi nati onal
l ogi c), then i ts l atest expressed val ue wi l l be assi gned to Q.
Therefore, whether Rst i s asserted or not, "Q <= D" wi l l be the onl y
statement si mul ated. Thi s fl i p-fl op has no cl ear.
We'l l l ook at the effect of del ays l ater.
2010-06-24 Essenti al s of Ver i l og Sl i de 39
RTL Bl ocki ng Assi gnment
Use bl ocki ng assi gnment statements
• I n a testbench initial bl ock, to sequence del ayed statements.
• I n uncl ocked l ogi c i n an always bl ock.
A bl ocki ng assi gnment bl ocks both readi ng and eval uati on wi thi n i ts
procedural bl ock; thi s i s why i t i s cal l ed a bl ocki ng assi gnment.
After the bl ocki ng assi gnment has been eval uated and si mul ated, the next
By contrast, nonbl ocki ng assi gnments wi th a del ay are si mul ated
concurrentl y and are executed l ast i n any si mul ati on epoch (ti me).
2010-06-24 Essenti al s of Ver i l og Sl i de 40
Bl ocki ng Assi gnments i n a Testbench
Characteristics of a typical verilog testbench module:
• Usual l y no modul e I /O's.
• An i nstanti ati on (uni t) of the top desi gn module to be tested.
• Test-vari abl e decl arati ons to wi re sti mul i to the desi gn uni t.
• Ti mescal e to be propagated to al l modul es of the desi gn uni t.
• Mai n test procedure usual l y i n a si ngl e initial bl ock.
Bl ocki ng assi gnments used, to guarantee orderl y executi on i n
si mul ati on ti me.
• Other concurrent bl ocks may defi ne free-runni ng cl ocks or
suppl ementary test procedures.
2010-06-24 Essenti al s of Ver i l og Sl i de 41
D Fl i p-Fl op Testbench Exampl e
`timescale 1ns/100ps
//
module DFF_Tst; // No I/O in testbench header.
reg D_reg, Clk_reg, Rst_reg;
wire Q_wire;
//
initial
begin
Clk_reg = 1'b0;
Rst_reg = 1'b0; // These two initialized before sim time 0.
#1 D_reg = 1'b1; // Thus, D remains unknown for 1 ns.
#5 Clk_reg = 1'b1; // First clock edge at time 6 ns.
#5 Clk_reg = 1'b0; // time = 11 ns.
#1 Rst_reg = 1'b1; // Clear asserted at time 12.
. . . (statements omitted) . . .
#5 Clk_reg = 1'b1; // time = 46.
#5 Clk_reg = 1'b0;
#20 \$finish; // Simulation ends at time = 71.
end
// The DFF instance under test:
DFF U_1 ( .Q(Q_wire), .D(D_reg), .Clk(Clk_reg), .Rst(Rst_reg) );
//
endmodule // DFF_Tst.
2010-06-24 Essenti al s of Ver i l og Sl i de 42
D Fl i p-Fl op Testbench, Cl ock Di sentangl ed
`timescale 1ns/100ps
//
module DFF_TstNew;
reg D_reg, Clk_reg, Rst_reg;
wire Q_wire;
//
always@(Clk_reg)
#5 Clk_reg <= ~Clk_reg; // Must be NONbl ocki ng!
initial
begin
Clk_reg = 1'b1; // Clock is at any time divisible by 10.
Rst_reg = 1'b0;
#1 D_reg = 1'b1; // D again remains unknown for 1 ns.
#11 Rst_reg = 1'b1; // Clear asserted at time 12 for 5 ns.
#5 Rst_reg = 1'b0; // Clocking can be effective.
#4 D_reg = 1'b1; // Next posedge Clk will schedule Q for 1.
#16 D_reg = 1'b0; // Next posedge Clk will schedule Q for 0.
#20 \$finish; // Simulation ends at time = 57.
end
//
DFF U_1 ( .Q(Q_wire), .D(D_reg), .Clk(Clk_reg), .Rst(Rst_reg) );
endmodule // DFF_TstNew.
2010-06-24 Essenti al s of Ver i l og Sl i de 43
RTL NonBl ocki ng Assi gnment
Two di fferences from bl ocki ng assi gnment:
1. I f there i s a del ay, nonbl ocki ng assi gnments become concurrent.
// BLOCKING:
... at ti me t:
#5 Z[0] = D[0];
#5 Z[1] = D[1];
// Z[1] is assigned at t+10
// NONBLOCKING:
... at ti me t:
#5 Z[0] <= D[0];
#5 Z[1] <= D[1];
// Z[0] and Z[1] are assigned at t+5
2. Whether or not there i s a del ay, nonbl ocki ng assi gnments are executed
after al l others (at a gi ven si mul ati on ti me).
// BLOCKING:
always@(posedge Clk)
#5 Z = D;
always@(posedge Clk)
#5 W = Z;
// Race to assign W.
// NONBLOCKING:
always@(posedge Clk)
#5 Z <= D;
always@(posedge Clk)
#5 W <= Z;
// W will get the old value of Z.
2010-06-24 Essenti al s of Ver i l og Sl i de 44
NonBl ocki ng Assi gnment i n a Fl i p-Fl op
module DFF (output Q, input D, Clk, Rst);
reg Qreg;
//
assign #3 Q = Qreg; // This is a continuous assignment,
// NOT a blocking assignment!
always@(posedge Clk, posedge Rst)
begin
if (Rst == 1'b1)
Qreg <= 1'b0;
else Qreg <= D;
end
endmodule // DFF.
The nonbl ocki ng assi gnments emul ate the i nternal del ay of a cl ocked,
sequenti al devi ce.
2010-06-24 Essenti al s of Ver i l og Sl i de 45
NonBl ocki ng Assi gnment i n a Cl ock Generator
Recal l ,
always@(Clock) #5 Clock <= ~Clock;
• Wi th a bl ocki ng assi gnment, no osci l l ati on.
• Wi th the nonbl ocki ng assi gnment shown, every i nversi on woul d
occur after the always bl ock had been resensi ti zed; therefore,
osci l l ati on woul d occur.
However, any del ayed nonbl ocki ng assi gnment, i ncl udi ng the above, may be
rejected as an error by the synthesi zer.
2010-06-24 Essenti al s of Ver i l og Sl i de 46
RTL Last Statement Wi ns, Agai n
always@(posedge Clk, posedge Rst)
begin
if (Rst==1'b1)
Q <= 1'b0;
Q <= D; // else omitted.
end
As di scussed before, Q al ways gets D,
because "Q <= D" i s l ast.
always@(posedge Clk, posedge Rst)
begin
#1 if (Rst==1'b1)
Q <= 1'b0;
Q <= D;
end
Q al ways gets D, but, after a del ay of
1.
always@(posedge Clk, posedge Rst)
begin
if (Rst==1'b1)
#1 Q <= 1'b0;
Q <= D;
end
Q al ways gets D, but i f Rst was
asserted the l ast ti me D was assi gned,
Q goes to 1'b0 after 1.
always@(posedge Clk, posedge Rst)
begin
if (Rst==1'b1)
#1 Q <= 1'b0;
#1 Q <= D;
end
The del ays make the statements concur r ent.
Q gets D after 1 i f Rst was not asserted; i f Rst
was asser ted, ther e i s a r ace between D and
1'b0, and the resul t i s si mul ator-dependent.
2010-06-24 Essenti al s of Ver i l og Sl i de 47
End Basi c RTL
2010-06-24 Essenti al s of Ver i l og Sl i de 48
Lab 2: Sequenti al Devi ce
Methodol ogy: Al ways have everythi ng worki ng, except for detai l s!
1. module & header --> fi ve always bl ocks --> regs --> seven conti nuous assi gnments.
2. fi x i nputs = sensi ti vi ty l i sts --> add outputs = assi gnment targets.
3. fi ni sh always bl ocks --> testbench fi l e --> fi ni sh desi gn --> compl ete testbench.
2010-06-24 Essenti al s of Ver i l og Sl i de 49
More on Veri l og Operators
2010-06-24 Essenti al s of Ver i l og Sl i de 50
Operator Li st (compl ete)
Symbol Type Symbol Type Symbol Type
~
bi twi se
*
ari thmeti c
>
rel ati onal
&
bi twi se
/
ari thmeti c
<
rel ati onal
~&
reducti on
+
ari thmeti c
>=
rel ati onal
|
bi twi se
-
ari thmeti c
<=
rel ati onal
~|
reducti on
%
ari thmeti c
==
equal i ty
^
bi twi se
**
ari thmeti c
!=
equal i ty
~^,^~
reducti on
!
l ogi cal
===
equal i ty (case)
>>
shi ft
&&
l ogi cal
!==
equal i ty (case)
<<
shi ft
||
l ogi cal
? :
condi ti onal
>>>
shi ft (ari th)
{ }
concatenati on
>>>
shi ft (ari th) { n{ } } repl i cati on
Any bi twi se operator except ~ al so i s a reducti on operator. Al l reducti on
operators are unary.
Equal i ty operators are a ki nd of rel ati onal operator.
Operators i n col or are i gnored i n thi s Workshop.
2010-06-24 Essenti al s of Ver i l og Sl i de 51
Operator Precedence Tabl e
Precedence Operator
l owest = 0 ? : (condi ti onal )
1
||
2
&&
3
| ~|
4
^ ~^ ^~
5
& ~&
6
== != === !===
7
< <= > >=
8
<< >> <<< >>>
9 + - (bi nary)
10
* / %
11
**
hi ghest = 12 + - ! ~ (unary)
Al l operators except the condi ti onal operator associ ate l eft to ri ght when of
equal precedence.
2010-06-24 Essenti al s of Ver i l og Sl i de 52
The Concatenate Operator
Concatenate: { ..., ..., ... }
• Creates a temporary vector as wi de as the sum of i ts operand
wi dths.
• Al l ows any number of operands.
• Every operand must have an expl i ci t wi dth.
• The resul t i s al i gned on the LSB (as usual ) and truncated or zero-
extended to fi l l the desti nati on.
For exampl e,
wire[11:0] Z;
wire[5:0] W;
reg[3:0] A, B;
...
initial
begin
A = 4'h5; // 4'b0101
B = 4'h7; // 4'b0111
end
assign #1 Z = {3'b111, A, B}; // Z gets 12'b0111_0101_0111;
assign #2 W = {A,B}; // W gets 6'b01_0111
2010-06-24 Essenti al s of Ver i l og Sl i de 53
End Veri l og Operators
Begi n Si mul ati on Control (Sensi ti vi ty)
2010-06-24 Essenti al s of Ver i l og Sl i de 54
Sensi ti vi ty Li sts
An expressi on i s eval uated after the si mul ator reads i t i n a concurrent
statement.
Readi ng i s tri ggered by the sensi ti vi ty l i st whi ch makes the concurrent
statement sensi ti ve to change.
A "change" i s a change i n any bi t,
to '0' from anythi ng el se (= fal l i ng edge = negedge)
to '1' from anythi ng el se (= ri si ng edge = posedge).
We shal l study four ki nds of concurrent statement:
• always bl ock
• initial bl ock
• conti nuous assi gnment
• pri mi ti ve i nstanti ati on
2010-06-24 Essenti al s of Ver i l og Sl i de 55
always Bl ock Sensi ti vi ty
An always contai ns a procedural bl ock:
Can assi gn to reg or integer; not wire.
Used for anythi ng compl i cated i n the desi gn.
Al ways sensi ti ve, but usual l y under event control :
• change control .
• edge control .
The always means that the si mul ator wi l l try to read the bl ock just before
ti me 0 and always after every si mul ated event.
An event control wi l l prevent readi ng unl ess the si mul ated event i s l i sted.
The bl ock i s not synthesi zabl e i f change and edge control s are mi xed.
2010-06-24 Essenti al s of Ver i l og Sl i de 56
always Bl ock Change Control
A change control prevents readi ng of an always bl ock unti l any change i n
the l i st occurs.
Exampl e,
always @(A, B, C)
begin
(statements)
end
The event control i s "@(A, B, C)".
After ti me 0, the bl ock i s not read agai n unl ess A, B, or C changes.
2010-06-24 Essenti al s of Ver i l og Sl i de 57
always Bl ock Edge Control
An edge control prevents readi ng of an always bl ock unti l the speci fi ed
edge occurs.
Exampl e,
always @(posedge Clk, negedge ClrN)
begin
(statements)
end
The event control i s "@(posedge Clk, negedge ClrN)".
The bl ock i s not read unl ess a posi ti ve edge (change to '1') occurred on the
Clk vari abl e, or a negati ve edge (change to '0') occurred on the ClrN vari abl e.
2010-06-24 Essenti al s of Ver i l og Sl i de 58
initial Bl ock Sensi ti vi ty
An initial contai ns a procedural bl ock:
Can assi gn to reg or integer; not wire.
Used for anythi ng compl i cated i n the testbench.
Shoul d be avoi ded i n desi gn modul es.
No expl i ci t sensi ti vi ty l i st; i s read onl y once, begi nni ng just before si mul ati on
ti me 0.
For exampl e,
initial
begin
Clk = 1'b0; // Clk set to '0' before time 0.
#0 Rst = 1'b0; // Rst changes to '0' at time 0.
#1 D = 1'b1; // D changes to '1' at time 1.
(other statements)
\$finish; // Terminate the simulation.
end
2010-06-24 Essenti al s of Ver i l og Sl i de 59
Conti nuous Assi gnment (assign) Sensi ti vi ty
Thi s i s a si mpl e, nonprocedural statement:
Can assi gn onl y to a wire, not reg or integer.
Contai ns one statement.
Sensi ti vi ty l i st i s any expressi on on the ri ght-hand si de of the statement.
I ntroduced wi th the keyword assign.
Exampl es:
module ModuleName(output W, ...);
...
assign W = a & b | c; // W is a port = a net type (wire).
endmodule
wire[31:0] X;
integer A, B;
...
// Put the greater of A or B into X; A if they are equal:
assign #2 X = (A>=B)? A : B;
2010-06-24 Essenti al s of Ver i l og Sl i de 60
Pri mi ti ve I nstanti ati on Sensi ti vi ty
Pri mi ti ve component (gate) i nstances are nonprocedural statements:
Predefi ned i n veri l og.
Desi gner deci des where to i nstanti ate, and how to connect them.
Perform el ementary combi nati onal l ogi cal functi ons.
Outputs on l eft; i nputs on ri ght.
Sensitive to any change on an i nput.
Exampl e of xor pri mi ti ve:
wire D, A, B;
reg C;
...
xor xor01(D, A, B, C); // Same as assign D = A ^ B ^ C;
We'l l study these pri mi ti ve components l ater.
2010-06-24 Essenti al s of Ver i l og Sl i de 61
End Si mul ati on Control and Sensi ti vi ty
Begi n Latch I nference and Synthesi s I ssues
2010-06-24 Essenti al s of Ver i l og Sl i de 62
Latch I nference
A l atched state occurs when a vari abl e control l ed by a change-sensi ti ve
always bl ock i s not sensi ti ve to some speci fi c i nput change:
• I ncompl ete sensi ti vi ty l i st.
• Omi tted control construct condi ti on.
A l atch becomes combi nati onal when there i s no i nsensi ti vi ty.
always@(A, B)
begin
Za = A & B & C;
Zb = A | B | C;
end
Za and Zb l atched by omi ssi on of C.
always@(A,B,C) woul d make
them combi nati onal .
always@(A, B)
begin
if (A == 1'b1)
Z = A & B;
end
Z l atched by omi ssi on of control
state (A != 1'b1).
else Z = A | B woul d make Z
combi nati onal .
2010-06-24 Essenti al s of Ver i l og Sl i de 63
Avoi d Synthesi s of Latches
The synthesi zer i s bi ased agai nst l atch i nference for techni cal reasons.
• Refuses a sensi ti vi ty l i st wi th mi xed edge and change event
control s.
• Refuses top-l evel compl i cated control s: One if or case.
• Assumes that compl i cated i nferred l atched states are errors; may
produce a combi nati onal netl i st anyway.
NEVER OMIT A VARIABLE FROM A CHANGE-
SENSITIVE EVENT CONTROL!
NEVER TRY TO IMPLEMENT A COMPLICATED
LATCH PROCEDURALLY!
2010-06-24 Essenti al s of Ver i l og Sl i de 64
A Good Transparent Latch Model
A si mpl e transparent l atch can be model l ed correctl y thi s way:
always@(a,sel)
if (sel==1'b1)
z = a;
Thi s l atch can be synthesi zed wi thout ri sk or ambi gui ty.
2010-06-24 Essenti al s of Ver i l og Sl i de 65
Latches and Muxes
Latch i nference and mux i nference are cl osel y rel ated:
For exampl e, suppose we have decl arati ons i n a modul e of
wire a, b, sel;
reg z;
always@(a, b, sel)
if (sel==1'b1)
z = a;
else z = b;
always@(*)
if (sel==1'b1)
z = a;
else z = b;
always@(sel)
if (sel==1'b1)
z = a;
else z = b;
always@(a, b)
if (sel==1'b1)
z = a;
else z = b;
good mux better mux strange l atch strange l atch
2010-06-24 Essenti al s of Ver i l og Sl i de 66
Latchi ng By Mi stake
One reason why the synthesi zer avoi ds l atches i s human error.
Here i s a nonstandard l atch whi ch contai ns no procedural control construct;
but, b i s omi tted from the sensi ti vi ty l i st:
always@(a,v)
Z = a | b;
Thi s i s the ki nd of l atch often created by a typo.
The verilog-2001 standard i ntroduced always@(*) to prevent thi s ki nd of
error.
2010-06-24 Essenti al s of Ver i l og Sl i de 67
End Synthesi s I ssues
Lab 3 I ntroducti on
End Day 1
2010-06-24 Essenti al s of Ver i l og Sl i de 68
Lab 3: ALU Schemati c
The desi gn wi l l be a datapath uni t named ALU.
The schemati c for thi s devi ce:
2010-06-24 Essenti al s of Ver i l og Sl i de 69
Lab 3: ALU Functi on Tabl e
Operation Sel Z[63:32] Z[31:0] Ov
Off 0 32'bz 32'bz 1'bz
A + B (unsigned) 1
{31'b0,carry
bit}
A + B
carry
A + B (signed) 2
32'b(sign bit)
A + B
sign
A and B
3 A & B A & B Z[0]
A or B
4 A | B A | B Z[0]
A x B (unsigned)
5
(A*B)[63:32] (A*B)[31:0]
Z[64]
concatenate
6 B A B[0]
concat. reversed
7 B reversed A reversed B[31]
The si gned addi ti on shoul d assume 30-bi t operand si gni fi cance, onl y.
Here, reversed means reversed i n bi t-order. For exampl e, 4'b0011 reversed
becomes 4'b1100.
2010-06-24 Essenti al s of Ver i l og Sl i de 70
Day 2
Del ays and Synchroni zati on
2010-06-24 Essenti al s of Ver i l og Sl i de 71
Whence That Del ay?
RTL veri l og del ays ("#n") are fi cti ti ous:
• Desi gner makes esti mates . . . and hopes.
• Onl y RTL cl ock peri od and phase i s real i sti c.
Chi p del ays come from the netl i st:
• Gate propagati on del ays.
}
Logi cal
netl i st
• Wi re capaci ti ve del ays.
• Speed of l i ght i n copper.
etc.
}
Physi cal
(l ayed-out)
netl i st
There i s no reason to associ ate a del ay wi th each veri l og RTL statement i n
the desi gn!
2010-06-24 Essenti al s of Ver i l og Sl i de 72
Bl ocki ng and Nonbl ocki ng Statements
Never mi x them i n a si ngl e desi gn bl ock:
Ti mi ng compl exi ty.
Possi bl e race condi ti ons.
Netl i st ti mi ng wi l l i gnore the mi xture.
Synthesi zer wi l l reject any mi xture.
...
begin
Z1 <= A && B;
#1 Z2 = C && D;
#1 Z1 <= Z2 | E;
Z1 = 1'b0;
end
Don't even
2010-06-24 Essenti al s of Ver i l og Sl i de 73
Undel ayed Bl ocki ng and Nonbl ocki ng Statements
Sequences of both ki nds work i nternal l y about the same way:
• Executed i n the order i n whi ch the statements are read, top to bottom.
• Last one wi ns, for mul ti pl e, successi ve, i ndependent assi gnments to the
same vari abl e.
They work di fferentl y for an external concurrent bl ock. At any si mul ati on
ti me, bl ocki ng assi gnments are updated fi rst, over the whol e si mul ati on:
• Same ti me as pri mi ti ve component updates and conti nuous
assi gnments.
• Compl eted before any nonbl ocki ng assi gnment.
Therefore, to si mul ate and synthesi ze proper setup:
Use bl ocki ng statements for uncl ocked l ogi c.
Use nonbl ocki ng statements for cl ocked l ogi c.
Al so:
Use bl ocki ng statements for any l ogi c dependi ng on i ntermedi ate updates.
2010-06-24 Essenti al s of Ver i l og Sl i de 74
Exampl e of Undel ayed Statements
// Delayed statements on top, where they can be found easily:
//
assign #2 OutPort = OutPortReg ^ InnerWire;
// #2 is collected skew and sequential delays.
assign #5 InnerWire = InnerReg | OtherInnerReg;
// #5 is collected combinational delays.
//
always@(*)
begin
temp1 = Ain^Bin;
temp2 = Cin^Din;
InnerReg = (temp1 & temp2) | Ain^Din;
end
//
// Clocked logic:
//
always@(posedge Clock, posedge Reset)
begin
if (Reset==1'b1)
OutPortReg <= 'b0;
else OutPortReg <= InnerReg; // Current value sampled.
end
2010-06-24 Essenti al s of Ver i l og Sl i de 75
Effect of Cl ocki ng by Nonbl ocki ng Assi gnment
Suppose thi s, cl ocked at some si mul ati on ti me t:
always@(posedge Clk)
J <= A;
always@(posedge Clk)
K = B;
always@(posedge Clk)
X = J;
always@(posedge Clk)
Y = K;
always@(posedge Clk)
Z <= X;
X i s wel l -defi ned, because J i s updated l ate.
Y and Z are i n race condi ti ons.
2010-06-24 Essenti al s of Ver i l og Sl i de 76
Del ayed Bl ocki ng and Nonbl ocki ng Statements
Del ayed bl ocki ng statements are executed i n order, but del ayed. Del ayed
nonbl ocki ng statements are read al l at once and executed i n order of del ay
ti me (schedul ed concurrentl y).
For exampl e, here are the same assi gnments and del ays:
always@(*)
begin
Areg = 3'b110;
Breg = 3'b001;
Creg = 3'b100;
#3 Areg = Breg | Creg;
#2 Breg = &Creg;
#1 Creg = Areg | Breg;
end
always@(posedge Clk)
begin
Areg <= 3'b110;
Breg <= 3'b001;
Creg <= 3'b100;
#3 Areg <= Breg | Creg;
#2 Breg <= &Creg;
#1 Creg <= Areg | Breg;
end
2010-06-24 Essenti al s of Ver i l og Sl i de 77
Cl ocks and Asynchronous Control s
Cl ocked bl ock:
• always bl ock.
• Edge-sensi ti ve event control (s), onl y (synthesi s requi rement).
• No change sensi ti vi ty (synthesi s requi rement).
• No more than one cl ock per bl ock (synthesi s requi rement).
• Mul ti pl e edge sensi ti vi ti es i mpl y asynchronous control s.
For exampl e,
always@(posedge A) ... // A is a clock.
always@(negedge A) ... // A is a clock.
always@(posedge A, negedge B) ... // One of A and B may clock.
Not synthesi zabl e:
always@(posedge clk, clear, preset) ...
always@(clear, posedge clk) ...
reg[1:0] ClkBus;
always@(posedge ClkBus) ...
2010-06-24 Essenti al s of Ver i l og Sl i de 78
Cl ock I nference
Cl ocked bl ock wi th asynchronous control (s):
• always bl ock wi th at l east two edges.
• Cl ock i s i nferred i nsi de the bl ock by i ts l ower pri ori ty.
• Other edges are asynchronous control s.
Exampl e:
always@(posedge Clk, posedge Clear)
if (Clear==1'b1)
Q <= 1'b0;
else Q <= D;
I f Clear i s asserted, i t takes pri ori ty; therefore, Clk must be the cl ock and
Clear the asynchronous control .
2010-06-24 Essenti al s of Ver i l og Sl i de 79
Asynchronous Control Pri ori ty
Asynchronous control (s):
• Cl ock i s i nferred i nsi de the bl ock; has l owest pri ori ty.
• Asynchronous control s cannot avoi d bei ng pri ori ti zed (procedural code).
• Li brary may i ncl ude a component wi th mul ti pl e asynchronous control s.
• Synthesi zer wi l l i gnore veri l og pri ori ty (probabl y doesn't matter).
For exampl e,
always@( posedge Clk
, negedge Preset_n
, negedge Clear_n
)
if (Preset_n==1'b0)
Q <= 1'b1;
else if (Clear_n==1'b0)
Q <= 1'b0;
else Q <= D;
}
I f Pre and Clr are asser ted at once,
thi s synthesi zed component may
cl ear:
Avoi d more than one asynchronous control per bl ock, i f possi bl e.
2010-06-24 Essenti al s of Ver i l og Sl i de 80
End Del ays and Synchroni zati on
Begi n Structural Desi gn and Wi ri ng Del ays
2010-06-24 Essenti al s of Ver i l og Sl i de 81
Structural Desi gn
Structural desi gn content:
• No operator; no procedural code.
• No reg bi t or vector.
• Yes: wires or busses of them.
• Yes: component instances.
The I /O's i n a module header are that modul e's ports.
Structural desi gn process:
• I nstanti ate components and decl are wires.
• Connect wi res to i nstances of user-defi ned modul es.
• Connect wi res to i nstances of veri l og pri mi ti ve components.
• Connecti on i s cal l ed port mappi ng.
2010-06-24 Essenti al s of Ver i l og Sl i de 82
Structural Desi gn Port Mappi ng
Structural desi gn may al l ow conti nuous assi gnment statements:
• To assi gn a wi re i n a modul e to that modul e's output port.
• To rename a wi re by assi gni ng one wi re to another.
• No expressi on operator al l owed.
A port map may i ncl ude parameter overri des as wel l as wi ri ng. See
referenced textbooks.
There are two ways to port-map to an i nstance:
• By port name.
• By port posi ti on.
2010-06-24 Essenti al s of Ver i l og Sl i de 83
Port Mappi ng by Name
Port mappi ng by name i s the recommended way:
• Li st port names wi th dot and parentheses.
• Put mapped expressi on i n parentheses.
Expressi on must be a si mpl e name for structural desi gn.
wire or reg name, or l i teral constant, for input ports.
wire name for output or inout ports.
Exampl e from our l abs:
ALU U1 ( .Z(ZWatch), .Ov(OvWatch)
, .A(AStim), .B(BStim), .Sel(SelCount)
);
Mappi ng by name doesn't work for veri l og pri mi ti ves.
2010-06-24 Essenti al s of Ver i l og Sl i de 84
Port Mappi ng by Posi ti on
Port mappi ng by posi ti on:
• You must know exact order i n whi ch ports were decl ared i n module.
• Li st port-mapped expressi ons i n modul e-decl arati on order.
¦ Expressi on must be a si mpl e name for structural desi gn.
¦ wire or reg name, or l i teral constant, for input ports.
¦ wire name for output or inout ports.
Port mapping by position is error-prone, difficult to maintain
properly, and should be avoided.
Excepti on: veri l og pri mi ti ve predecl ared ports:
• Al ways output port on l eft.
• Al ways input port(s) on ri ght.
Our ALU modul e i nstance, mapped by posi ti on:
ALU U1 ( ZWatch, OvWatch, AStim, BStim, SelCount );
2010-06-24 Essenti al s of Ver i l og Sl i de 85
Veri l og Pri mi ti ve Gates
Veri l og pri mi ti ve components are bui l t i nto the l anguage:
• I ncl ude l ogi c gates, buffer gates, swi tch-l evel components.
• No port name; i nstance name i s opti onal .
• No veri l og pri mi ti ve for sequenti al l ogi c.
The most common ones:
Logic Gates Buffer Gates
and buf
nand not
or bufif1
nor bufif0
xor notif1
xnor notif0
An i nstanti ati on:
wire A, B, C, Z;
nand (Z, A, B, C); // Z gets !(A && B && C).
2010-06-24 Essenti al s of Ver i l og Sl i de 86
Veri l og Logi c Gate Exampl es
Pri mi ti ve l ogi c gates:
• Have mul ti pl e i nputs.
• Are equi val ent to conti nuous assi gnment statements.
Exampl es:
wire A, B, C, D, E;
wire[31:0] Bus;
reg Areg, Breg;
...
and (E, A, C, D); // Same as assign E = A && C && D;
and #2 (B, A, C); // Same as assign #2 B = A && C;
xnor XN_001 (C, A, Bus[12], Breg); // C gets !(A^Bus[12]^Breg).
nor N_001(Areg, Breg, C); // ILLEGAL!
Note:
I n the xnor, i t i s fi ne to name a reg (Breg) as an i nput, i n RTL desi gn.
The nor i s i l l egal because onl y a wire, not a reg, may be mapped to an
output, even i n a mostl y-RTL desi gn.
2010-06-24 Essenti al s of Ver i l og Sl i de 87
Veri l og Buffer Gate Exampl es
Pri mi ti ve buffer gates:
• Are used to tune netl i st dri ve strength, or to turn off dri ve ('z').
• Except buf and not, have one output and two i nputs.
• Except these, fi rst i nput i s data; second i nput i s 'z' control .
• Are equi val ent to conti nuous assi gnment statements.
Exampl es:
wire A, B, C, D, E;
wire[31:0] Bus;
...
not Not01 (E, A); // Same as assign E = !A;
buf #2 (B, A); // Same as assign #2 B = A;
bufif1 Buf1(C,Bus[2],A); // assign C = (A==1'b1)? Bus[2]:1'bz;
notif1 N_001(A,B,C); // assign A = (C==1'b1)? ~B : 1'bz;
notif0 N_002(D,B,C); // assign D = (C==1'b0)? ~B : 1'bz;
Note: Nami ng conventi on i s that when the "if" i s true ("bufif1"), the
control i s asserted and the dri ver i s on.
2010-06-24 Essenti al s of Ver i l og Sl i de 88
Mul ti val ue Del ays
Veri l og al l ows si mul ati on of a wire del ay wi th speci fi ed mul ti pl e val ues:
• Di fferent ri se and fal l ti mes.
• Di fferent ti me to 'z' l evel .
Exampl es:
assign #(3, 5) OutWire_001 = newvalue;
bufif1 #(3, 5, 7)
GateInst_001(OutWire_002, InWire_002, Control_002);
The OutWire_001 del ay from anythi ng to '1' wi l l be 3 ti me uni ts; from
anythi ng to '0' wi l l be 5.
The OutWire_002 del ays to '1' or '0' wi l l be the same as for OutWire_001;
when OutWire_002 goes to 'z', the del ay wi l l be 7.
2010-06-24 Essenti al s of Ver i l og Sl i de 89
Si mul ati on of wire Del ays
A change on a wire may be assi gned one, two, or three del ay val ues:
#(every_del ay)
Si mul ator uses thi s for al l schedul i ng.
#(ri se, fal l )
Si mul ator uses rise del ay to schedul e changes to '1'.
Si mul ator uses fall del ay to schedul e changes to '0'.
#(ri se, fal l , to_z)
Si mul ator uses rise del ay and fall del ay as for 2 val ues.
Si mul ator uses to_z del ay to schedul e changes to 'z'.
Del ays to 'x' use the shortest del ay i n a mul ti val ue expressi on; to 'z' i s the
same, except when a 3-val ue del ay i s speci fi ed.
Mul ti val ue del ay expressi ons are al l owed for wire types:
• Conti nuous assi gnment statements.
• Pri mi ti ve component i nstanti ati ons.
A procedural assi gnment can have onl y one del ay val ue and, of course, can't
assi gn to a wi re.
2010-06-24 Essenti al s of Ver i l og Sl i de 90
Ti mi ng Tri pl ets
Ti mi ng Tri pl et:
• Three val ues, col on-separated.
• Represent technol ogy-rel ated minimum:typical:maximum del ay
condi ti ons.
• Usual l y found i n back-annotated netl i sts -- rarel y i n RTL.
• Al l owed anywhere a del ay val ue i s al l owed.
For exampl e,
assign #3 Sum1 = A ^ B; // Plain delay expression.
assign #(2:3:5) Sum2 = A ^ B; // Timing triplet.
assign #(2:3:5, 1:3:6) Sum3 = A ^ B; // Multivalue triplet.
//
always@(posedge Clk)
begin
#5 Reg1 <= A & B; // Plain delay.
#(5,6) Reg2 <= A | C; // I LLEGAL! Multivalue only for wires!
#(4:5:6) Reg3 <= B%4; // Plain delay replaced by triplet.
end
2010-06-24 Essenti al s of Ver i l og Sl i de 91
End Del ays
Shi ft Regi sters
I ntroducti on to Lab 4
2010-06-24 Essenti al s of Ver i l og Sl i de 92
Shi ft Regi sters
A regi ster of bi ts:
• Shi ft l eft = shi ft up = shi ft toward MSB.
• Shi ft ri ght = shi ft down = shi ft toward LSB.
• Usual l y, the shi ft i s one bi t-posi ti on per cl ock.
• Barrel shi fter can shi ft n bi t posi ti ons i n one or two cl ocks.
Exampl e of shi fted regi ster:
2010-06-24 Essenti al s of Ver i l og Sl i de 93
Veri l og Shi fti ng
Two di fferent ways:
• Use veri l og shi ft operator:
reg[7:0] ShReg1, ShReg2;
...
ShReg1 <= 8'b0011_0010;
ShReg1 <= ShReg1<<1; // ShReg1 now holds 8'b0110_0100.
• Mani pul ate bi ts i ndi vi dual l y:
...
ShReg2 <= 8'b0011_0010;
begin
ShReg2[7] <= ShReg2[6];
ShReg2[6] <= ShReg2[5];
ShReg2[5] <= ShReg2[4];
ShReg2[4] <= ShReg2[3];
ShReg2[3] <= ShReg2[2];
ShReg2[2] <= ShReg2[1];
ShReg2[1] <= ShReg2[0];
ShReg2[0] <= 1'b0;
end // ShReg2 now holds 8'b0110_0100.
2010-06-24 Essenti al s of Ver i l og Sl i de 94
Shi ft Regi ster Schemati c
Fi ve-bi t shi ft regi ster wi th cl ear and seri al l oad.
Shi fts from l eft to ri ght i n the schemati c.
Does a veri l og l eft shi ft, assumi ng:
• The fl i p-fl op Q outputs r epresent the r egi ster val ue.
• Schemati c bi t 4 i s the MSB.
We shal l i mpl ement thi s shi ft regi ster i n veri l og, i n several vari ati ons, i n our next l ab.
2010-06-24 Essenti al s of Ver i l og Sl i de 95
Lab 4: Structural and RTL Shi ft Regi sters
Thi s l ab wi l l be focussed on the use of del ays and nonbl ocki ng assi gnments.
We'l l use a structural model to devel op a veri l og testbench.
We'l l reuse the testbench i n many vari ati ons.
Two different kinds of shift register model:
• One structural shi ft regi ster:
Based on a fl i p-fl op model and a mux model .
• Many RTL shi ft regi ster vari ati ons:
Vari ous nonbl ocki ng and bl ocki ng assi gnments.
Vari ous del ays.
2010-06-24 Essenti al s of Ver i l og Sl i de 96
Lab 4: Structural Shi ft Regi ster
1. Model a fl i p-fl op wi th cl ear,
and a 2-i nput mux:
2. Outl i ne the shi ft regi ster and testbench.
3. I nstanti ate the outl i ne shi ft regi ster.
4. Compl ete the testbench and the desi gn:
2010-06-24 Essenti al s of Ver i l og Sl i de 97
Lab 4: RTL Shi ft Regi ster
Many RTL model s:
1. Copy your structural fi l es; omi t the fl i p-fl op and mux model .
3. I mpl ement the shi ft regi ster wi th veri l og "<<" and nonbl ocki ng
assi gnments.
always@(posedge ClkIn, posedge ClrIn)
if (ClrIn==1'b1)
ShiftReg <= 'b0;
else begin
ShiftReg <= (ShiftEna==1'b1)? ShiftReg<<1 : ShiftReg;
ShiftReg[0] <= (ShiftEna==1'b1)? Din : ShiftReg[0];
end
4. Rei mpl ement the shi ft regi ster i n several di fferent ways.
2010-06-24 Essenti al s of Ver i l og Sl i de 98
Veri l og Comments, Stri ngs, and
Messages
2010-06-24 Essenti al s of Ver i l og Sl i de 99
Two di fferent comment formats (same as for C++):
• Li ne comment: "//" whi ch starts anywhere on a l i ne.
• Bl ock comment:
"/*" begi ns a comment whi ch doesn't end unti l "*/".
Al so may di sabl e compi l ati on wi th a compi l er di recti ve:
`ifdef COMMENTED_OUT
(stuff)
`endif
≅ ≅≅ ≅
/*
(stuff)
*/
The compi l er won't read anythi ng between `ifdef and `endif unl ess
COMMENTED_OUT i s defi ned.
2010-06-24 Essenti al s of Ver i l og Sl i de 100
Compi l er Di recti ves (Macroes)
Use `define and other macro di recti ves spari ngl y:
• They are gl obal -- no fi l e boundary.
• They don't depend on desi gn structure, just compi l ati on order.
• Other desi gners may pi ck same name.
Use `undef at end of fi l e.
Excepti on: `timescale.
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`define Compi l er Di recti ve Exampl e
`define BLOCKING
...
always@(posedge Clk)
begin
`ifdef BLOCKING
#3 Q1 = D1;
#2 Q2 = D2;
`else
#3 Q1 <= D1;
#2 Q2 <= D2;
`endif
end
...
`undef BLOCKING
2010-06-24 Essenti al s of Ver i l og Sl i de 102
Ti mescal e Compi l er Di recti ve
Syntax: `timescale n u
n
/ m u
m
• n i s an i nteger uni t of del ay ti me duri ng si mul ati on.
• u
n
i s the uni t of measurement used to express n.
• m i s the maxi mum resol uti on of ti me al l owed to the si mul ator.
• u
m
i s the uni t of measurement used to express m.
• Spaces between the tokens are opti onal .
Val ue of n determi nes how del ays are scal ed.
Must have nu
n
≥ ≥≥ ≥ mu
m
.
Must have n and m equal to 1, 10, or 100.
Exampl e,
`timescale 1ns/10ps
...
#0.05 X = Y & Z; // The delay is 50 ps.
2010-06-24 Essenti al s of Ver i l og Sl i de 103
Veri l og Si mul ator Stri ngs
Veri l og stri ngs:
• ASCI I character stri ngs i n quotes.
• Rarel y, stored i n a reg vector.
• More frequentl y, l i teral constants to be pri nted by messagi ng system
Exampl e:
\$display("\nThis is a verilog string.\n");
The "\n" escape sequences are NL (newl i ne) symbol s.
<-- bl ank l i ne.
The resul t:
This is a verilog string.
<-- bl ank l i ne.
2010-06-24 Essenti al s of Ver i l og Sl i de 104
Veri l og Messagi ng System Tasks
• Procedural .
• Pri nt to si mul ator consol e wi ndow or di sc fi l e.
• Syntax i s based on C l anguage printf functi ons.
Two very useful ones:
• \$display(format, args_for_display) for a pri ntout before nonbl ocki ng
assi gnment.
• \$strobe(format, args_for_display) for a pri ntout after nonbl ocki ng
assi gnment.
A si mpl e, homemade asserti on statement usi ng \$time:
if (X!=Y)
\$strobe("***Time=%04d. X=%1b == Y=%1b failed.", \$time,X,Y);
At si mul ati on ti me 331, "***Time=0331. X=1 == Y=0 failed."
2010-06-24 Essenti al s of Ver i l og Sl i de 105
Veri l og Message Format Speci fi ers
\$display(format, args_for_display):
• The format refers to the stri ng to be pri nted. I t may contai n tokens
whi ch speci fy where arg val ues are to be substi tuted.
• The args_for_di spl ay refers to an argument l i st of l i teral s or
vari abl es.
The most common format speci fi ers are these:
%h pri nt arg as hex i nteger
%d pri nt arg as deci mal i nteger
%b pri nt arg as bi nary i nteger
%s pri nt arg as character stri ng
%m pri nt modul e i nstance name here
2010-06-24 Essenti al s of Ver i l og Sl i de 106
Numeri cal Format Wi dth Speci fi ers
Precede a %h, %d, %b, etc. numeri cal speci fi er wi th "n" for the mi ni mum
number of pl aces.
Use "0n" to fi l l unused l eadi ng pl aces wi th zeroes.
For exampl e,
integer x;
...
x = 5;
\$display("%s = [%04b] = [%4b].", "The value", x, x);
Here, n = 4. Thi s pri nts, "The value = [0101] = [ 101].".
Otherwi se, usi ng "%b" wi th no n, the i nteger woul d be pri nted wi th a defaul t
of 29 l eadi ng bl anks, because i ntegers are 32 bi ts wi de.
2010-06-24 Essenti al s of Ver i l og Sl i de 107
End Comments, Stri ngs, and Messages
Begi n Vectors and Arrays
2010-06-24 Essenti al s of Ver i l og Sl i de 108
Vectors Agai n
Veri l og vector:
• An ordered set of bi ts.
User-decl ared: reg or wire.
Predecl ared: integer.
• Represents the val ue on a hardware bus.
Vector assi gnment:
• enti re vector.
• bi t-sel ect.
• part-sel ect.
2010-06-24 Essenti al s of Ver i l og Sl i de 109
Vector Sel ects
bi t-sel ect: i ndexed expressi on referenci ng just one bi t i n a vector.
OutBit1 = InBus[2]; // Bit 2 only.
part-sel ect: i ndex-ranged constant expressi on referenci ng one or more bi ts.
A 1-bi t part-sel ect and a fi ve-bi t part-sel ect:
OutBit1 = InBus[3:3]; // Bit 3 only.
OutBusA = InBus[6:2]; // Bits 6..2.
A sel ect may appear on the l eft-hand si de. For exampl e,
wire[0:15] DBus; // These are declarations, not selects.
reg[127:0] Video;
...
assign DBus[8:15] = 8'b00zz_xx11; // Bits 0..7 unaffected.
...
always@(posedge BitClock)
begin
...
Video[64:1] <= 64'h33b4_1223_1112_af01; // Bit 0 unaffected.
end
2010-06-24 Essenti al s of Ver i l og Sl i de 110
Vector Bi t-Reversal
Reversal = a ki nd of bi t-swi zzl e.
Not al l owed i n a si ngl e assi gnment statement:
reg[7:0] OldByte, NewByte;
reg[0:7] Rev;
...
NewByte = OldByte[0:7]; // Illegal: Modifies value.
NewByte = Rev[0:7]; // OK. Declared with bit 0 on left.
Bi t-reversal onl y can be done bi t-by-bi t, for exampl e i n a for l oop:
reg[7:0] OldByte, NewByte;
integer i;
...
for (i=0; i<=7; i=i+1)
NewByte[i] = OldByte[7-i]; // Each bit keeps its value.
Note: Vari abl e i ndi ces are al l owed i n bi t-sel ects but never i n part-sel ects.
2010-06-24 Essenti al s of Ver i l og Sl i de 111
Arrays
Used to model a hardware memory (RAM or ROM). Decl arati on syntax i s:
vector_type[vector_range] array_name [array_range];
For exampl e, an array of 4 integers:
integer Int_Array[0:3];
An array of 4 bytes, each wi th bi t 7 the MSB:
reg[7:0] Byte_Array[3:0];
Array range expressi on i s an enumerati on of the words stored; word-order
i s i rrel evant to any val ue i n the array.
Vector range expressi on i s a true, di rected, range, not an enumerati on; bi t-
order determi nes val ue.
Array restri cti ons:
• One address (vari abl e or constant) al l owed per array expressi on.
• No assi gnment of enti re array al l owed.
2010-06-24 Essenti al s of Ver i l og Sl i de 112
Array Exampl e: Si mpl e RAM
module RAM (output[7:0] Obus
, input[7:0] Ibus
);
reg[7:0] Storage[15:0];
reg[7:0] ObusReg;
//
assign #1 Obus = ObusReg;
//
always@(posedge Clk)
endmodule
2010-06-24 Essenti al s of Ver i l og Sl i de 113
End Vectors and Arrays
Veri l og Model l i ng Summary and Revi ew
2010-06-24 Essenti al s of Ver i l og Sl i de 114
Model l i ng Sequenti al Logi c
Sequenti al l ogi c general l y requi res procedural veri l og code.
Cruci al : Desi gn the cl ocki ng for adequate setup ti me.
Use a si ngl e cl ock:
One edge to i ni ti ate changes
Consi der usi ng the opposi te edge to sampl e resul ts.
I ndependent cl ocks usual l y are a bad i dea:
• Worki ng hardware wi l l requi re synchroni zi ng l atches.
• Si mul ati on i s determi ni sti c -- speci al work to emul ate i ndependentl y
dri fti ng cl ocks.
I ndependent cl ocks someti mes are unavoi dabl e:
• Communi cati ng between di fferent computers.
• Ethernet or other seri al l i nks.
2010-06-24 Essenti al s of Ver i l og Sl i de 115
Revi ew: Veri l og Rul es of Thumb
• Use nonbl ocki ng assi gnments for cl ocked l ogi c.
• Use bl ocki ng assi gnments for uncl ocked l ogi c (or, combi nati onal ).
• Use always@(*) for combi nati onal bl ocks.
• Keep del ays out of procedural code, i f possi bl e. Preferabl y, l ump del ays
i nto conti nuous assi gnments.
• Never assi gn to the same vari abl e i n more than one always bl ock.
• Never mi x bl ocki ng and nonbl ocki ng assi gnments i n the same always
bl ock.
2010-06-24 Essenti al s of Ver i l og Sl i de 116
Lab 5 I ntroducti on
Veri l og Decoder
2010-06-24 Essenti al s of Ver i l og Sl i de 117
Lab 5: Counter-Decoder Desi gn
Desi gn i s CountDec.
Cl ock dri ves a resettabl e, 4-bi t up-counter.
The 16 count val ues are i nput to a decoder:
• Decoder produces 12 one-hot patterns on a 16-bi t bus.
• Decoder i ssues a si mul ati on error on the 4 undecodabl e i nputs.
2010-06-24 Essenti al s of Ver i l og Sl i de 118
Lab 5: Decoder Basi cs
Decodi ng i s a combi nati onal process.
Decoders usual l y output a one-hot transl ati on of thei r i nputs.
• Address decodi ng for a RAM.
• Control s for di screte functi ons, such as LED di gi t di spl ays.
For exampl e, a basi c decoder for a two-bi t i nput:
reg[1:0] SelBus;
reg[3:0] DecodedBus;
...
always@(*) // always@(SelBus) OK, too.
begin
case (SelBus)
2'b00: DecodedBus = 4'b0001;
2'b01: DecodedBus = 4'b0010;
2'b10: DecodedBus = 4'b0100;
2'b11: DecodedBus = 4'b1000;
default: DecodedBus = 'bx; // e. g., for an 'x' in.
endcase
end
2010-06-24 Essenti al s of Ver i l og Sl i de 119
The Lab 5 Decoder
• A 4-bi t i nput bus.
• A defi ned 16-bi t output for val ues 4'd0 to 4'd11.
• Undefi ned output for 4'd12 to 4'd15.
• Si mul ati on error message for undefi ned outputs.
The requi red outputs:
I nput Output
0 16'b0100_0000_0000_0000
1 16'b0000_0000_0000_0001
2 16'b0000_0000_0000_0100
3 16'b0000_0000_0000_1000
4 16'b0000_0000_0001_0000
5 16'b0000_0000_0010_0000
6 16'b0000_0000_1000_0000
7 16'b0000_0001_0000_0000
8 16'b0000_0100_0000_0000
9 16'b0000_1000_0000_0000
10 16'b0001_0000_0000_0000
11 16'b1000_0000_0000_0000
(>11) 16'hxxxx
2010-06-24 Essenti al s of Ver i l og Sl i de 120
End of Veri l og Course
Wrap-up Lecture
2010-06-24 Essenti al s of Ver i l og Sl i de 121
Wrap-up Lecture: The Val ue of Synthesi s
Veri l og RTL si mul ati on:
• Cl ari fi es desi gner i deas.
• Veri fi es functi onal i ty.
• Fakes ti mi ng (except cl ock).
Synthesi s produces a netl i st:
• Permi ts back-annotated trace and gate del ays.
• Al l ows si mul ati on or formal methods to veri fy RTL functi onal i ty.
• Al l ows si mul ati on and stati c ti mi ng veri fi cati on of
¦ Propagati on del ays of the gates.
¦ Setup, hol d, and other cl ocki ng constrai nts.
Synthesi s al so enforces some good veri l og codi ng practi ces.
2010-06-24 Essenti al s of Ver i l og Sl i de 122
Wrap-up Lecture: Constructs Not Covered
Language-specific constructs:
tradi ti onal (verilog-1995) headers. many compi l er di recti ves.
tasks and functi ons*. speci fy bl ocks and ti mi ng arcs.
repeat, whi l e, forever control s. ti mi ng checks.
parameters, l ocal params*. generate bl ocks*.
many pri mi ti ve gate features. i nstance arrays.
swi tch-l evel model l i ng;
strength; contenti on.
compl ex del ay si mul ati on.
net types. si mul ati on schedul er str ati fi ed event queue*.
user-defi ned pri mi ti ves (UDP's). system tasks and functi ons, i ncl udi ng fi l e I /O.
Contextual constructs:
Backus-Naur format* (BNF).
back-annotati on of netl i sts* (SDF fi l es).
VCD trace fi l e dumps.
programmi ng l anguage i nterface (PLI ).
desi gn-for-test* (DFT).
comment di recti ves (for synthesi s).
desi gn compi l er synthesi s scri pts* (TcL).
l i brary devel opment.
(* blue = more i mportant i n VLSI desi gn)
2010-06-24 Essenti al s of Ver i l og Sl i de 123
Wrap-up Lecture: Parti ng Advi ce
You have the bare mi ni mum of veri l og for actual desi gn work; but, experi ence
i s i mpossi bl e to del i ver i n two days.
Suggesti ons:
• Devel op your own styl e through practi ce and more l earni ng of veri l og.
• Do not del ay i n usi ng what has been presented here; forgetti ng can be
as qui ck and effecti ve as l earni ng.
• Obtai n one or more of the referenced textbooks.
• Take other veri l og courses.
• Get a copy of the current I EEE 1364 Std document:
I t i s ful l of codi ng exampl es, cl ari fi cati ons, and expl anati ons.
Compl etel y defi nes the l anguage and the PLI .
Resol ves di fferences of opi ni on.
2010-06-24 Essenti al s of Ver i l og Sl i de 124
That's I t
(pl ease fi l l out eval uati on)

2010-06-24

Essentials of Verilog

List of Slides
Essentials of Verilog .................................................................................................................................................................................... 1 Schedule....................................................................................................................................................................................................... 2 Some Hardware Terminology...................................................................................................................................................................... 3 Some Software Terminology........................................................................................................................................................................ 4 The Verilog Module ..................................................................................................................................................................................... 5 Outline of a Module ..................................................................................................................................................................................... 6 Example of a Module ................................................................................................................................................................................... 7 Lab 1: Minilab Flip-Flop............................................................................................................................................................................. 8 Basic Verilog Data Types ............................................................................................................................................................................ 9 Bits and Vectors: Bits ............................................................................................................................................................................... 10 Bits and Vectors: Vectors.......................................................................................................................................................................... 11 Bits and Vectors: Width Rules.................................................................................................................................................................. 12 reg Variables.............................................................................................................................................................................................. 13 reg Variable Example ................................................................................................................................................................................ 14 wire Variables............................................................................................................................................................................................ 15 wire Variable Connection .......................................................................................................................................................................... 16 wire Variable Example .............................................................................................................................................................................. 17 wire Variable Contention Example ........................................................................................................................................................... 18 integer Variables ....................................................................................................................................................................................... 19 integer Variable Example.......................................................................................................................................................................... 20 End Verilog Variables................................................................................................................................................................................ 21 Basic Verilog Operators............................................................................................................................................................................. 22 Logical Operators ...................................................................................................................................................................................... 23 Bitwise Operators ...................................................................................................................................................................................... 24 Unary Bitwise Operators........................................................................................................................................................................... 25 Arithmetic Operators................................................................................................................................................................................. 26 Relational Operators ................................................................................................................................................................................. 27 Shift Operators .......................................................................................................................................................................................... 28 Conditional Operator................................................................................................................................................................................. 29 End Basic Verilog Operators ..................................................................................................................................................................... 30 Sequential RTL.......................................................................................................................................................................................... 31 RTL Procedural Control: if ....................................................................................................................................................................... 32 RTL Procedural Control: case .................................................................................................................................................................. 33 RTL Procedural Control: for..................................................................................................................................................................... 34 RTL Expressions & Statements ................................................................................................................................................................ 35 Expressions & Statements in RTL Mux.................................................................................................................................................... 36