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POST GRADUATE DIPLOMA
VLSI DESIGN & TECHNOLOGY
Most Advanced and Comprehensive Bridging Course Structure in VLSI Industry For Engineering Graduates
Taught By Industry Experts Based On Industry Standard ASIC Flow Using Industry Standard EDA Tools Enhance Job Prospects Significantly Focused For Industry Requirements Architecture Exploration Advanced Digital Design Verilog Coding Styles Advanced Verification Techniques Synthesis and STA Floor Planning Place and Route
Bridging The Gap
100 % Job Oriented Cadence Tools Based Flow
Post Graduate Diploma in VLSI Design & Technology is an intensive course for enhancing and augmenting knowledge of the students in VLSI Design field. This course is structured to build upon basic Digital electronics and CMOS subjects which students take in their undergraduate studies and train them in the specialized field of VLSI Design. IIVDT courses are highly modular with each module providing comprehensive training on specific aspect of the VLSI Design flow.
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2 and 3 block FSM Coding MODULE 6 Advanced Functional Verification Delay Concepts Tasks & Functions Stimulus generation Race conditions File IO Operations M iscellaneous constructs System Tasks Compiler directives Verification Process Test bench structures Bus function models Self Checking Testbenches Testbench Stimulus Randomization Functional Verification Coverage Statement Branch Expression Path Toggle “An Employment Oriented Extensive Professional VLSI Course” . 2 and 3 block FSM Coding 1-Hot FSM Coding MODULE 5S ystem Verilog For Digital Design Basic FSM Coding Guidelines M oore and M ealy FSM Coding 1. ROM Clock-gating FIFO Design Clock-domain crossing issues Low power techniques Reset Assertion De-assertion MODULE 4Verilog HDL For Digital Design Introduction to HDLs Basic constructs Syntax M odeling/Abstraction styles Data Types Verilog Operators Logical Operators Bitwise and Reduction Operators Concatenation Operator Conditional Operators Blocking and Non-Blocking Operators Procedures Tasks and Functions S tate Machine Coding Basic FSM Coding Guidelines M oore and M ealy FSM Coding 1.Course Contents MODULE 1 VLS I Essentials VLS I Overview Evolution of integration technology Overview of manufacturing technology Overview of ASIC/VLSI Design flow CMOS Design History of transistors Types in transistor logic MOS Technology CMOS Inverter Characteristics Logic gates. latches and flip-flops Adders. M ultiplexers and M ultipliers Stick diagrams Layout Digital Logic Design Introduction to Digital logic Number Systems Boolean algebra Boolean minimization Combinational circuit design Sequential circuit design Finite state machines Designing complex digital circuits Logic families M iscellaneous concepts MODULE 2 – VLS I CAD En vironment Linux OS Introduction Creating Files Directory Structure Advanced Linux Commands Shell Scripting Text Editors GVim Gedit/Nedit Vi MODULE 3Advanced Digital Design System On Chip Architecture Shift Registers and Counters Data processing Circuits Finite State M achine Design M ealy M oore Binary Gray One-Hot M emories RAM .
MODULE 7 – Advanced Verification Using S ystem Verilog Introduction to SV Enhancement to System Verilog Array Structures & Unions. Interface and M odports OOP's Concept of System Verilog Inheritance Virtual methods Parameterized classes Virtual interface S ystem Verilog Verification Constructs Constrained Randomization techniques System Verilog Event Ordering Clocking block and Program block Functional Coverage Class Based verification environment S ystem Verilog Assertions Introduction to Assertion Overview of properties and assertion SVA Properties and operators SVA Sequences and operators Checkers MODULE 8 – CAD En vironment Automation Perl Scripting MODULE 9 – Extensive Interview Preparation Technical Interview Preparation Aptitude Interview Preparation MODULE 10 – Industry S tandard Major Projects Understanding Standard Protocol Specification Creating Design Architecture Detailed Design Specification Creation Using Verilog For Design Implementation Develop Testbench for Directed Tests Create self Checking Regression Suite MODULE 11 .( Optional ) Digital Design Implementation Using FPGA FPGA Architecture Introduction to Programmable logic Basic Components of FPGA LUT CLB Switch M atrix IOB FPGA Design Flow Xilinx tool Flow Reading Reports Implementing IP cores Global timing Constraints Synchronous Design Techniques HDL Coding Techniques FPGA Design Techniques Synthesis Techniques Implementation Options Cadence Certified Trainers Post Gradate Diploma Add-on Modules MODULE 12 – AS IC S ynthesis Synthesis Definition and Goals Technology Libraries Environment Description WireLoad M odels Process Conditions Timing Constraints Generation Fundamentals Of Timing Optimization Constraints Process of Logic S ynthesis Reading Verilog Elaboration Synthesize Optimization S ynthesis S trategies Top-down Synthesis Bottom Up Synthesis Path Group Creation Grouping/Ungrouping MODULE 13 – AS IC Design For Testability (DFT) MODULE 14 – S tatic Timing Analysis Timing Paths And Groups Analysis Timing Path Optimizing Constraints MODULE 15 Backend Physical Design Flow Floor Planning Core Utilization IO Pad Placement IO Pin Placement Placement Blockages Power Planning Core Power Ring Pad Power Ring Placement Methodologies Congestion Driven Placement Timing Driven Placement Clock Tree S ynthesis Routing Design Rule Checking (DRC) .
Taxes Our Students are Placed In Following Companies erutcurtS seeF erutcurtS seeF erutcurtS seeF erutcurtS seeF Post Graduate Diploma 6 Month Duration Rs 95. Taxes .000 + Govt.000 + Govt.000 + Govt. Taxes Diploma Backend Design 2 Month Duration (Part Time) Rs 50.An ISO 9001:2008 Certified Institute Advanced Diploma 4 Month Duration Rs 65.Tech VLSI Projects 4 Month Duration (Part Time) Rs 28. Taxes Certificate Custom Digital 6 Weeks Duration (Part Time) Rs 25. Taxes B.Tech IEEE Projects 4 Month Duration (Part Time) Rs 30.000 + Govt.000 + Govt.000 + Govt. Taxes M.