my_cv | Hardware Description Language | Electronic Design

HARISH SHARMA Contact No.: +91-9784077967

OBJECTIVE Looking for a challenging career which demands the best of my professional ability in terms of technical and analytical skills, and helps me in broadening and enhancing my current skill and knowledge. EDUCATIONAL QUALIFICATION 2011-2013 Pursuing M. Tech. in Electronics and Communication Engineering(ECE) from ITM University, Gurgaon with CGPA 7.02 till 3rd semester. 2006-2010 B. Tech. in Electronics and Communication Engineering (ECE) from L.I.E.T. ,Alwar (Formerly: Laxmi Devi Institute of Engineering and Technology, affiliated to RTU Kota) with a percentage of 68.31% . 2005-2006 Higher Secondary from Yashwant sr. sec. school (affiliated to B.S.E.R.), Alwar (Rajasthan) 70.61%. 2002-2003 Senior Secondary from Yashwant sr. sec. school (affiliated to B.S.E.R.), Alwar (Rajasthan) 66.16% .

TECHNICAL-SKILLS Concurrent Languages - HDLs • RTL Design in Verilog HDL and VHDL Scripting Languages • Shell, Perl/Tk, TCL/Tk Operating Systems • Linux – RedHat v6, Windows XP/Vista/7 EDA Tools & Technology • Cadence Design Systems • • • • NC-Sim,LTspice Mentor Graphics ModelSim SE v6.0a Xilinx

• Xilinx ISE Design Suite 12.3/13.2, Xilinx ISE v7, FPGA Implementation Xilinx SPARTAN 3AN • Tanner 7

PROJECTS • • Dissertation in MULTI CLOCK FIFO for Network on Chip (noc). Noida ITM on Modeling and Simulation of I-V Char. . Seven Segment Display. VerilogHDL. Rajasthan. Xilinx Hardware Design of Mobile Bugg.. OrCAD – Pspice. Mini Project(M. • TRAINING ASSOCIATIONS • • DKOP Labs. Mini Project (B. Gurgaon Tool Command Language and Tk Toolkit (Tcl/Tk) Skills Development Program in RTL Design and Verification. CMOS & Digital Design & Verilog. • • • • Training in VLSI Designs from DKOP Labs where I gained industrial insight into various technologies & tools like FPGA. Of SOLAR CELL Using LTspice. INTERESTS • Digital VLSI Design • RTL Design and Verification • EDA Tools Designing • Physical Design • Digital Electronics • Electronic Device and Circuits. (ii) Design a synchronous circular FIFO structure using VerilogHDL. Major Project ( Radio Frequency Identifier For Security Systems. TCL-TK. VHDL. Ripple Carry Counter. Design and FPGA Implementation of UART. Kali Mori Alwar. PS2 Key Board Interfacing. Verilog HDL: (i) Analysis & simulation of 5-bit Multiplier design using pipelined and Non -pipelined approaches. • Industrial Training on PLCC (Power Line Carrier Communication) from Power Grid Sub Station.

Ram Prakash Sharma. 1988 Mr. No.PERSONAL INFORMATION Date of Birth: Father’s Name: Nationality: Sex: Marital Status: Languages known: Address: 23th April. Ram Prakash Sharma Indian Male Single English. Hindi Mr. 20 A. Place: Gurgaon Date: FEB 2013 Harish Sharma .Hardeva Vihar Alwar Rajasthan-301001 DECLARATION I hereby declare that the information furnished above is true to best of my knowledge. H.

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