ARM-based Embedded MPU

SAMA5D3 Series
SUMMARY DATASHEET

Description
The Atmel SAMA5D3 series is a high-performance, power-efficient embedded MPU based on the ARM ® Cortex ® -A5 processor, achieving 536 MHz with power consumption levels below 0.5 mW in low-power mode. The device features a floating point unit for high-precision computing and accelerated data processing, and a high data bandwidth architecture. It integrates advanced user interface and connectivity peripherals and security features. The SAMA5D3 series features an internal multi-layer bus architecture associated with 39 DMA channels to sustain the high bandwidth required by the processor and the high-speed peripherals. The device offers support for DDR2/LPDDR/LPDDR2 and MLC NAND Flash memory with 24-bit ECC. The comprehensive peripheral set includes an LCD controller with overlays for hardware-accelerated image composition, a touchscreen interface and a CMOS sensor interface. Connectivity peripherals include Gigabit EMAC with IEEE1588, 10/100 EMAC, multiple CAN, UART, SPI and I2C. With its secure boot mechanism, hardware accelerated engines for encryption (AES, TDES) and hash function (SHA), the SAMA5D3 ensures anti-cloning, code protection and secure external data transfers. The SAMA5D3 series is optimized for control panel/HMI applications and applications that require high levels of connectivity in the industrial and consumer markets. Its lowpower consumption levels make the SAMA5D3 particularly suited for battery-powered devices. There are four SAMA5D3 devices in this series. Table 1-1 “SAMA5D3 Devices” shows the differences in the embedded features. All other features are available on all derivatives; this includes the three USB ports as well as the encryption engine and secure boot features.

This is a summary document. The complete document is available on the Atmel website at www.atmel.com.

11121BS–ATARM–08-Mar-13

1.

Features
z

Core
z

ARM® Cortex®-A5 Processor with ARM v7-A Thumb2® Instruction Set
z

CPU Frequency up to 536 MHz

z z

32 Kbyte Data Cache, 32 Kbyte Instruction Cache, Virtual Memory System Architecture (VMSA) Fully Integrated MMU and Floating Point Unit (VFPv4) One 160 Kbyte Internal ROM Single-cycle Access at System Speed, Embedded Boot Loader: Boot on NAND Flash, SDCard, eMMC, serial DataFlash®, selectable Order One 128 Kbyte Internal SRAM, Single-cycle Access at System Speed High Bandwidth 32-bit Multi-port Dynamic Ram Controller supporting 512 Mbyte 8 bank DDR2/LPDDR/LPDDR2 Independent Static Memory Controller with SLC/MLC NAND Support with up to 24-bit Error Correcting Code (PMECC) Power-on Reset Cells, Reset Controller, Shut Down Controller, Periodic Interval Timer, Watchdog Timer and Real-time Clock Boot Mode Select Option, Remap Command Internal Low-power 32 kHz RC Oscillator and Fast 12 MHz RC Oscillators Selectable 32768 Hz Low-power Oscillator and 12 MHz Oscillator One 400 to 1000 MHz PLL for the System and one PLL at 480 MHz optimized for USB High Speed 39 DMA Channels including two 8-channel 64-bit Central DMA Controllers 64-bit Advanced Interrupt Controller Three Programmable External Clock Signals Programmable Fuse Box with 256 fuse bits, 192 of them available for Customer Shut Down Controller Battery Backup Registers Clock Generator and Power Management Controller Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities LCD TFT Controller with Overlay, Alpha-blending, Rotation, Scaling and Color Space Conversion ITU-R BT. 601/656 Image Sensor Interface Three HS/FS/LS USB Ports with On-Chip Transceivers
z z

z

Memories
z z z z

z

System running up to 166 MHz
z z z z z z z z z

z

Low Power Management
z z z z

z

Peripherals
z z z

One Device Controller One Host Controller with Integrated Root Hub (3 Downstream Ports)

z z z z z z z z z z

One 10/100/1000 Mbps Gigabit Ethernet Mac Controller (GMAC) with IEEE1588 support One 10/100 Mbps Ethernet Mac Controller (EMAC) Two CAN Controllers with 8 Mailboxes, fully Compliant with CAN 2.0 Part A and 2.0 Part B Softmodem Interface Three High Speed Memory Card Hosts (eMMC 4.3 and SD 2.0) Two Master/Slave Serial Peripheral Interface Two Synchronous Serial Controllers Three Two-wire Interface up to 400 Kbits supporting I2C Protocol and SMBUS Four USARTs, two UARTs, one DBGU Two Three-channel 32-bit Timer/Counters

SAMA5D3 Series [SUMMARY DATASHEET]
11121BS–ATARM–08-Mar-13

2

z z z

One Four-channel 16-bit PWM Controller One 12-channel 12-bit Analog-to-Digital Converter with Resistive Touch-Screen function Write Protected Registers TRNG: True Random Number Generator Encryption Engine
z z z

z

Security
z z

AES: 256-bit, 192-bit, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications TDES: Two-key or Three-key Algorithms, Compliant with FIPS PUB 46-3 Specifications SHA: Supports Secure Hash Algorithm (SHA1, SHA224, SHA256, SHA384, SHA512)
®

z

Atmel Secure Boot Solution Five 32-bit Parallel Input/Output Controllers 160 I/Os Input Change Interrupt Capability on Each I/O Line, Selectable Schmitt Trigger Input Individually Programmable Open-drain, Pull-up and Pull-down Resistor, Synchronous Output, Filtering Slew Rate Control on High Speed I/Os Impedance Control on DDR I/Os 324-ball LFBGA, pitch 0.8 mm

z

I/O
z z z z z z

z

Package
z

Table 1-1.

SAMA5D3 Devices SAMA5D31 SAMA5D33 X X X X X X X X SAMA5D34 X X X X X X X X X SAMA5D35

LCDC GMAC EMAC CAN0, CAN1 HSMCI2 UART0 UART1 TC1

X

SAMA5D3 Series [SUMMARY DATASHEET]
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3

2.

Block Diagram

Figure 2-1. SAMA5D3 Block Diagram
DH S DH DP SD /HH M/ SD HH PA G1 SD 25 MA GT CK GTXCK G12 XE -G 5CK GC N RX -G C O GRRS, TX K X G E GR ER CO R - L GT X0- GRX X GR D GM 0-G X7 V D TX7 ER C, G M E E T FC DI O X K EC EN RS ER D V E T X 0- E , E R X R X EM 0-ET X1 ER DC X1 ,E LC MD LCD-D D_ AT0 IO LC V -L D_ SY CD LC PC NC _ D_ K , L DA DE , LC CD T23 N, D_ _H LC D S IS I_D D_ ISP YN C PW IS OI_P IS M IS CK I_D1 I_H 1 SY NC , IS I_V SY NC DD R_ CA L P DD R_ CA LN

NT RS T TD I TD O TM TC S/SW K/S D WC IO LK JTA GS EL

TST

BMS

HH S HH DPC SD H H MC HH SDP SD B MB VB G

SysC
FIQ IRQ

JTAG / SWD
AIC
In-Circuit Emulator

HS Trans

HS Trans

HS Trans

PIO

DDR_VREF DDR_A0-DDR_A13 DDR_D0-DDR_D31 DDR_DQM[3..0] DDR_DQS[3..0]

PIO

DRXD DTXD PCK0-PCK2

DBGU

PC PB

PA HS USB Device DMA GMAC 10/100/1000 EMAC 10/100 LCD ISI

Cortex-A5
PLLA PLLUTMI
ICache 32 KB MMU BIU

VFP DCache 32 KB

HS EHCI USB HOST DMA

DDR2 LPDDR2 512 MB

XIN XOUT

Osc12 MHz

PMC

DMA

DMA

DMA

DMA

12 MHZ RC Osc WDT RC
XIN32 XOUT32 SHDN WKUP VDDBU NRST OSC 32K

I/D
PIT
4 GPBR EBI

DDR_DQSN[3..0] DDR_CS DDR_CLK,DDR_CLKN DDR_CKE DDR_RAS, DDR_CAS DDR_WE DDR_BA[2..0] D0-D15 A21/NANDALE A22/NANDCLE NRD/NANDOE NWE/NWR0/NANDWE NCS3/NANDCS NANDRDY A0/NBS0 A1-A20 A23-A25 NWR1/NBS1 NCS0,NCS1,NCS2 NWAIT

Multi-Layer Matrix
RTC RSTC
TRNG SHA AES TDES DMA

SHDC POR POR PIOA PIOC PIOE

NAND Flash Controller MCL/SLC ECC (4 KB SRAM)

PIOB PIOD

ROM 160 KB

SRAM0 64 KB

SRAM1 64 KB

8-CH DMA0

8-CH DMA1

Peripheral Bridge

Reduced Static Memory Controller

PIO

DMA CAN0 CAN1 TWI0 TWI1 TWI2

DMA USART0 USART1 USART2 USART3

DMA

DMA SPI0 SPI1

DMA SSC0 SSC1

DMA MCI0/MCI1/MCI2 SD/SDIO eMMC TC0, TC1 TC2, TC3 TC4, TC5

DMA 4-CH PWM

UART0 UART1

Real-time Events

DMA 12-CH 12-bit ADC TouchScreen SMD

PIO

P
N CA RX NT 0-C X0 A -C NR A X TW NT 1 TW D0 X1 CK -TW 0TW D2 CK CT 2 S RT 03 SCS03 RDK0X 3 TX 0-3 UR D0 D -3 UT X0NP U XD R CS D 0 X 1, NP -UT 1 XD CS 1 2, NP C NP S3 C SP S0 C M K O M SI TK ISO 0 TF -TK TD 0-T 1 F RD 0-T 1 0 D RF -RD1 0 1 RK -RF 0 1 M -RK CI 1 M 0_C C M I1_ DA CI C 2 D M _C A C D M I0_ A CI C M MC 1_CK CI I K M 0_D 2_C CI A K M 1_D [7..0 CI A ] 2 [ TI _D 3..0 O A ] TI A0 [3.. O -T 0] TC B0 IO -T A PW LK0 IOB5 M -TC 5 LK PW H0 5 PW ML PW M 0-P MH FI W 3 0- M PW L3 M TS FI AD 3 TR I G AD 0 AD UL 1 AD UR 2 AD LL GP 3 AD A LR 5- D4 G P TS PAD I AD 11 VR EF

DIB

SPI0_, SPI1_

CA

SAMA5D3 Series [SUMMARY DATASHEET]
11121BS–ATARM–08-Mar-13

DI

BN

4

3.

Signal Description
Table 3-1 gives details on the signal names classified by peripheral.
Signal Description List Function Type Active Level Frequency (MHz) Comments

Table 3-1.

Signal Name

Clocks, Oscillators and PLLs XIN XOUT XIN32 XOUT32 VBG PCK0 - PCK2 Main Oscillator Input Main Oscillator Output Slow Clock Oscillator Input Slow Clock Oscillator Output Bias Voltage Reference for USB Programmable Clock Output Input Output Input Output Analog Output

Shutdown, Wake-up Logic SHDN WKUP Shut-Down Control Wake-Up Input ICE and JTAG TCK/SWCLK TDI TDO TMS/SWDIO JTAGSEL Test Clock/Serial Wire Clock Test Data In Test Data Out Test Mode Select/Serial Wire Input/Output JTAG Selection Reset/Test NRST TST NTRST BMS Microcontroller Reset Test Mode Select Test Reset Signal Boot Mode Select I/O Input Input Input Debug Unit - DBGU DRXD DTXD Debug Receive Data Debug Transmit Data Input Output Advanced Interrupt Controller - AIC IRQ FIQ External Interrupt Input Fast Interrupt Input Input Input Low Input Input Output I/O Input Output Input

PIO Controller - PIOA - PIOB - PIOC - PIOD - PIOE PA0 - PAxx PB0 - PBxx PC0 - PCxx PD0 - PDxx PE0 - PExx Parallel IO Controller A Parallel IO Controller B Parallel IO Controller C Parallel IO Controller D Parallel IO Controller E I/O I/O I/O I/O I/O

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11121BS–ATARM–08-Mar-13

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Table 3-1.

Signal Description List (Continued) Function Type Active Level Frequency (MHz) Comments

Signal Name

External Bus Interface - EBI D0 - D15 A0 - A25 NWAIT Data Bus Address Bus External Wait Signal I/O Output Input Static Memory Controller - HSMC NCS0 - NCS3 NWR0 - NWR1 NRD NWE NBS0 - NBS1 NANDOE NANDWE Chip Select Lines Write Signal Read Signal Write Enable Byte Mask Signal NAND Flash Output Enable NAND Flash Write Enable Output Output Output Output Output Output Output DDR2/LPDDR Controller DDR_VREF DDR_CALP DDR_CALN DDR_CK, DDR_CKN DDR_CKE DDR_CS DDR_BA[2..0] DDR_WE DDR_RAS, DDR_CAS DDR_A[13..0] DDR_D[31..0] DQS[3..0] DQSN[3..0] DQM[3..0] Reference Voltage Positive Calibration Reference Negative Calibration Reference DDR2 differential clock DDR2 Clock Enable DDR2 Controller Chip Select Bank Select DDR2 Write Enable Row and Column Signal DDR2 Address Bus DDR2 Data Bus Differential Data Strobe DQSN must be connected to DDR_VREF for DDR2 memories Write Data Mask Input Input Input Output Output Output Output Output Output Output I/O/-PD I/O- PD I/O- PD Output High Low Low Low Low Low Low Low Low Low Low Low Low

High Speed Multimedia Card Interface - HSMCI0-2 MCI0_CK, MCI1_CK, MCI2_CK MCI0_CDA,MCI1_C DA, MCI2_CDA MCI0_DA[7..0] MCI1_DA[3..0] MCI2_DA[3..0) Multimedia Card Clock Multimedia Card Command Multimedia Card 0 Data Multimedia Card 1 Data Multimedia Card 2 Data I/O I/O I/O I/O I/O

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Table 3-1.

Signal Description List (Continued) Function Type Active Level Frequency (MHz) Comments

Signal Name

Universal Synchronous Asynchronous Receiver Transmitter- USART0-3 SCKx TXDx RXDx RTSx CTSx USARTx Serial Clock USARTx Transmit Data USARTx Receive Data USARTx Request To Send USARTx Clear To Send I/O Output Input Output Input

Universal Asynchronous Receiver Transmitter - UARTx [1..0] UTXDx URXDx UARTx Transmit Data UARTx Receive Data Output Input

Synchronous Serial Controller - SSCx [1..0] TDx RDx TKx RKx TFx RFx SSC Transmit Data SSC Receive Data SSC Transmit Clock SSC Receive Clock SSC Transmit Frame Sync SSC Receive Frame Sync Timer/Counter - TCx [5..0] TCLKx TIOAx TIOBx TC Channel x External Clock Input TC Channel x I/O Line A TC Channel x I/O Line B Input I/O I/O Output Input I/O I/O I/O I/O

Serial Peripheral Interface - SPIx [1..0] SPIx_MISO SPIx_MOSI SPIx_SPCK SPIx_NPCS0 SPIx_NPCS[3..1] Master In Slave Out Master Out Slave In SPI Serial Clock SPI Peripheral Chip Select 0 SPI Peripheral Chip Select I/O I/O I/O I/O Output Low Low

Two-Wire Interface -TWIx [2..0] TWDx TWCKx Two-wire Serial Data Two-wire Serial Clock I/O I/O CAN controller - CANx CANRXx CANTXx CAN input CAN output Input Output Soft Modem - SMD DIBN DIBP Soft Modem Signal Soft Modem Signal I/O I/O

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11121BS–ATARM–08-Mar-13

7

Table 3-1.

Signal Description List (Continued) Function Type Active Level Frequency (MHz) Comments

Signal Name

Pulse Width Modulation Controller- PWMC PWMH[3..0] PWML[3..0] PWMFIx PWM Waveform Output High PWM Waveform Output LOW PWM Fault Input Output Output Input USB Host High Speed Port - UHPHS HHSDPA HHSDMA HHSDPB HHSDMB HHSDPC HHSDMC USB Host Port A High Speed Data + USB Host Port A High Speed Data USB Host Port B High Speed Data + USB Host Port B High Speed Data USB Host Port C High Speed Data + USB Host Port C High Speed Data Analog Analog Analog Analog Analog Analog

USB Device High Speed Port - UDPHS DHSDP DHSDM USB Device High Speed Data + USB Device High Speed Data Analog Analog

GIgabit Ethernet 10/100/1000 - GMAC GTXCK G125CK G125CKO GTXEN GTX[7..0] GTXER GRXCK GRXDV GRX[7..0] GRXER GCRS GCOL GMDC GMDIO Transmit Clock or Reference Clock 125 MHz input Clock 125 MHz output Clock Transmit Enable Transmit Data Transmit Coding Error Receive Clock Receive Data Valid Receive Data Receive Error Carrier Sense and Data Valid Collision Detect Management Data Clock Management Data Input/Output Input Input Output Output Output Output Input Input Input Input Input Input Output I/O

RMII Ethernet 10/100 - EMAC EREFCK ETXEN ETX[1..0] ECRSDV ERX[1..0] ERXER Transmit Clock or Reference Clock Transmit Enable Transmit Data Carrier Sense/Data Valid Receive Data Receive Error Input Output Output Input Input Input

SAMA5D3 Series [SUMMARY DATASHEET]
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Table 3-1.

Signal Description List (Continued) Function Management Data Clock Management Data Input/Output Type Output I/O Active Level Frequency (MHz) Comments

Signal Name EMDC EMDIO

LCD Controller - LCDC LCDDAT[23..0] LCDVSYNC LCDHSYNC LCDPCK LCDDEN LCDPWM LCDDISP LCD Data Bus LCD Vertical Synchronization LCD Horizontal Synchronization LCD pixel Clock LCD Data Enable LCDPWM for Contrast Control LCD Display ON/OFF Output Output Output Output Output Output Output Image Sensor Interface - ISI ISI_D[11..0] ISI_HSYNC ISI_VSYNC ISI_PCK Image Sensor Data Image Sensor Horizontal Synchro Image Sensor Vertical Synchro Image Sensor Data clock Input input input input

Touch Screen Analog-to-Digital Converter - ADC AD0UL AD1UR AD2LL AD3LR AD4PI AD5-AD11 ADTRG ADVREF Upper Left Touch Panel Upper Right Touch Panel Lower Left Touch Panel Lower Right Touch Panel Panel Input 7 Analog Inputs ADC Trigger ADC Reference Analog Analog Analog Analog Analog Analog Input Analog

SAMA5D3 Series [SUMMARY DATASHEET]
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4.

Package and Pinout
The SAMA5D3 product is available in a 324-ball LFBGA package.

4.1

Mechanical Overview of the 324-ball LFBGA Package
Figure 4-1 shows the orientation of the 324-ball BGA Package.

Figure 4-1. Orientation of the 324-ball LFBGA Package
Bottom VIEW
V U T R P N M L K J H G F E D C B A

1 2

3 4 5 6 7 8 9 10 11 12 13 14 15

16 17 18

SAMA5D3 Series [SUMMARY DATASHEET]
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4.2

324-ball LFBGA Package Pinout
SAMA5D3 Pinout for 324-ball LFBGA Package
Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal, Dir, PU, PD, HiZ, ST
PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST ISI_D0 ISI_D1 TWD2 TWCK2 PWMH0 PWML0 PWMH1 PWML1 I/O O O O O O ISI_D2 ISI_D3 ISI_D4 ISI_D5 ISI_D6 ISI_D7 I I I I I I I I PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST URXD1 UTXD1 PWMH0 PWML0 TK1 TF1 PWMH1 PWML1 TD1 RK1 PWMH2 PWML2 I O O O I/O I/O O O O I O O ISI_VSYNC ISI_HSYNC I I PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST

Table 4-1.

Pin
E3 F5 D2 F4 D1 J10 G4 J9 F3 J8 E2 K8 F2 G6 E1 H5 H3 H6 H4 H7 H2 J6 G2 J5 F1 J4 G3 J3 G1 K4 H1 K3 T2 N7 T3 N6 P5 T4 R4 U1 R5 P3

Power Rail
VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1

I/O Type
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO_CLK2 GPIO GPIO GPIO GMAC GMAC GMAC GMAC GMAC GMAC GMAC GMAC GMAC GMAC

Signal
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9

Dir
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

Signal

Dir

Signal
LCDDAT0 LCDDAT1 LCDDAT2 LCDDAT3 LCDDAT4 LCDDAT5 LCDDAT6 LCDDAT7 LCDDAT8 LCDDAT9 LCDDAT10 LCDDAT11 LCDDAT12 LCDDAT13 LCDDAT14 LCDDAT15 LCDDAT16 LCDDAT17 LCDDAT18 LCDDAT19 LCDDAT20 LCDDAT21 LCDDAT22 LCDDAT23 LCDPWM LCDDISP LCDVSYNC LCDHSYNC LCDPCK LCDDEN TWD0 TWCK0 GTX0 GTX1 GTX2 GTX3 GRX0 GRX1 GRX2 GRX3 GTXCK GTXEN

Dir
O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O I/O O O O O O I I I I I O

Signal

Dir

Signal

Dir

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Table 4-1.

SAMA5D3 Pinout for 324-ball LFBGA Package (Continued)
Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal, Dir, PU, PD, HiZ, ST
PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST GTX4 GTX5 GTX6 GTX7 GRX4 GRX5 GRX6 GRX7 G125CKO O O O O I I I I O PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST TIOA3 TIOB3 TCLK3 TIOA4 TIOB4 TCLK4 TIOA5 TIOB5 TCLK5 I/O I/O I I/O I/O I I/O I/O I PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST LCDDAT20 LCDDAT19 TIOA1 TIOB1 TCLK1 PCK2 I/O I/O I O LCDDAT18 LCDDAT17 LCDDAT16 LCDDAT21 O O O O O O PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST

Pin
R6 V3 P6 V1 R7 U3 P7 V2 V5 T6 N8 U4 M7 U5 M8 T5 N9 V4 M9 P8 M10 R9 D8 A4 E8 A3 A2 F8 B3 G8 B4 F7 A1 D7 C6 E7 B2 F6 B1 E6 C3 D6 C4 D5

Power Rail
VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0

I/O Type
GMAC GMAC GMAC GMAC GMAC GMAC GMAC GMAC GMAC GMAC GMAC GMAC GMAC GMAC GMAC GMAC GMAC GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO MCI_CLK GPIO GPIO GPIO GPIO GPIO GPIO

Signal
PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21

Dir
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

Signal

Dir

Signal
GTXER GRXCK GRXDV GRXER GCRS GCOL GMDC GMDIO G125CK MCI1_CDA MCI1_DA0 MCI1_DA1 MCI1_DA2 MCI1_DA3 MCI1_CK SCK1 CTS1 RTS1 RXD1 TXD1 DRXD DTXD ETX0 ETX1 ERX0 ERX1 ETXEN ECRSDV ERXER EREFCK EMDC EMDIO MCI2_CDA MCI2_DA0 MCI2_DA1 MCI2_DA2 MCI2_DA3 MCI2_CK TK0 TF0 TD0 RK0 RF0 RD0

Dir
O I I I I I O I/O I I/O I/O I/O I/O I/O I/O I/O I O I O I O O O I I O I I I O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I

Signal
RF1 RD1 PWMH3 PWML3 CANRX1 CANTX1

Dir
I/O I O O I O

Signal

Dir

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Table 4-1.

SAMA5D3 Pinout for 324-ball LFBGA Package (Continued)
Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal, Dir, PU, PD, HiZ, ST
PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST TWD1 TWCK1 PWMFI0 PWMFI2 I/O O I I ISI_D11 ISI_D10 ISI_D9 ISI_D8 ISI_PCK PWMFI1 I I I I I O PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST TIOA0 TIOB0 TCLK0 I/O I/O I PWMH2 PWML2 PWMH3 PWML3 O O O O PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 O O O CANRX0 CANTX0 PWMFI3 I O I PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PCK0 PCK1 O O PIO, I, PU, ST PIO, I, PU, ST A,I, PD, ST A,I, PD, ST

Pin
C2 G9 C1 H10 H9 D4 H8 G5 D3 E4 K5 P1 K6 R1 L7 P2 L8 R2 K7 U2 K9 M5 K10 N4 L9 N3 L10 N5 M6 T1 N2 M3 M2 L3 M1 N1 L1 L2 K1 K2 J1 J2 P13 R14

Power Rail
VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDANA VDDANA VDDANA VDDANA VDDANA VDDANA VDDANA VDDANA VDDANA VDDANA VDDANA VDDANA VDDIOM VDDIOM

I/O Type
GPIO GPIO GPIO_CLK GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO MCI_CLK GPIO GPIO GPIO_CLK GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO_ANA GPIO_ANA GPIO_ANA GPIO_ANA GPIO_ANA GPIO_ANA GPIO_ANA GPIO_ANA GPIO_ANA GPIO_ANA GPIO_ANA GPIO_ANA EBI EBI

Signal
PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 PE0 PE1

Dir
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

Signal

Dir

Signal
SPI1_MISO SPI1_MOSI SPI1_SPCK SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 URXD0 UTXD0 FIQ MCI0_CDA MCI0_DA0 MCI0_DA1 MCI0_DA2 MCI0_DA3 MCI0_DA4 MCI0_DA5 MCI0_DA6 MCI0_DA7 MCI0_CK SPI0_MISO SPI0_MOSI SPI0_SPCK SPI0_NPCS0 SCK0 CTS0 RTS0 RXD0 TXD0 ADTRG AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 A0/NBS0 A1

Dir
I/O I/O I/O I/O O O O I O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I O I O I I I I I I I I I I I I I O O

Signal

Dir

Signal

Dir

SAMA5D3 Series [SUMMARY DATASHEET]
11121BS–ATARM–08-Mar-13

13

Table 4-1.

SAMA5D3 Pinout for 324-ball LFBGA Package (Continued)
Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal, Dir, PU, PD, HiZ, ST
A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST SCK3 CTS3 RTS3 RXD3 TXD3 SCK2 I/O I O I O I/O A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST CTS2 RTS2 RXD2 TXD2 TIOA2 TIOB2 TCLK2 I O I O I/O I/O I LCDDAT22 LCDDAT23 O O A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST PIO,I, PD, ST PIO, I, PD, ST PIO, I, PD, ST PIO, I, PD, ST PWML1 O PIO,I, PD, ST I, PD, I I O I O O, PU I, ST I, PU, ST I, PU, ST I, ST O SWDIO SWCLK I/O I I, ST I, ST

Pin
R13 V18 P14 U18 T18 R15 P17 P15 P18 R16 N16 R17 N17 R18 N18 P16 M18 N15 M15 N14 M17 M13 M16 N12 M14 M12 L13 L15 L14 L16 U15 U9 U8 V8 U16 V16 T12 T10 V9 P11 R8 M11 N10 P9

Power Rail
VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDBU VDDIOP0 VDDIOP0 VDDIOP0 VDDBU VDDBU VDDBU VDDBU VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0

I/O Type
EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI SYSC SYSC CLOCK CLOCK CLOCK CLOCK SYSC SYSC RSTJTAG RSTJTAG RSTJTAG RSTJTAG RSTJTAG RSTJTAG

Signal
PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PE16 PE17 PE18 PE19 PE20 PE21 PE22 PE23 PE24 PE25 PE26 PE27 PE28 PE29 PE30 PE31 TST BMS XIN XOUT XIN32 XOUT32 SHDN WKUP NRST NTRST TDI TDO TMS TCK

Dir
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I O I O O I I/O I I O I I

Signal

Dir

Signal
A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21/NANDALE A22/NANDCLE A23 A24 A25 NCS0 NCS1 NCS2 NWR1/NBS1 NWAIT IRQ

Dir
O O O O O O O O O O O O O O O O O O O O O O O O O O O O I I

Signal

Dir

Signal

Dir

SAMA5D3 Series [SUMMARY DATASHEET]
11121BS–ATARM–08-Mar-13

14

Table 4-1.

SAMA5D3 Pinout for 324-ball LFBGA Package (Continued)
Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal, Dir, PU, PD, HiZ, ST
I, PD O, PU O, PU I, PD I, PD I, PD I, PD I, PD I, PD I, PD I, PD I, PD I, PD I, PD I, PD I, PD I, PD I, PD I, PD O, PU I, PU O, PU O, PU I O O O O O O O O O O O O O O HiZ HiZ HiZ HiZ HiZ HiZ

Pin
T9 V6 U6 K12 K15 K14 K16 K13 K17 J12 K18 J14 J16 J13 J17 J15 J18 H16 H18 L12 L18 L17 K11 C13 B10 C11 A9 D11 B9 E10 D10 A8 C10 B8 F11 A7 D9 A6 H12 H17 H13 G17 G16 H15

Power Rail
VDDBU VDDIOP0 VDDIOP0 VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR

I/O Type
SYSC DIB DIB EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI

Signal
JTAGSEL DIBP DIBN D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 NCS3/NANDCS NANDRDY NRD/NANDOE NWE/NANDWE DDR_VREF

Dir
I O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I O O I O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O

Signal

Dir

Signal

Dir

Signal

Dir

Signal

Dir

DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO

DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5

SAMA5D3 Series [SUMMARY DATASHEET]
11121BS–ATARM–08-Mar-13

15

Table 4-1.

SAMA5D3 Pinout for 324-ball LFBGA Package (Continued)
Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal, Dir, PU, PD, HiZ, ST
HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ O O O O I, PD I, PD I, PD I, PD I, PU I, PU I, PU I, PU O O O O O O

Pin
F17 G15 F16 E17 G14 E16 D17 C18 D16 C17 B16 B18 C15 A18 C16 C14 D15 B14 A15 A14 E12 A11 B11 F12 A10 E11 G12 E15 B15 D12 E18 G18 B17 B13 D18 F18 A17 A13 C8 B12 A12 B7 C12 E13

Power Rail
VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR

I/O Type
DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO

Signal
DDR_D6 DDR_D7 DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15 DDR_D16 DDR_D17 DDR_D18 DDR_D19 DDR_D20 DDR_D21 DDR_D22 DDR_D23 DDR_D24 DDR_D25 DDR_D26 DDR_D27 DDR_D28 DDR_D29 DDR_D30 DDR_D31 DDR_DQM0 DDR_DQM1 DDR_DQM2 DDR_DQM3 DDR_DQS0 DDR_DQS1 DDR_DQS2 DDR_DQS3 DDR_DQSN0 DDR_DQSN1 DDR_DQSN2 DDR_DQSN3 DDR_CS DDR_CLK DDR_CLKN DDR_CKE DDR_CALN DDR_CALP

Dir
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O I/O I/O I/O I/O I/O I/O I/O I/O O O O O I I

Signal

Dir

Signal

Dir

Signal

Dir

Signal

Dir

SAMA5D3 Series [SUMMARY DATASHEET]
11121BS–ATARM–08-Mar-13

16

Table 4-1.

SAMA5D3 Pinout for 324-ball LFBGA Package (Continued)
Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal, Dir, PU, PD, HiZ, ST
O O O O O O I O, PD O, PD O, PD O, PD DHSDP DHSDM O, PD O, PD I I

Pin
G11 A5 B5 E9 B6 F9 R11 U14 V14 U12 V12 U10 V10 V15 T13 C5, C7, D14, T15, T7, U17, V7 A16, C9, N13, T14, T8, V17 D13, F14, G10, G13, H11 E14, F10, F13, F15, H14 P12, T16 J11, T17 G7, V11 L11, M4 E5, J7, N11, U7 V13 U13 R12 R10 P10 U11 T11

Power Rail
VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VBG VDDUTMII VDDUTMII VDDUTMII VDDUTMII VDDUTMII VDDUTMII VDDBU GNDBU

I/O Type
DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO VBG USBHS USBHS USBHS USBHS USBHS USBHS power supply ground

Signal
DDR_RAS DDR_CAS DDR_WE DDR_BA0 DDR_BA1 DDR_BA2 VBG HHSDPC HHSDMC HHSDPB HHSDMB HHSDPA HHSDMA VDDBU GNDBU

Dir
O O O O O O I I/O I/O I/O I/O I/O I/O I I

Signal

Dir

Signal

Dir

Signal

Dir

Signal

Dir

VDDCORE

power supply

VDDCORE

I

I

GNDCORE

ground

GNDCORE

I

I

VDDIODDR

power supply

VDDIODDR

I

I

GNDIODDR

ground

GNDIODDR

I

I

VDDIOM

power supply

VDDIOM

I

I

GNDIOM

ground

GNDIOM

I

I

VDDIOP0

power supply

VDDIOP0

I

I

VDDIOP1

power supply

VDDIOP1

I

I

GNDIOP

ground

GNDIOP

I

I

VDDUTMIC VDDUTMII GNDUTMI VDDPLLA GNDPLL VDDOSC GNDOSC

power supply power supply ground power supply ground power supply ground

VDDUTMIC VDDUTMII GNDUTMI VDDPLLA GNDPLL VDDOSC GNDOSC

I I I I I I I

I I I I I I I

SAMA5D3 Series [SUMMARY DATASHEET]
11121BS–ATARM–08-Mar-13

17

Table 4-1.

SAMA5D3 Pinout for 324-ball LFBGA Package (Continued)
Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal, Dir, PU, PD, HiZ, ST
I I I I I

Pin
L6 L4 L5 R3 P4

Power Rail
VDDANA GNDANA VDDANA VDDFUSE GNDFUSE

I/O Type
power supply ground power supply power supply ground

Signal
VDDANA GNDANA ADVREF VDDFUSE GNDFUSE

Dir
I I I I I

Signal

Dir

Signal

Dir

Signal

Dir

Signal

Dir

SAMA5D3 Series [SUMMARY DATASHEET]
11121BS–ATARM–08-Mar-13

18

5.

Mechanical Characteristics

Figure 5-1. 324-ball LFBGA Package Drawing

TITLE

Low Profile Fine Pitch Ball Grid Array

324

Table 5-1.

324-ball LFBGA Package Characteristics 3

Moisture Sensitivity Level Table 5-2. 400 Table 5-3. Package Reference

Device and 324-ball LFBGA Package Maximum Weight mg

JEDEC Drawing Reference JESD97 Classification Table 5-4. Ball Land Nominal Ball Diameter Solder Mask Opening Solder Mask Definition Solder Package Information

MO-275-KAAE-1 e8

0.350 mm ± 0.05 0.30 mm 0.275 mm ± 0.05 SMD SAC105

SAMA5D3 Series [SUMMARY DATASHEET]
11121BS–ATARM–08-Mar-13

19

6.

SAMA5D3 Ordering Information
SAMA5D3 Ordering Information Package BGA324 BGA324 Package Type Green Green Temperature Operating Range Industrial -40°C to 85°C Industrial -40°C to 85°C Industrial -40°C to 85°C Industrial -40°C to 85°C Ordering Code ATSAMA5D31A-CU ATSAMA5D33A-CU

Table 6-1.

ATSAMA5D34A-CU

BGA324

Green

ATSAMA5D35A-CU

BGA324

Green

SAMA5D3 Series [SUMMARY DATASHEET]
11121BS–ATARM–08-Mar-13

20

Revision History
In the tables that follow, the most recent version of the document appears first. “rfo” indicates changes requested during the document review and approval loop.

Table 6-2. Doc. Rev 11121BS Comments Removed “AT91SAM” from the document title. “Description”, added a cross-reference to Table 1-1 “SAMA5D3 Devices” in the last paragraph. Replaced “Cortex™” references with “Cortex®“ in “Description” and further on in the entire document. Section 5. “Mechanical Characteristics”, added “Nominal Ball Diameter” and “Solder” rows in Table 54 “Package Information”. Change Request Ref. rfo rfo rfo

Table 6-3. Doc. Rev 11121AS Comments First issue Change Request Ref.

SAMA5D3 Series [SUMMARY DATASHEET]
11121BS–ATARM–08-Mar-13

21

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