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On appeal to the Board, Micron argued that Bennett, while not disclosing

precharging, discloses “an operation code that instructs the receiving memory

device as to what function to perform.” (A1741-42; see also A1067.) Micron

further argued that it would have been obvious in 1990 to include both a write

request and an automatic precharge instruction in Bennett’s alleged operation code,

notwithstanding that neither Bennett nor any other cited reference actually

discloses this concept, and notwithstanding that the examiner had found precisely

the opposite.

Micron’s argument was not only contrary to the examiner’s findings, it was

also contrary to the only expert testimony proffered on this issue. Rambus’s

expert, Mr. Murphy, testified that in Bennett’s mainframe computer system, high-

level and low-level instructions would be generated by different parts of the

system. (See A1628[¶102] (“Because Bennett is not focused on memory devices,

it does not provide any disclosure about specific DRAM functions such as

precharging.”); A1629[¶105] (“[T]he localized operation of precharging DRAMs

Case: 13-1087 Document: 26-1 Page: 34 Filed: 04/01/2013


after the completion of a row access is not something that would be handled by the

processors in Bennett that generate requests to ‘memory’ as those processors

would not be aware of the page boundaries [i.e., which row particular data is stored

in] for the particular memory devices within the memory modules of Bennett.”).)

As Mr. Murphy further explained, an instruction to precharge is a low-level

instruction that would have been issued at the level of the memory controller for

the DRAMs alone, whereas a read or write instruction would have been initiated

by the CPU, translated by the memory controller, and then passed along separately

to the DRAMs. (A1628[¶102]; A1629[¶105].) Indeed, in both Wicklund and

Bowater, precharge instructions are generated by the memory controller, whereas

read and write instructions are generated by the CPU—a higher level processor.

Thus, as Mr. Murphy explained, if DRAMs were implemented in Bennett at all

(despite not being taught), instructions to write and precharge would have been two

different instructions, originated by two different parts of the system.

(A1628[¶102]; A1629[¶105]; see also A1611[¶50].) Micron submitted no

evidence rebutting this testimony of Mr. Murphy. Indeed, Micron submitted no

expert testimony at all during this reexamination proceeding.

At oral argument before the Board, Micron argued for the first time that

Bennett’s “read-modify-write” instruction constitutes a “multi-function” operation

code because it specifies to both read and write in one instruction. (A1012[ll.4-8].)

Case: 13-1087 Document: 26-1 Page: 35 Filed: 04/01/2013


But, as Rambus explained, that instruction does not contain two independent and

distinctly identifiable instructions. That is, when Bennett’s system is instructed to

“read-modify-write” to a memory address, as shown in Figure 34 of Bennett, it

reads the data in that memory address and writes a new value to that same address,

all based on a single instruction. (See A1067; A1345[91:13-23].) The read-

modify-write instruction has no independent portion that would allow it to, for

example, only read or only write. (Id.) Thus, as Rambus explained to the Board,

Bennett does not disclose a “bundled” operation code that gives two separate,

independent instructions, such as 1) whether to read or write, and 2) whether to

automatically precharge after the read/write operation has finished. (A1590-91.)

Moreover, the examiner had already considered the disclosure of a “read

modify write” instruction in Wicklund and other references and determined that

such an instruction does not render obvious the concept of including both a write

request and an automatic precharge instruction in a single operation code. (See,

e.g., A1496 (noting that Wicklund “discloses the assertion of read, write and read

modify write operation” (emphasis added); and A1513 (finding that Bennett in

view of Wicklund does not render claim 34 obvious).) Thus, Micron’s “read-

modify-write” argument had effectively already been considered and rejected by

the examiner.

Case: 13-1087 Document: 26-1 Page: 36 Filed: 04/01/2013


3. The Board’s Reversal of the Examiner’s Decision
Confirming Claim 34

In its decision on appeal, the Board’s analysis of “Bennett with Wicklund or

Bowater” spans a total of seven pages. (A29-35.) In those seven pages, the Board

never identifies any specific errors in the examiner’s underlying findings of fact

regarding the teachings of Bennett, Wicklund, or Bowater. (Id.)

For instance, the Board found that “Bennett discloses synchronous memory

chips” and further found that Bennett renders obvious the use of synchronous

DRAM chips. (A29.) Although Rambus disagrees with those findings, they are

nevertheless the same findings that the examiner made. (A1539.) Likewise, the

Board adopted wholesale the examiner’s finding that “Bennett discloses

controlling memory devices using operation codes.” (A30; A1512.)

The Board also found that “Bennett discloses multiple functions in a

memory write code,” referring specifically to the “read-modify-write code”

disclosed in Figure 34 of Bennett. (A27; A30.) Although the examiner had not

specifically addressed whether a read-modify-write (“RMW”) instruction

constitutes a single- or multiple-function operation code, he repeatedly discussed

the presence of RMW instructions in the prior art and concluded that they did not

disclose or render obvious the operation code recited in claim 34, i.e., one that

contains both a write instruction and an automatic precharge instruction. (See, e.g.,

A1496-97; A1504; A1540.)

Case: 13-1087 Document: 26-1 Page: 37 Filed: 04/01/2013


For instance, in discussing various combinations based on the Olson

reference (not appealed by Micron), the examiner discussed the read-modify-write

concept at length and rejected the notion that it inherently discloses the claimed

operation code:

Examiner agrees that it is further inherent with a RMW
[read-modify-write] request that the sense amplifiers
must be precharged “some time after a write operation”;
however, the claims are not broad to cover any arbitrary
time period. The claims specifically require that the
precharging is indicated in the same operation code that
specifies that the memory device must sample data to be
written and that the precharging is responsive to the
writing of data and not any other time period or

(A1504.) The examiner similarly found that the RMW instruction in Wicklund did

not render obvious an operation code that includes both a write instruction and an

automatic precharge instruction, as recited in claim 34. (A1513; 1540-41.) Thus,

the examiner was fully aware of RMW instructions and specifically rejected the

notion that they inherently disclose or render obvious the operation code of claim

34. On appeal, the Board did not point to any factual errors in these findings by

the examiner. (See A29-35.)

Regarding Wicklund, the Board likewise did not dispute the examiner’s

finding that any precharge instruction in Wicklund is issued as a separate

instruction after a read/write instruction has already been received. (A1498.)

Case: 13-1087 Document: 26-1 Page: 38 Filed: 04/01/2013


Despite accepting the examiner’s finding that Wicklund teaches only

separate instructions for writing and precharging, the Board found that “the

precharge and write functions (and their signals) are intimately coupled together . .

.” (A30.) Notwithstanding claim 34’s clear requirement that the write and

precharge instructions be given at the same time, the Board concluded that the

alleged “intimate[] coupl[ing]” of these two separate instructions in Wicklund

“support[s] the obviousness of the disputed limitations of claim 34 requiring the

signals to be in a single op code”—flatly contrary to the Examiner’s conclusion of

nonobviousness based on the same facts. (Id.)

The Board further reasoned that “Bennett discloses controlling memory

chips using multiple functions in a write code.” (Id.) Based on this, the Board

found “it would have been obvious to place the prior art coupled write and

precharge signals as described in the ’037 patent or Wicklund into Bennett’s op

code which carries related write signals together, so that the modified chips of

Bennett (DRAMs) can be precharged after a write function as was typically

required in DRAMs.” (A31.) The examiner, in contrast, had reached the opposite

conclusion (i.e., nonobviousness) based on the same facts.

Specifically, the examiner had looked at Wicklund’s disclosure of separate

write and precharge operations and concluded that this does not disclose or render

obvious the claimed operation code, even if combined with Bennett. The examiner

Case: 13-1087 Document: 26-1 Page: 39 Filed: 04/01/2013


noted that, in Wicklund’s normal mode, the device “precharges prior to the writing

of data that is at a new address and not automatically after data is written.”

(A1513 (emphases added).) Accordingly, because combining Wicklund with

Bennett still would not result in the recited features of claim 34 (i.e., an operation

code containing both a write instruction and an instruction to automatically

precharge after writing), the examiner concluded there was no prima facie case of

obviousness. (Id.)

The Board justified its departure from the examiner’s conclusion of

nonobviousness as follows:

The Examiner’s rationale for nonobviousness based on
these findings appears to be that row closing causes a
precharge on the current row, and then writing on the
next row occurs. (See [A1512-13].) While the findings
underlying the rationale appear to be factually supported
to an extent, the findings support obviousness, because
the rationale does not consider that the controller signals
a precharge on the DRAMs after writing in the normal
mode. Also, the controller signals a precharge after
shifting from the page mode to the normal mode and
writing to a new row pursuant to the shift.

(A32-33 (emphases in original).)

Two things are notable about the Board’s justification for reversing the

examiner’s finding of nonobviousness. First, the Board failed to indicate any error

in the examiner’s underlying findings, acknowledging instead that they “appear to

be factually supported to an extent” (without explaining what aspects, if any, are

Case: 13-1087 Document: 26-1 Page: 40 Filed: 04/01/2013


not factually supported). (Id.) Second, the Board cited no record evidence to

support its conclusion that the examiner’s findings “support obviousness” rather

than nonobviousness as the examiner found.

Moreover, contrary to the Board’s suggestion that the examiner failed to

consider certain facts, the examiner had in fact “consider[ed] that the controller

signals a precharge on the DRAMs after writing in the normal mode.” (Id.)

Specifically, the examiner had thoroughly reviewed this aspect of Wicklund and


Wicklund precharges based on a “next access.” Thus, at
best, Wicklund discloses that precharging occurs some
time after the writing of data, however this does not
disclose automatically precharging after writing data and
wherein this precharging instruction came within the
same operation code as the specifying of the sampling of
the data to be written request. Precharging based on a
next access is determined prior to memory access and
this determination does not instruct a memory device to
precharge automatically after data is written.

(A1498 (emphasis added).) The Board never challenged this factual finding by the

examiner as being incorrect.

The Board also concluded that Wicklund’s prediction algorithm suggests

that it would have been obvious to send the precharge signal with the write signal

in advance of closing the row. (A31.) The Board cited Wicklund’s disclosure of

closing a row after a number of page mode cycles to allow the sense amplifiers to

refresh their charges. (Id.) The Board concluded—directly contrary to the

Case: 13-1087 Document: 26-1 Page: 41 Filed: 04/01/2013


examiner’s conclusion—that “it also would have been obvious to send a precharge

signal with a write signal in an op code, before writing to the currently open

DRAM row in a page mode, but after determining, pursuant to a clock, that the

page mode time is about to expire, as Wicklund and Bowater suggest.” (Id.

(internal citations omitted).)

Again, though, the examiner had already considered this argument and

rejected it:

The claims require the automatic[ ] precharge of data
after the writing of data not the automatic[ ] precharge
after a counter has elapsed. In addition, assuming
arguendo that this is an automatic[ ] precharge that
occurs sometime after the writing of data, as noted above,
this indication is based on a counter and there is no
support for including this information along with [a]
write request since that would defeat the purpose of the
essential counter.

(A1501 (emphasis added).) The Board did not address or even cite to this finding

by the examiner in its decision on appeal.

On rehearing, the Board reiterated that “[t]he thrust of [its] Decision is that it

was widely known . . . that ‘prior art systems typically precharge DRAMs in the

non-page (normal) mode after a read or a write option.’” (A10.) It further

reiterated that “the Decision simply describes the two separate signals as coupled

in the prior art, because one follows the other in the normal read or write mode. As

such, putting the two related signals into the same operation code would have been

Case: 13-1087 Document: 26-1 Page: 42 Filed: 04/01/2013


obvious, since Bennett puts other related instructions in the same operation code

such as the read-modify-write operation code.” (A10-11.) Nowhere in its

rehearing decision did the Board point to any factual errors in the examiner’s

decision or explain factually why its own belief about what a person of ordinary

skill in the art would have considered obvious in 1990 was superior to the

examiner’s conclusion, given that both conclusions were based on the same facts.

4. The Board’s Determination That Bennett Rendered
Synchronous DRAMs Obvious in 1990

As explained above, the examiner construed a “synchronous dynamic

random access memory device” in claim 34 to mean “a synchronous DRAM chip,

hence requiring the memory to be on a single integrated chip.” (A1480 (emphasis

added); see also A1539.) In arriving at this construction, the examiner relied on

the ’037 patent’s specification, which makes clear that a synchronous DRAM

device is a single chip. (A1480-82 (citing A80[3:46-49].) Neither Micron nor the

Board has challenged this construction. Thus, regarding the “synchronous

DRAM” limitation, the question before the examiner and the Board was whether a

person of ordinary skill in the art in 1990, reading Bennett (which does not disclose

DRAMs) would have been motivated to connect a single DRAM chip directly to

Bennett’s primary bus and operate it synchronously.

It is undisputed that, while Bennett discloses many possible Users that can

be connected to the synchronous Versatile Bus, it does not disclose DRAMs, even

Case: 13-1087 Document: 26-1 Page: 43 Filed: 04/01/2013


though DRAMs existed at the time of Bennett’s filing. (A1628[¶100];

A1600[¶17].) Nevertheless, Micron argued that one of the disclosed Users in

Bennett—the so-called “large memory” User—could hypothetically be made up of

DRAMs, such that DRAMs are either “inherent or obvious.” (A1723 (“A person

having ordinary skill in the art would have understood the disclosure of the large

slower memory chips as an inherent or obvious description of DRAM based

devices incorporating the synchronous bus interface.”).)

The only DRAMs in use at the time of the claimed invention, however, were

asynchronous DRAMs. (A1601[¶20].) For instance, Wicklund and Bowater both

disclose conventional, asynchronous DRAM-based systems. The known way of

using DRAMs at that time was by connecting many DRAM chips to a secondary

bus having a dedicated memory controller. (A1625[¶92]; A1442; A1600-01[¶¶19-

20]; A1611[¶50]; A1654[¶41].) That whole group, i.e., the asynchronous DRAMs

along with the secondary bus and a memory controller (collectively called a

memory card or module), was then connected to a primary bus. (A1625[¶92].)

Indeed, an expert retained by Micron conceded in litigation that Bennett’s

“large memory,” to the extent it could be made up of DRAMs, “would have been

composed of multiple chips.” (A1686 (emphasis added).) And Samsung, the other

party that initially requested reexamination, made the same point in its request, i.e.,

that Bennett’s large memory “necessarily” would have been made of multiple

Case: 13-1087 Document: 26-1 Page: 44 Filed: 04/01/2013


chips. (A1842; see also A1625[¶92].) As Rambus explained to the Board, these

admissions are highly relevant because the examiner’s construction of

“synchronous dynamic random access memory device” specifically requires a

single chip that operates synchronously (as opposed to multiple asynchronous

chips that are connected to a memory controller that, in turn, is connected

synchronously to a primary bus). (A1586-87.)

Consistent with Micron’s and Samsung’s admissions, Bennett discloses that

the “large memory” includes up to 232

addresses of 32-bit words (A1625[¶92]

(citing A1347[95:58-59])), a number that even now cannot be contained on a

single DRAM chip. (See A1600[¶17]).

Moreover, as Mr. Murphy explained in an unrebutted declaration, Bennett’s

architecture would not permit individual DRAM chips to be connected directly to

Bennett’s primary bus. Specifically, Mr. Murphy testified that Bennett describes

the VBI as being designed to accept complex connections, containing many

different pins. (A1626-28[¶¶95-99].) If a single DRAM chip were to be connected

to the primary bus, it would have to contain all of those pins and the complex

circuitry that goes with them. (Id.) Mr. Murphy explained that DRAMs were

desirable specifically because they were small and cheap, and adding so many pins

and so much circuitry would have made each DRAM chip large and expensive and

therefore undesirable. (Id.; see also A1303[8:10-12].)

Case: 13-1087 Document: 26-1 Page: 45 Filed: 04/01/2013


Despite these facts, the examiner found that Bennett rendered synchronous

DRAMs obvious in 1990, based on its disclosure of “memory devices that

receive[ ] a clock.” (A1539.) Although none of the cited prior-art references

disclosed a synchronous DRAM, and despite Rambus’s evidence showing that no

one in 1990 (or now, for that matter) would have connected a single DRAM chip

directly to the synchronous primary bus in Bennett’s mainframe computer (akin to

connecting a home’s driveway directly to a 16-lane superhighway), the Board

nevertheless agreed with the examiner, finding that Bennett’s Figure 38 shows

“memories” connected to a synchronous bus, which the Board concluded could be

individual DRAM chips. (A26-27; A3-6.)

The following annotated figures from Wicklund (top) and Bennett (bottom)

summarize the Board’s holding on this point:

Case: 13-1087 Document: 26-1 Page: 46 Filed: 04/01/2013


As illustrated above, Rambus presented evidence (including admissions by

Micron and Samsung and the unrebutted testimony of Mr. Murphy) that, to the

extent DRAMs would be used at all in Bennett, they would have been incorporated

as shown above in red (see arrow pointing to Device D), i.e., an entire group of

asynchronous DRAMs and their controller would be attached to Bennett’s primary

bus. The Board found, however, that it would have been obvious in 1990 to follow

the blue path above (see arrow pointing to Device C) by attaching an individual

DRAM chip directly to the synchronous Versatile Bus of Bennett’s mainframe

computer system.

Case: 13-1087 Document: 26-1 Page: 47 Filed: 04/01/2013


The Board further addressed claim 34’s requirement that the synchronous

DRAM include a “delay time” between a write instruction and the corresponding

write operation. In finding this limitation obvious, the Board simply stated that

Rambus’s argument “reduces to [the] single chip argument.” (A7.) In other

words, according to the Board, if one were to modify Bennett to include a single

DRAM chip connected synchronously to the primary bus, that chip would

necessarily satisfy the claimed delay time limitation. But Bennett does not discuss

the claimed delay time at all. (A1628[¶100].) Nor did the Board point to any other

reference from which the delay-time limitation could be incorporated.

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