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Published by: sabatino123 on Apr 01, 2013
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The ’037 patent is generally directed to the structure, operation, and control

of Dynamic Random Access Memory devices or “DRAMs.” DRAMs store

information in memory cells, which are typically arranged in a two-dimensional

rectangular array. (A79[1:64-2:1]; A1600[¶15].) The array of cells includes

columns and rows, such that each cell can be accessed using a row/column address.

(A79[1:64-2:1]; A1600[¶15].) Each memory cell contains a capacitor for storing a

charge representing one bit of information; for example, a charged capacitor may

represent a “1,” while a capacitor with no charge would represent a “0.” (Id.) A

computer typically has many DRAMs controlled by a single memory controller.

(See, e.g., A84[11:18-26] (discussing a computer with 100 DRAMs).)

A central processing unit (“CPU”) can transfer information to or from a

memory address using a memory controller. (A1599-601[¶¶13-20].) The memory

controller accesses a designated row/column address in a given DRAM and

performs either a read or write operation. (Id.) To read information, the memory

controller sends instructions to sense the charge on the capacitor in that cell. To

write information, the memory controller sends instructions such that the charge on

the capacitor in that cell is changed to represent either a “0” or a “1.” (Id.)

Case: 13-1087 Document: 26-1 Page: 14 Filed: 04/01/2013


Information and control signals flowing between the CPU and the memory

controller or between the memory controller and the numerous DRAMs can travel

on one or more “buses,” each consisting of a series of wires or “lines” that connect

the devices. (A80[3:55-4:38].) Prior-art computers typically had a primary bus

that connected the CPU to the memory controller and a secondary bus that

connected the memory controller to the numerous DRAMs, as shown in the figure

below from the Wicklund reference (each set of two-way arrows represents a bus).

(A1442; see also A1600-01[¶¶19-20]; A1611[¶50]; A1625[¶92]; A1654[¶41].)

Generally, instructions traveling along the primary bus are system-wide

instructions such as instructions to access memory, while instructions traveling

along the secondary bus—between the memory controller and the individual

DRAMs—manage the detailed operations of the individual DRAMs in the memory

array. (A1629[¶105].)

Case: 13-1087 Document: 26-1 Page: 15 Filed: 04/01/2013


A focus of the ’037 patent is to make the memory system more efficient so

that data can be transferred faster than was possible in the prior art. (A81[5:36-

39].) This is accomplished, in part, by: (1) employing a synchronous memory

interface between the memory controller and the DRAMs, i.e., one that utilizes an

external clock signal to govern memory transactions with the individual DRAMs;

and (2) using multi-bit operation codes that include both read/write instructions

and instructions regarding “precharging.”

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