Introduction to VHDL

M. Balakrishnan Dept of Computer Science & Engg. I.I.T. Delhi
Chapter 6: Introduction to VHDL

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Domains of Description : Gajski‟s Y-Chart
Behavioral domain Structural domain

VHDL models

Physical domain Chapter 6: Introduction to VHDL

Level of abstraction

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VHDL Development
• US DoD initiated in 80‟s • Very High Speed ASIC Description Language • Initial objective was modeling only and thus only a simulator was envisaged • Subsequently tools for VHDL synthesis were developed
Chapter 6: Introduction to VHDL

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HDL Requirements • • • • Abstraction Modularity Concurrency Hierarchy Chapter 6: Introduction to VHDL 4 .

Abstraction VHDL supports description of components as well as systems at various levels of abstraction • Gate and component delays • Clock cycles • Abstract behavior without any notion of delays Chapter 6: Introduction to VHDL 5 .

Modularity • Every component in VHDL is referred to as an entity and has a clear interface • The interface is called an entity declaration • The “internals” of the component are referred to as the architecture declaration • There can be multiple architectures at even different levels of abstraction associated with the same entity Chapter 6: Introduction to VHDL 6 .

VHDL Example a AND b c Chapter 6: Introduction to VHDL 7 .

c : out bit).VHDL Description: AND gate entity AND2 is port (a. Chapter 6: Introduction to VHDL 8 . architecture beh of AND2 is begin c <= a and b. b: in bit . end AND2. end beh.

Concurrency in VHDL Descriptions signals signals process 1 process 2 Chapter 6: Introduction to VHDL process n 9 .

Concurrent and Sequential Computations • Processes are concurrent • Sequential activity within each process Nesting of statements : • Concurrent statements in a concurrent statement • Sequential statements in a concurrent statement • Sequential statements in a sequential statement Chapter 6: Introduction to VHDL 10 .

Hierarchy in VHDL C0 C1 C2 C3 C4 C5 C6 C7 S11 S12 S1 S2 S3 S4 S6 S7 S8 S9 S13 S10 S14 S5 Chapter 6: Introduction to VHDL 11 .

Modeling Styles in VHDL M.T. Delhi Chapter 6: Introduction to VHDL 12 . Balakrishnan Dept. Sci. of Comp. & Engg. I.I.

Modeling Styles • Semantic model of VHDL • Structural description • Data Flow description • Algorithmic description • RTL description Chapter 6: Introduction to VHDL 13 .

Modeling Choices in VHDL • Behavioral and Structural Domains – Several Levels of Abstraction • Multiple Styles of Behavioral Description: – Data Flow Style (concurrent) – Procedural Style (sequential) • Combinations. – special case of data flow style . e.g. variations and special cases of these.FSM described using case statement in a process Chapter 6: Introduction to VHDL 14 .FSM described using guarded blocks – special case of procedural style ..

Structural Description • Carries same information as a NET LIST • Net List = (Component instances) + (Nets) • Structural Description in VHDL = (Signals) + (Component instances + Port maps) • Many sophisticated features in VHDL to make it more versatile: * Variety of signal types * Generic components * Generate statements for creating arrays of component instances * Flexibility in binding components to design entities and architectures Chapter 6: Introduction to VHDL 15 .

Behavioral Description • Procedural (textual order => execution order) • Non-procedural (textual order NOT => execution order) • Sequential statements • Control constructs alter normal sequential flow • Concurrent statements • Data flow (or rather data dependency restricts concurrency) Called Behavioral description in VHDL Called Data flow description in VHDL 16 Chapter 6: Introduction to VHDL .

behavior -.structure -.nesting -.structure -.data flow -.error check 17 Chapter 6: Introduction to VHDL .behavior -. component instantiation generate statement block statement concurrent assertion stmt -.Concurrent Statements in VHDL • • • • • • • process statement concurrent procedure call concurrent signal assign.

Inputs Cout. -. Y. -. X Y Cin FullAdder Sum Cout Chapter 6: Introduction to VHDL 18 . Sum: out bit).Example: 1-bit Full Adder entity FullAdder is port (X.Outputs end FullAdder. Cin: in bit.

Cout <= (X and Y) or (X and Cin) or (Y and Cin) after 15 ns. Chapter 6: Introduction to VHDL 19 .Example: 1-bit Full Adder (contd.) Architecture Equations of FullAdder is begin -. end Equations.Concurrent Assignment Sum <= X xor Y xor Cin after 10 ns.

-. B: in bit_vector(3 downto 0). Ci: in bit. Co: out bit). -. Chapter 6: Introduction to VHDL 20 .Example: 4-bit Adder entity Adder4 is port (A.Outputs end Adder4.Inputs S: out bit_vector(3 downto 0).

S(3)). C(2). C(3). B(3). C(2). C(3). Sum: out bit). end Structure. Co.) Architecture Structure of Adder4 is Component FullAdder port (X. B(1). Chapter 6: Introduction to VHDL 21 . Ci. FA2: FullAdder port map (A(2). C(1). FA1: FullAdder port map (A(1). S(0)). B(0).Example: 4-bit Adder (contd. B(2). Cin: in bit. C(1). S(2)). FA3: FullAdder port map (A(3). Cout. S(1)). begin -.Instantiations FA0: FullAdder port map (A(0). signal C: bit_vector (3 downto 1). Y.

Example: 4-bit Comparator entity nibble_comparator is port (a. a_eq_b. a_lt_b : out bit).lt : in bit. b: in bit_vector (3 downto 0). gt.eq. Chapter 6: Introduction to VHDL 22 . a_gt_b. end nibble_comparator.

im(i*3-1). begin c0:comp1 port map(a(0). im(i*3+0). end nibble_comparator. signal im: bit_vector (0 to 8).im(6).Structural Description (contd.im(i*3-2). a_gt_b.lt : in bit. a_lt_b : out bit). Chapter 6: Introduction to VHDL 23 . for all : comp1 use entity work. end generate.bit_comparator(gate_level). im(1).im(8). c1toc2: for i in 1 to 2 generate c:comp1 port map(a(i).im(i*3+1).im(i*3-3).eq. b.b(i).im(i*3+2)).b(3). gt. c3: comp1 port map(a(3).im(7). im(0). end component. a_eq_b. eq. gt. a_eq_b. a_gt_b. a_lt_b). lt.b(0). im(2)).) architecture iterative of nibble_comparator is component comp1 port (a.

a_gt_b <= (gt and s) or (a and not b). architecture dataflow of comp1 is signal s : bit. end dataflow. end comp1. gt. b. a_lt_b <= (lt and s) or (not a and b).eq. a_gt_b.lt : in bit. begin s <= (a and b) or (not a and not b).Example: 1-bit Comparator (data flow) entity comp1 is port (a. Chapter 6: Introduction to VHDL 24 . a_eq_b. a_lt_b : out bit). a_eq_b <= eq and s.

Ashenden. PWS Publishing Co. Roth.. Chapter 2 (pp. Jr. Morgon Kaufmann Chapter 6: Introduction to VHDL 25 . 44 to 84) • The Designer‟s Guide to VHDL Peter J.References • Digital Systems Design Using VHDL Charles H.

Balakrishnan Dept. & Engg. I. Sci.T. of Comp.I. Delhi Chapter 6: Introduction to VHDL 26 .Behavioral Description in VHDL M.

Modeling Styles • Semantic model of VHDL • Structural description • Data Flow description • Algorithmic description • RTL description Chapter 6: Introduction to VHDL 27 .

behavior -.data flow -.error check 28 Chapter 6: Introduction to VHDL .structure -.structure -.behavior -. component instantiation generate statement block statement concurrent assertion stmt -.nesting -.Concurrent Statements in VHDL • • • • • • • process statement concurrent procedure call concurrent signal assign.

CLK: in bit. end DFF. QN: out bit := „1‟) .Example: D Flip-Flop entity DFF is port (D. D DFF CLK Chapter 6: Introduction to VHDL Q QN 29 . Q: out bit.

Example: DFF (contd. end Beh.) Architecture Beh of DFF is begin process (CLK) begin if (CLK = „1‟ then Q <= D after 10 ns. endif. QN <= not D after 10 ns. endprocess. Chapter 6: Introduction to VHDL 30 .

Concurrent Conditional Assignment: 4 to 1 Multiplexer y <= else else else x0 x1 x2 x3 x0 x1 x2 x3 when when when when y sel = 0 sel = 1 sel = 2 sel = 3 sel Chapter 6: Introduction to VHDL 31 .

CASE Statement: 4 to 1 Multiplexer Case sel is when 0 => when 1 => when 2 => when 3 => end case y <= x0 y <= x1 y <= x2 y <= x3 x0 x1 x2 x3 y Chapter 6: Introduction to VHDL 32 .

variable var3. sum <= var1. var1 := var3. begin process variable var1: integer:= 1. begin wait on trigger. end var. var2: integer:= 2.Variables And Signals Architecture var of dummy is signal trigger. sum: integer := 0. Chapter 6: Introduction to VHDL 33 . var3 := var1 + var2. end process.

Variables And Signals Architecture sig of dummy is signal trigger. sig2: integer:= 2. begin process begin wait on trigger. sig1 <= sig3. sum: integer := 0. end process. end sig. signal sig3. Chapter 6: Introduction to VHDL 34 . signal sig1: integer:= 1. sum <= sig1. sig3 <= sig1 + sig2.

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