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** Models for representing sequential circuits
**

Abstraction of sequential elements Finite state machines and their state diagrams Inputs/outputs Mealy, Moore, and synchronous Mealy machines

** Finite state machine design procedure
**

Verilog specification Deriving state diagram Deriving state transition table Determining next state and output functions Implementing combinational logic

CS 150 - Fall 2005 – Lec #7: Sequential Implementation – 1

**Mealy vs. Moore Machines
**

Moore: outputs depend on current state only Mealy: outputs depend on current state and inputs Ant brain is a Moore Machine We could have specified a Mealy FSM

Output does not react immediately to input change Outputs have immediate reaction to inputs As inputs change, so does next state, doesn’t commit until clocking event

L’ R / TL, F L / TL A react right away to leaving the wall L’ R’ / TR, F

CS 150 - Fall 2005 – Lec #7: Sequential Implementation – 2

Specifying Outputs for a Moore Machine Output is only function of state Specify in state bubble in state diagram Example: sequence detector for 01 or 10 0 B/0 0 reset 0 A/0 1 C/0 1 1 0 E/1 1 0 1 D/1 reset 1 0 0 0 0 0 0 0 0 0 0 input – 0 1 0 1 0 1 0 1 0 1 current state – A A B B C C D D E E next state A B C B D E C E C B D output 0 0 0 0 0 0 1 1 1 1 CS 150 .Fall 2005 – Lec #7: Sequential Implementation – 4 0/1 1/1 reset 1 0 0 0 0 0 0 input – 0 1 0 1 0 1 current state – A A B B C C next state A B C B C B C output 0 0 0 0 1 1 0 .Fall 2005 – Lec #7: Sequential Implementation – 3 Specifying Outputs for a Mealy Machine Output is function of state and inputs Specify output on transition arc between states Example: sequence detector for 01 or 10 0/0 B 0/0 reset/0 A 1/0 C 1/0 CS 150 .

more logic may be necessary to decode state into outputs – more gate delays after Combinational logic for Next State inputs reg Logic for outputs outputs Logic for outputs Combinational logic for Next State outputs reg Mealy Machines react faster to inputs inputs state feedback state feedback CS 150 . input change can cause output change as soon as logic is done – a big problem when two machines are interconnected – asynchronous feedback React in same cycle – don't need to wait for clock In Moore machines.Comparison of Mealy and Moore Machines Mealy Machines tend to have less states Moore Machines are safer to use Different outputs on arcs (n^2) rather than states (n) Outputs change at clock edge (always one cycle later) In Mealy machines.1 Mealy or Moore? A B clock out D Q Q A D Q Q out B clock D Q Q CS 150 .B = 0.Fall 2005 – Lec #7: Sequential Implementation – 6 .Fall 2005 – Lec #7: Sequential Implementation – 5 Mealy and Moore Examples Recognize A.

0 then 0.B = 1.Mealy and Moore Examples (cont’d) Recognize A.Fall 2005 – Lec #7: Sequential Implementation – 7 Registered Mealy Machine (Really Moore) Synchronous (or registered) Mealy Machine Registered state AND outputs Avoids ‘glitchy’ outputs Easy to implement in programmable logic Moore Machine with no output decoding Outputs computed on transition to next state rather than after entering View outputs as expanded state vector Inputs output logic next state logic Current State CS 150 .1 Mealy or Moore? A D Q Q B D clock Q Q out out A D Q Q B D Q Q clock D D Q Q Q Q CS 150 .Fall 2005 – Lec #7: Sequential Implementation – 8 Outputs .

two1s = 2. if (in) next_state = two1s.Fall 2005 – Lec #7: Sequential Implementation – 9 Moore Verilog FSM (cont’d) always @(in or state) case (state) zero: begin // last input was a zero out = 0. input clk. if (in) next_state = one1. end two1s: begin // we've seen at least 2 ones out = 1. reg [1:0] state. reset.Reduce 1s Example Change the first 1 to 0 in each string of 1’s Example Moore machine implementation // State assignment parameter zero = 0. 0 0 zero [0] 1 one1 [0] 1 two1s [1] 1 0 CS 150 . // state register reg [1:0] next_state. one1 = 1. in. else next_state = zero. reg out. next_state = zero. module reduce (out. else next_state = zero.Verilog FSM . reset. endcase 0 zero [0] 1 0 one1 [0] 1 two1s [1] 1 0 include all signals that are input to state and output equations CS 150 . if (in) next_state = two1s. end default: begin // in case we reach a bad state out = 0. clk. end one1: begin // we've seen one 1 out = 0.Fall 2005 – Lec #7: Sequential Implementation – 10 . in). else next_state = zero. output out.

end endcase always @(posedge clk) if (reset) state <= zero.Fall 2005 – Lec #7: Sequential Implementation – 11 Mealy Verilog FSM for Reduce-1s Example module reduce (clk. end else begin next_state = zero. out = 1. else next_state = zero. input clk. else state <= next_state.Moore Verilog FSM (cont’d) // Implement the state register always @(posedge clk) if (reset) state <= zero. in. // state register reg next_state. else state <= next_state. out = 0. one = 1. reg out. endmodule 0 0 zero [0] 1 one1 [0] 1 two1s [1] 1 0 CS 150 . output out. end one: // we've seen one 1 if (in) begin next_state = one. reset. always @(in or state) case (state) zero: begin // last input was a zero if (in) next_state = one. reset. out). parameter zero = 0. endmodule CS 150 .Fall 2005 – Lec #7: Sequential Implementation – 12 0/0 zero 0/0 1/0 one1 1/1 7 . in. out = 0. reg state.

in. end else begin next_state = zero. reg state. 125 Cory Hall Five Quiz-like Questions -. Today. they should contain all the information you need to answer the question correctly No calculators or other gadgets are necessary! Don’t bring them! No blue books! All work on the sheets handed out! Do bring pencil and eraser please! If you like to unstaple the exam pages. out). end one: // we've seen one 1 if (in) begin next_state = one. reset. parameter zero = 0. one = 1.Fall 2005 – Lec #7: Sequential Implementation – 13 0/0 zero 0/0 1/0 one1 1/1 7 Announcements Review Session.Synchronous Mealy Verilog FSM for Reduce-1s Example module reduce (clk. output out. in. reset. else next_state = zero. always @(in or state) case (state) zero: begin // last input was a zero if (in) next_state = one. out <= next_out. input clk. end else begin state <= next_state. out <= 0.Please Read Them Carefully! They are not intended to be tricky. 1-2:30 PM. next_out = 1. reg next_out. 5-6 PM. end endcase always @(posedge clk) if (reset) begin state <= zero. then bring a stapler with you! Write your name and student ID on EVERY page in case they get separated -it has happened! Don’t forget your two-sided 8. end endmodule CS 150 . 125 Cory Hall Examination. Wednesday. // state register reg next_state. reg out. next_out = 0.Fall 2005 – Lec #7: Sequential Implementation – 14 .5” x 11” crib sheet! CS 150 . next_out = 0.

PLA structures (minimum unique terms).6). 7. 6.3) CS 150 . nickels No change N Coin Sensor D Reset Vending Machine FSM Open Release Mechanism Clock CS 150 . ROMs.2.1. master/slave concept Basic Finite State Machines: Representations (state diagrams. transparent vs. Muxes. 1-2:30 PM. (Simplified) Xilinx CLB Sequential logic: R-S latches.1. 125 Cory Hall Topics covered through last Wednesday Combinational logic: design and optimization (K-maps up to and including 6 variables) Implementation: Simple gates (minimum wires and gates).Announcements Examination.1. 6. Decoders.Fall 2005 – Lec #7: Sequential Implementation – 15 Example: Vending Machine Release item after 15 cents are deposited Single coin slot for dimes. Moore vs. flip-flops.5). 4 (4.1. 4. 2. 3 K&B: Chapters 1. Counters Structural and Behavioral Verilog for combinational and sequential logic Labs 1. 7 (7.1. 6 (6. transition tables). 2 (2. 4.3).2. 7.3). Shifters.Fall 2005 – Lec #7: Sequential Implementation – 16 . edge-triggered behavior. 3.2. 3 (3.1-2. Mealy Machines. Registers. Wednesday.

Fall 2005 – Lec #7: Sequential Implementation – 18 . nickel two dimes S1 N S3 N S7 [open] D S4 [open] N S5 [open] S2 D S6 [open] N S0 D Reset Draw state diagram: Inputs: N.Fall 2005 – Lec #7: Sequential Implementation – 17 Example: Vending Machine (cont’d) Minimize number of states . dime dime.reuse states whenever possible Reset present state 0¢ inputs D N 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 – – next state 0¢ 5¢ 10¢ – 5¢ 10¢ 15¢ – 10¢ 15¢ 15¢ – 15¢ output open 0 0 0 – 0 0 0 – 0 0 0 – 1 0¢ N 5¢ N D 10¢ N+D 15¢ [open] 15¢ D 10¢ 5¢ symbolic state table CS 150 . reset Output: open chute Assume N and D asserted for one cycle Each state has a self loop for N = D = 0 (no coin) Assumptions: CS 150 . D.Example: Vending Machine (cont’d) Suitable Abstract Representation Tabulate typical input sequences: 3 nickels nickel.

Fall 2005 – Lec #7: Sequential Implementation – 19 Example: Vending Machine (cont’d) Mapping to Logic D1 Q1 0 0 1 1 0 1 1 1 D X X X X 1 1 1 1 Q0 N D D0 Q1 0 1 1 0 1 0 1 1 X X X X 0 1 1 1 Q0 N D Q1 Open 0 0 1 0 0 0 1 0 X X X X 0 0 1 0 Q0 N D1 = Q1 + D + Q0 N D0 = Q0’ N + Q0 N’ + Q1 N + Q1 D OPEN = Q1 Q0 CS 150 .Example: Vending Machine (cont’d) Uniquely Encode States present state inputs Q1 Q0 D N 0 0 0 0 0 1 1 0 1 1 0 1 0 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 1 1 1 1 – – next D1 0 0 1 – 0 1 1 – 1 1 1 – 1 state D0 0 1 0 – 1 0 1 – 0 1 1 – 1 output open 0 0 0 – 0 0 0 – 0 0 0 – 1 CS 150 .Fall 2005 – Lec #7: Sequential Implementation – 20 .

1 0 0 output D0 open 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D0 = Q0 D’ N’ D1 = Q0 N + Q1 D’ N’ D2 = Q0 D + Q1 N + Q2 D’ N’ D3 = Q1 D + Q2 D + Q2 N + Q3 OPEN = Q3 0 0 1 0 0 1 0 0 1 0 0 0 CS 150 .0 1 0 1 0 0 1 0 0 .Example: Vending Machine (cont’d) One-hot Encoding present state Q3 Q2 Q1 Q0 0 0 0 1 inputs D N 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 ..0 0 1 0 1 0 1 0 0 ...next state D3 D2 D1 0 0 0 0 0 1 0 1 0 .Fall 2005 – Lec #7: Sequential Implementation – 22 .Fall 2005 – Lec #7: Sequential Implementation – 21 Equivalent Mealy and Moore State Diagrams Moore machine outputs associated with state Reset N’ D’ + Reset 0¢ [0] N D 5¢ [0] N D 10¢ [0] N+D 15¢ [1] Reset’ N’ D’ D/1 N+D/1 15¢ Reset’/1 N’ D’ D/0 N/0 10¢ N’ D’/0 Mealy machine outputs associated with transitions Reset/0 (N’ D’ + Reset)/0 N’ D’ N/0 0¢ N’ D’/0 5¢ N’ D’/0 CS 150 .

Reset. open <= next_open. D 10¢ [0] N+D 15¢ [1] N’ D’ Reset’ always @(posedge clk) if (Reset || (!N && !D)) state <= zero. Reset. = zero. end end … endcase Reset/0 (N’ D’ + Reset)/0 0¢ N/0 D/0 N/0 D/1 N+D/1 15¢ 10¢ 5¢ N’ D’/0 N’ D’/0 N’ D’/0 Reset’/1 always @(posedge clk) if (Reset || (!N && !D)) begin state <= zero. parameter zero = 0. // state register reg next_state.Fall 2005 – Lec #7: Sequential Implementation – 24 7 . reg open. output open. D. open <= 0. fifteen = 3. always @(N or D or state) case (state) zero: begin if (D) begin next_state = ten. end endcase Reset N’ D’ + Reset 0¢ [0] N N’ D’ = five. reg open. N. D). input Clk. N. five = 1. D). end … fifteen: begin if (!Reset) next_state else next_state open = 1. end else if (N) begin next_state = five. Reset. = ten.Moore Verilog FSM for Vending Machine module vending (open. always @(N or D or state) case (state) zero: begin if (D) next_state else if (N) next_state else next_state open = 0. ten = 2. D. reg next_open. next_open = 0. next_open = 0. Clk. Reset. ten = 2. endmodule CS 150 . output open. Clk. D 5¢ [0] N N’ D’ = fifteen. = zero. N. parameter zero = 0. reg state. end else begin next_state = zero.Fall 2005 – Lec #7: Sequential Implementation – 23 7 Mealy Verilog FSM for Vending Machine module vending (open. end endmodule CS 150 . next_open = 0. five = 1. reg state. N. else state <= next_state. input Clk. // state register reg next_state. end else begin state <= next_state. fifteen = 3.

Example: Traffic Light Controller A busy highway is intersected by a little used farmroad Detectors C sense the presence of cars waiting on the farmroad Assume you have an interval timer that generates: with no car on farmroad. farm lights transition from Green to Yellow to Red.Fall 2005 – Lec #7: Sequential Implementation – 26 . highway lights go from Green to Yellow to Red. TS is to be used for timing yellow lights and TL for green lights CS 150 . allowing the farmroad lights to become green these stay green only as long as a farmroad car is detected but never longer than a set interval when these are met.Fall 2005 – Lec #7: Sequential Implementation – 25 Example: Traffic Light Controller (cont’d) Highway/farm road intersection farm road car sensors highway CS 150 . highway gets at least a set interval as green a short time pulse (TS) and a long time pulse (TL). allowing highway to return to green even if farmroad vehicles are waiting. in response to a set (ST) signal. light remain green in highway direction if vehicle on farmroad.

HR assert green/yellow/red highway lights FG. HY.Example: Traffic Light Controller (cont’d) Tabulation of Inputs and Outputs inputs reset C TS TL description place FSM in initial state detect vehicle on the farm road short time interval expired long time interval expired outputs description HG. FY.Fall 2005 – Lec #7: Sequential Implementation – 27 Example: Traffic Light Controller (cont’d) State Diagram (TL•C)' S0 TL•C / ST S0: HG S1: HY S2: FG S3: FY TS / ST S2 TL+C' / ST TS' S1 TL+C / ST S3 TS' TS / ST Reset (TL+C')' CS 150 .Fall 2005 – Lec #7: Sequential Implementation – 28 . FR assert green/yellow/red highway lights ST start timing a short or long interval Tabulation of unique states – some light configurations imply others state S0 S1 S2 S3 description highway green (farm road red) highway yellow (farm road red) farm road green (highway red) farm road yellow (highway red) CS 150 .

S3 = 3. ST <= 0.Fall 2005 – Lec #7: Sequential Implementation – 29 Traffic Light Controller Verilog module traffic (ST. parameter S0 = 0. C. end endmodule (TL+C')' CS 150 . Red = 10) Outputs ST H 0 Green 0 Green 1 Green 0 Yellow 1 Yellow 0 Red 1 Red 1 Red 0 Red 1 Red FY = 10 FY = 11 FY = 1000 F Red Red Red Red Red Green Green Green Yellow Yellow (one-hot) CS 150 . reg state. next_ST = 0. Reset. reg next_ST. ST <= next_ST. end … endcase (TL•C)' S0 TL•C TL+C / ST TS' S1 Reset TS / ST S3 TS' TS / ST S2 TL+C' / ST always @(posedge Clk) if (Reset) begin state <= S0. TS). TL. Clk.Example: Traffic Light Controller (cont’d) Generate state table with symbolic states Consider state assignments Inputs C TL 0 – – 0 1 1 – – – – 1 0 0 – – 1 – – – – SA1: SA2: SA3: TS – – – 0 1 – – – 0 1 Present State HG HG HG HY HY FG FG FG FY FY HG = 00 HG = 00 HG = 0001 HY = 01 HY = 10 HY = 0010 Next State HG HG HY HY FG FG FY FY FY HG FG = 11 FG = 01 FG = 0100 output encoding – similar problem to state assignment (Green = 00. input Clk. S2 = 2. end else begin state <= next_state. S1 = 1. always @(C or TL or TS or state) case (state) S0: if (!(TL && C)) begin next_state = S0. else if (TL || C) begin next_state = S1. output ST. TS. TL. Reset. reg ST. C. Yellow = 01. next_ST = 1.Fall 2005 – Lec #7: Sequential Implementation – 30 . reg next_state.

Fall 2005 – Lec #7: Sequential Implementation – 32 .Logic for Different State Assignments SA1 NS1 = C•TL'•PS1•PS0 + TS•PS1'•PS0 + TS•PS1•PS0' + C'•PS1•PS0 + TL•PS1•PS0 NS0 = C•TL•PS1'•PS0' + C•TL'•PS1•PS0 + PS1'•PS0 ST = C•TL•PS1'•PS0' + TS•PS1'•PS0 + TS•PS1•PS0' + C'•PS1•PS0 + TL•PS1•PS0 H1 = PS1 H0 = PS1'•PS0 F1 = PS1' F0 = PS1•PS0' NS1 = C•TL•PS1' + TS'•PS1 + C'•PS1'•PS0 NS0 = TS•PS1•PS0' + PS1'•PS0 + TS'•PS1•PS0 ST = C•TL•PS1' + C'•PS1'•PS0 + TS•PS1 H1 = PS0 H0 = PS1•PS0' F1 = PS0' F0 = PS1•PS0 NS3 = C'•PS2 + TL•PS2 + TS'•PS3 NS1 = C•TL•PS0 + TS'•PS1 NS2 = TS•PS1 + C•TL'•PS2 NS0 = C'•PS0 + TL'•PS0 + TS•PS3 SA2 SA3 ST = C•TL•PS0 + TS•PS1 + C'•PS2 + TL•PS2 + TS•PS3 H1 = PS3 + PS2 H0 = PS1 F1 = PS1 + PS0 F0 = PS3 CS 150 .Fall 2005 – Lec #7: Sequential Implementation – 31 Vending Machine Example Revisted (PLD mapping) D0 D1 OPEN = reset'(Q0'N + Q0N' + Q1N + Q1D) = reset'(Q1 + D + Q0N) = Q1Q0 CLK Q0 Seq DQ N DQ Q1 Seq D DQ Open Com Reset CS 150 .

Vending Machine (cont’d) OPEN = Q1Q0 creates a combinational delay after Q1 and Q0 change This can be corrected by retiming.Fall 2005 – Lec #7: Sequential Implementation – 34 . move flip-flops and logic through each other to improve delay OPEN = reset'(Q1 + D + Q0N)(Q0'N + Q0N' + Q1N + Q1D) = reset'(Q1Q0N' + Q1N + Q1D + Q0'ND + Q0N'D) Implementation now looks like a synchronous Mealy machine Common for programmable devices to have FF at end of logic CS 150 .. i.e.Fall 2005 – Lec #7: Sequential Implementation – 33 Vending Machine (Retimed PLD Mapping) OPEN = reset'(Q1Q0N' + Q1N + Q1D + Q0'ND + Q0N'D) CLK Q0 Seq DQ N DQ Q1 Seq D OPEN DQ Open Seq Reset CS 150 .

and synchronous Mealy machines Finite state machine design procedure Verilog specification Deriving state diagram Deriving state transition table Determining next state and output functions Implementing combinational logic CS 150 . Moore.Fall 2005 – Lec #7: Sequential Implementation – 35 .Sequential Logic Implementation Summary Models for representing sequential circuits Abstraction of sequential elements Finite state machines and their state diagrams Inputs/outputs Mealy.

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