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Lp trnh b nh thi (TIMER)

Gii thiu b nh thi


1. Cc thanh ghi ca b nh thi - Timer 0: TH0, TL0 - Timer 1: TH1, TL1 - Cc thanh ghi trng thi v ci t ch hot ng cho cc b nh thi: + TCON: iu khin + TMOD: Chn ch

V tr ca cc b nh thi trong s khi ca chip 89X51/52


Cc b nh thi

V TR CC THANH GHI CA B NH THI TRONG VNG NH C BIT- SFR

Thanh ghi TMOD: Timer Mode Chn ch hot ng


TMOD D7 D6 D5 D4 D3 D2 D1 D0

GATE

M1

GATE

M1

C/T

M0

C/T

M0

Chn ch hot ng cho TIMER1

Chn ch hot ng cho TIMER0

Bit M0, M1 ca thanh ghi TMOD


TMOD GATE C/T M1 M0 GATE C/T M1 M0

M1

M0

Ch

M t Ch nh thi 13 bit Ch nh thi 16 bit Ch t ng np li 8-bit Ch nh thi chia x

0 0 1 1

0 1 0 1

0 1 2 3

Thanh ghi TCON Timer/Counter Control Register


TCON

D7

D6

D5

D4

D3

D2

D1

D0

TF1

TF0

IE1

IE0

TR1
C ngt ca Timer1 C ngt ca Timer0

TR0
C ngt ngoi 1

IT1
C ngt ngoi 0

IT0

Ch hot ng ca Timer
- Ch 0: Ch nh thi 13 bit - Ch 1: Ch nh thi 16 bit
- THx, TLx cha gi tr m hin ti ca b nh thi

- Ch 2: Ch t np li 8-bit
- Byte thp gi gi tr m hin ti - Byte cao gi gi tr np li

- Ch 3: Ch nh thi chia x

Lp trnh cho b nh thi Timer 0


V d 1: lp trnh cho b nh thi 0 hot ng ch 1, 16 bit, c thi gian trn l 500us (s dng thch 12Mhz). Bc 1: Chn ch hot ng cho Timer 0
TMOD = 00000001B (0x01)

Bc 2: Np gi tr trn cho cc thanh ghi TH0, TL0


V b nh thi m ln 1 n v sau mi chu k my nn b nh thi s trn sau 500 chu k my khi np vo TH0, TL0 gi tr bng 65536 500 = 65036 tng ng 0FE0Ch TH0 = 0xFE; // MOV TH0, #0FEh TL0 = 0X0C; // MOV TL0, #0Ch

- Bc 3: Khi ng b nh thi T0
TF0 = 0; // (CLR TF0) Xa c trn TR0 = 1; // (SETB TR0) Khi ng b nh thi

- Bc 4: Ch b nh thi trn
while(!TF0) continue; // JNB TF0, $

- Bc 5: Nu tip tc mun s dng b nh thi: Dng b nh thi (TR0 = 0), np li gi tr cho TH0, TL0, khi ng li (TR0 = 1). TMOD GATE C/T M1 M0 GATE C/T M1 M0

Chng trnh hon chnh v d 1


C
TMOD = 00000001B TH0 = 0xFE; TL0 = 0x0C; TF0 = 0; // Xa c trn // Khi ng b nh thi TR0 = 1; // Ch c trn bt 1 while(!TF0) continue; // Dng b nh thi TR0 = 0; // Np li gi tr TH0 = 0xFE; TL0 = 0x0C; ... // Khi ng b nh thi TR0 = 1;

ASM
MOV TMOD, #00000001B MOV TH0, #0FEh MOV TL0, #0Ch CLR TF0; Xa c trn ;Khi ng b nh thi SETB TR1 ; Ch c trn bt 1 JNB TF0, $ ; Dng b nh thi CLR TR0 ; Np li gi tr MOV TH0, #0FEh; MOV TL0, #0Ch; ... // Khi ng b nh thi SETB TR0

Lp trnh cho b nh thi Timer 0 (ti p)


V d 2: lp trnh cho b nh thi 0 hot ng ch 2, 8-bit t np li, c thi gian trn l 200us (s dng thch 12Mhz). Bc 1: Chn ch hot ng cho Timer 0
TMOD = 00000010B (0x02)

Bc 2: Np gi tr trn cho cc thanh ghi TH0, TL0


ch 2, thanh ghi TH0 s gi gi tr np li, vy TH0 = 255 - 200; // MOV TH0, #55 TL0 = 255 - 200; // MOV TL0, #55

- Bc 3: Khi ng b nh thi T0
+ TF0 = 0; // (CLR TF0) Xa c trn + TR0 = 1; // (SETB TR0) Khi ng b nh thi

- Bc 4: Ch b nh thi trn
- while(!TF0) continue; // JNB TF0, $

- Bc 5: Xa c trn (TF0 = 0), tip tc i c trn bt 1 do thanh ghi TL0 t ng c np li.

Chng trnh hon chnh v d 2


C
TMOD = 0x02; TH0 = 55; TL0 = 55; TF0 = 0; // Xa c trn // Khi ng b nh thi TR0 = 1; // Ch c trn bt 1 while(!TF0) continue; // Dng b nh thi TR0 = 0; ... // Khi ng b nh thi TR0 = 1;

ASM
MOV TMOD, #00000010B MOV TH0, #55 MOV TL0, #55 CLR TF0; Xa c trn ;Khi ng b nh thi SETB TR1 ; Ch c trn bt 1 JNB TF0, $ ; Dng b nh thi CLR TR0 ... // Khi ng b nh thi SETB TR0

To tr s dng Timer
MAIN: MOV MOV MOV AGAIN: CPL CALL JMP TMOD, #00000010B TH0, #55 TL0, #55 P1.0 DELAY AGAIN void main() { TMOD = 0x02; while(1) { P1_0 = !P1_0; delay(55); } void delay(unsigned char us){ TH0 = us; TL0 = us; TF0 = 0 ; Xa c trn ;Khi ng b nh thi TR1 = 1; ; Ch c trn bt 1 while(!TF0) continue; ; Dng b nh thi TR0 = 0; }

DELAY: CLR TF0; Xa c trn ;Khi ng b nh thi SETB TR1 ; Ch c trn bt 1 JNB TF0, $ ; Dng b nh thi CLR TR0 RET

NGT
Gii thiu ngt Cc loi ngt v bng vector ngt:
Reset h thng Ngt ngoi 0 Timer 0 Ngt ngoi 1 Timer 1 Cng ni tip Timer 2 RST a ch vector ngt IE0 TF0 IE1 TF1 RI hoc TI TF2 hoc EXF2 0000H 0003H 000BH 0013H 001BH 0023H 002BH

Cc thanh ghi cu hnh ngt Lp trnh ngt

X l ca CPU i vi 1 ngt
Khi mt ngt xut hin v c CPU chp nhn, chng trnh chnh b ngt. Cc thao tc sau y xy ra: - Hon tt vic thc thi lnh hin hnh - Ct b m chng trnh (PC) vo stack - Trng thi ca ngt hin hnh c lu gi li - B m chng trnh PC s np a ch ca chng trnh con phc v ngt v i thc hin. - Thc hin xong s quay v chng trnh chnh ti v tr n b ngt v thc hin tip chng trnh chnh.

Thanh ghi cho php ngt IE (Interrupt Enable Register)


IE D7 D6 D5 D4 D3 D2 D1 D0

EA

ET2

ET1

ET0

Cho php ngt ton cc Cho php ngt do Timer 2 Khng s dng

ES
Cho php ngt do Timer 1

EX1
Cho php ngt do Timer 0 Cho php ngt ngoi 1

EX0

Cho php ngt do port ni tip

Cho php ngt ngoi 0

Thanh ghi u tin ngt IP (Interrupt Priority Register)


IP D7 D6 D5 D4 D3 D2 D1 D0

Khng s dng Khng s dng

PT2

PT1

PT0

PS
u tin ngt cho Timer 2 u tin ngt cho Timer 1

PX1
u tin ngt cho Timer 0 u tin ngt ngoi 1

PX0

u tin ngt do port ni tip

u tin ngt ngoi 0

LP TRNH NGT
1. Lp trnh vi ngt timer
Timer 0 Timer 1

2. Lp trnh vi ngt ngoi


Ngt ngoi 0 Ngt ngoi 1 Ngt ngoi theo sn xung v theo mc 0

3. u tin ngt
Th t u tin thc hin cc ngt Lp trnh theo i u tin cc ngt

1. Lp trnh ngt timer


IE Interrupt Enable Register

EA

ET2

ES

ET1

EX1

ET0

EX0

Bc 1: Chn ch hot ng ca timer nh phn lp trnh cho timer Bc 2: Cho php ngt:
Cho php ngt do timer
ET0 = 1; // Nu s dng ngt timer 0 ET1 = 1; // Nu s dng ngt timer 1

Cho php ng t ton c c


EA = 1; // Bt buc phi c khi s dng bt c ngt no.

Bc 3: Vit chng trnh phc v ngt Timer.


Chng trnh phc v ngt do timer c t cc vector ngt 000Bh (Timer 0) 001Bh (Timer 1). Cc chng trnh con phc v ngt cng ging nh cc chng trnh con khc, tuy nhin n c kt thc bng lnh RETI (Return from Interrupt) thay v lnh RET.

V d 1: Vit chng trnh nhy LED ni chn P1.0 vi chu k 500us s dng ngt timer 0. S dng thch anh 12Mhz.

ASM
ORG 0000H LJMP MAIN ORG 001BH LJMP T0_ISR ORG 0030H MAIN: MOV TMOD, #00000010B; Ch 2 MOV TH0, #55 MOV TL0, #55 CLR TF0; Xa c trn SETB ET0 SETB EA SETB TR0; Khi ng Timer 0 JMP $ T0_ISR: CPL P1.0 RETI

C
void main() { TMOD = 0x02; // Timer 0 ch 2 TH0 = 5; TL0 = 5; // Np gi tr cho TH0, TF0 = 0; // Xa c trn ET0 = 1; EA =1; TR0 = 1; // Khi ng Timer 0 while(1) continue; } void T0_ISR() interrupt 1 { P1_0 = !P1_0; }

V d 2: Vit chng trnh to xung vung chn P1.0 vi tn s 500Hz s dng ngt timer 1. Thch anh 12Mhz. ASM
ORG 0000H LJMP MAIN ORG 000BH LJMP T1_ISR ORG 0030H MAIN: MOV TMOD, #00010000B;Timer 1 ch 1 MOV TH1, #HIGH(-1000) MOV TL1, #LOW(-1000) CLR TF1; Xa c trn SETB ET1 SETB EA SETB TR1; Khi ng Timer 0 JMP $ T1_ISR: CLR TR1; Dng b nh thi MOV TH1, #HIGH(-1000); Np li MOV TL1, #LOW(-1000) CPL P1.0 SETB TR1; Khi ng timer 0 RETI

C
void main() { TMOD = 0x10; // Timer 1 ch 1 TH1 = 0xFC; TL1 = 0x17; // Np gi tr cho TF1 = 0; // Xa c trn ET1 = 1; EA = 1; TR1 = 1; // Khi ng Timer 1 while(1) continue; } void T1_ISR() interrupt 3 { TR1 = 0; // Dng b nh thi TH1 = 0xFC; TL1 = 0x17; // Np li P1_0 = !P1_0; TR1 = 1; // Khi ng b nh thi }

2. Lp trnh ngt ngoi


IE Interrupt Enable Register EA ET2 ES ET1 EX1 ET0 EX0

+ Lp trnh cho ngt ngoi 0 Cho php ngt ngoi 0 Cho php ngt ton cc EX0 = 1; EA = 1;

Vit chng trnh phc v ngt ngoi 0 + Lp trnh cho ngt ngoi 1 Cho php ngt ngoi 0 EX1 = 1; Cho php ngt ton cc EA = 1; Vit chng trnh phc v ngt ngoi 1 + Ngt ngoi c 2 kiu: Ngt bng mc 0 Ngt bng sn xung

Kch hot ngt ngoi bng sn xung hoc bng mc 0 chn ngt ngoi
TCON Timer/Counter Control Register

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Ngt ngoi 0: IT0 = 0: Ngt ngoi 0 c kch hot khi pht hin mc 0 chn ngt ngoi 0 (P3.2) IT0 = 1: Ngt ngoi 0 c kch hot khi pht hin sn xung chn ngt ngoi 0 (P3.2) Ngt ngoi 1: IT1 = 0: Ngt ngoi 1 c kch hot khi pht hin mc 0 chn ngt ngoi 0 (P3.3) IT1 = 1: Ngt ngoi 1 c kch hot khi pht hin sn xung chn ngt ngoi 0 (P3.3)

V d 1: Bt LED chn 1.0 khi xy ra mc 0 chn ngt ngoi 0 (P3.2). S dng ngt ngoi 0.

ASM
ORG 0000H LJMP MAIN ORG 0003H LJMP EX0_ISR ORG 0030H MAIN: SETB EX0; Cho php ngt ngoi 0 SETB EA; Cho php ngt ton cc JMP $ EX0_ISR: CLR P1.0 RETI

C
void main() { EX0 = 1; // Cho php ngt ngoi 0 EA = 1; // Cho php ngt ton cc while(1) continue; } void EX0_ISR() interrupt 0 { P1_0 = 0; }

V d 2: Bt LED chn 1.0 khi xy ra sn xung chn ngt ngoi 1 (P3.3). S dng ngt ngoi 1.

ASM
ORG 0000H LJMP MAIN ORG 0013H LJMP EX1_ISR ORG 0030H MAIN: SETB EX1; Cho php ngt ngoi 0 SETB EA; Cho php ngt ton cc JMP $ EX1_ISR: CLR P1.0 RETI

C
void main() { EX1 = 1; // Cho php ngt ngoi 0 EA = 1; // Cho php ngt ton cc while(1) continue; } void EX1_ISR() interrupt 2 { P1_0 = 0; }

Thanh ghi u tin ngt IP (Interrupt Priority Register)


IP D7 D6 D5 D4 D3 D2 D1 D0

Khng s dng Khng s dng

PT2

PT1

PT0

PS
u tin ngt cho Timer 2 u tin ngt cho Timer 1

PX1
u tin ngt cho Timer 0 u tin ngt ngoi 1

PX0

u tin ngt do port ni tip

u tin ngt ngoi 0

Lp trnh u tin ngt


IP Interrupt Priority Register

PT2

PS

PT1 PX1 PT0 PX0

Mun cho ngt no u tin th set bit u tin ca ngt ln. Khi 2 ngt xy ra cng lc th chui ngt bnh thng s b thay i Chui ngt l th t thc hin cc ngt bnh thng khi khng c ngt no c u tin, th t nh sau: ngt ngoi 0, ngt do timer 0, ngt ngoi 1, ngt do timer 1, ngt do cng ni tip, ngt do b timer 2 (i vi AT89S52 tr ln)