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Code of Conduct for the Laboratories General Laboratory Instructions List of experiments (as per JNTU) PART- A To verify the following functions 1) Adder, Subtractor, Comparator using IC 741 Op-Amp 2) Integrator and Differentiator using IC 741 Op-Amp. 3) Active Low Pass & High Pass Butterworth(Second Order) 4) RC Phase shift and Wien Bridge Oscillators using IC741 Op-Amp 5) IC 555 Timer in Monostable operation 6) Schmitt trigger circuits using IC 741 & IC 555. 7) IC 565- PLL Applications.
8) Voltage Regulator using IC 723, three terminal voltage regulators - 7805, 7809, 7912
5 6 8 9 11 17 20 25 28 32 37 -40 45 50 53 54 58 61 65 68 70 73 74
9) Sample and Hold LF 398 IC. 10) IC 566 VCO Applications PART-B To verify the functionality of the following 74 series TTL Ics 1) D Flip-Flop (74S74) and JK Master-Slave Flip-Flop (74LS73) 2) Decade counter (74LS90) and UP-Down Counter (74LS192) 3) Universal Shift registers – 74LS194/195. 4) 3-8 decoder – 74LS138. 5) 4 bit comparator 74LS85. 6) 8X1 Multiplexer – 74151 and 2x4 demultiplexer – 74155 7) RAM (16X4) – 74189 (read and write operations) 8) Stack and queue implementation using RAM, 74189
CODE OF CONDUCT FOR THE LABORATORY All students must observe the Dress Code while in the laboratory. Sandals or open-toed shoes are NOT allowed. Foods, drinks and smoking are NOT allowed. All bags must be left at the indicated place. The lab timetable must be strictly followed. Be PUNCTUAL for your laboratory session. Experiment must be completed within the given time. Noise must be kept to a minimum. Workspace must be kept clean and tidy at all time. Handle all equipments and components with care. All students are liable to pay for any damage to the equipment, accessories, tools, or components due to their own negligence. All equipments, apparatus, tools and components must be RETURNED to their original place after use. Students are strictly PROHIBITED from taking out any items from the laboratory. Students are NOT allowed to work alone in the laboratory without the Lab Supervisor Report immediately to the Lab Supervisor if any injury occurred. Report immediately to the Lab Supervisor any damages to equipment.
Before leaving the lab Place the stools under the lab bench. Turn off the power to all instruments. Turn off the main power switch to the lab bench. Please check the laboratory notice board regularly for updates.
One partner doing all the work will not be tolerated. and Record of the Experiment – 5marks Internal lab test(s) conducted during the semester carries 10 marks. conducted as per the JNTU regulations. Both partners should be able to explain the purpose of the experiment and the underlying concepts. analyze and test them in the laboratory. The lab books will be checked at the end of each lab session. For each program marks are awarded under three heads: Pre lab preparation – 5 marks Practical work – 5marks. ask for assistance. End semester lab examination. Each student is expected to have his/her own lab book where they will take notes on the experiments as they are completed. Of the 25 marks. 15 marks will be awarded for day-to-day work. Lab notes are a primary source from which you will write your lab reports. Organization of the Laboratory It is important that the experiments are done according to the timetable and completed within the scheduled time. Always attempt experiments. first without seeking help. When you get into difficulty. carries 50 marks. 4 .GENERAL LABORATORY INSTRUCTIONS You should be punctual for your laboratory session and should not leave the lab without the permission of the teacher. The aim of these exercises is to develop your ability to understand. You and your partner will work closely on the experiments together. if any equipment is faulty. Assessment The laboratory work of a student will be evaluated continuously during the semester for 25 marks. You should complete the prelab work in advance and utilize the laboratory time for verification only. A member of staff and a Lab assistant will be available during scheduled laboratory sessions to provide assistance. At the end of each laboratory session you must obtain the signature of the teacher along with the marks for the session out of 10 on the lab notebook. Please report immediately to the member of staff or lab assistant present in the laboratory.
You should include a well-drawn and labeled engineering schematic for each circuit investigated Your reports should follow the prescribed format.1 for second cycle. although students are encouraged to collaborate during lab. Your report should be complete. shifting back and forth from experimental facts to the presentation. NOTE:Internal diagrams and truth tables must be drawn neatly on left hand side. Graphics requiring drawn straight lines. Discussion of results can be in both the present and past tenses. They must be organized. Space must be provided in the flow of your discussion for any tables or figures. 5 . Error encountered :You are expected to note down the errors got in the lab so that you will have an idea of common mistakes you make in the lab. neat and legible.) Simulated Waveforms:A printout of the programs has to be attested. Well drawn free-hand sketches are permissible for schematics. Discussions or remarks about the presentation of data should mainly be in the present tense. Program(s):Programs have to be written without errors and with comments.Lab Reports Note that. Do not collect figures and drawings in a single appendix at the end of the report. Presentation Experimental facts should always be given in the past tense. Report Format: Lab write ups should consist of the following sections: Aim: Here you need to write in brief what you are doing in the laboratory in a line or two. thorough. to give your report structure and to make sure that you address all of the important points. understandable and literate. should be done with a straight edge.1 for the 1st cycle and Xillinx 9. Any specific conclusions or deductions should be expressed in the past tense. Software used: Here we want you to specify the vesion of the sftware used(This is required since we use Active-HDL 5.) Pin configuration:IC's pin diagram along with names of the pin. Reports should be submitted within one week after completing a scheduled lab session. Conclusion:Your observations have to be given. each must individually prepare a report and submit.(It would be even better to copy the errors and reproduce as it is.
7809. Comparator using IC 741 Op-Amp. 14) 4 bit comparator 74LS85. 8) Voltage Regulator using IC 723. 7) IC 565.PLL Applications. 7912 9) Sample and Hold LF 398 IC. Active Low Pass & High Pass Butterworth(Second Order) RC Phase shift and Wien Bridge Oscillators using IC741 Op-Amp IC 555 Timer in Monostable operation 6) Schmitt trigger circuits using IC 741 & IC 555. 74189 6 .7805.LIST OF EXPERIMENTS Part A : TO VERIFY THE FOLLOWING FUNCTIONS 1) 2) 3) 4) 5) Adder. Integrator and Differentiator using IC 741 Op-Amp. three terminal voltage regulators. Subtractor. 10) D Flip-Flop (74S74) and JK Master-Slave Flip-Flop (74LS73) 11) Decade counter (74LS90) and UP-Down Counter (74LS192) 12) Universal Shift registers – 74LS194/195. Part B : TO VERIFY THE FUNCTIONALITY of the following 74 series TTL ICs. 15) 8X1 Multiplexer – 74151 and 2x4 demultiplexer – 74155 16) RAM (16X4) – 74189 (read and write operations) 17) Stack and queue implementation using RAM. 13) 3-8 decoder – 74LS138.
A 7 .IC APPLICATIONS LAB PART.
The lab also introduces to the students 555 timer and its applications. The students will have an understanding of the concepts involved in various linear integrated circuits and their various applications. 5. various voltage regulators and 74 series TTL ICs. 3. Through this lab course the students will get a thorough understanding of various linear ICs especially the 741 operational amplifier and its various applications. Multimeter/Volt Meter 8 . electronic circuits. Regulated Power Supply.IC APPLICATIONS LAB OBJECTIVE The main Objective of this lab course is to gain the practical hands on experience by exposing the students to various linear and digital IC applications. 20 MHz/40 MHz Oscilloscope 2. Triangular and TTL). Square. switching theory and logic design and Solid state physics is required. EQUIPMENT REQUIRED FOR LABORATORIES: 1. 1 MHz Function Generator(Sine. PREREQUISITES Knowledge of electronic devices. Also the laboratory course of electronic devices and circuits and pulse and digital circuits should have been completed.
Rom = 1M Ω.EXPERIMENT . the op-amp is configured in inverting and non inverting mode and is used to compare a sine wave with a reference voltage (positive and negative). COMPARATOR USING IC 741 OP-AMP OBJECTIVE: To design and study adder. Rf = 100Ω . What is a comparator? ADDER Components: IC741. SUBTRACTOR. subtractor and comparator circuits using IC741. Equipment: Function generator Cathode ray oscilloscope Multimeter.it is shown that the op-amp can do addition and subtraction operations. Knowledge of IC 741 pin diagram 2. THEORY: In the Op-AMP applications. the adder and subtractor circuit are constructed. Must know the data sheet of IC741 4.01 ADDER. PRE-LAB:1. R1 = R2 = R3 = 300 Ω RL = 10K Ω. CIRCUIT DIAGRAM: V1 V2 V3 R1 300ohm R2 300ohm R3 300ohm 2 Rf 100ohm -15V 4 741 3 7 1 5 Rom +15V 1Mohm RL 10kohm 6 Vo 9 . Draw the internal circuit of IC 741 3.
3. 3. V1(V) 2 2 5 V2(V) 2 -3 -6 V3(V) 2 5 -2 Vo(Theoretical) Vo (Practical) SUBTRACTOR COMPONENTS: IC741. Connect the components as per the circuit diagram. CIRCUIT DIAGRAM: Rf 1kohm V2 R R11kohm 2 1kohm 3 -15V 4 741 7 1 5 RL 10kohm 6 V1 Vo Rom 1kohm +15V 10 . V2 = -6V.V2 = -3V.No 1. Rf = R1 = Rom = 1K Ω. Repeat the above procedure for V1 =2V. V3 = 5Vand also V1 =5V. 2. 2. OBSERVATIONS: S. Apply V1 = V2 =V3 = 2V and observe output voltage in CRO or multimeter. V3 =-2V. RL = 10K Ω.PROCEDURE: 1.
3.No V1(V) 1. Apply V1 =10V. Connect the components as per the circuit diagram. RL = 10 k Ω CIRCUIT DIAGRAM: R1 1kohm +15V 7 1 3 2 741 4 5 6 RL 10kohm Vo 5V 3. V2 = 5V and observe output voltage in CRO or millimetre.PROCEDURE: 1.54V_rms 1kHz 0Deg R 1kohm -15V Vref 11 . OBSERVATIONS: S. 10 5 10 V2(V) 5 10 10 Vo(Theoretical) V0=V1-V2 Vo (Practical) COMPARATOR COMPONENTS: IC 741. 3. R1 = R = 1 K Ω.V2 = 10V and also V1 =V2 =10V. 2. Repeat the above procedure for V1 =5V. 2.
3. 5. (a) When Vref = 3V 12 . 2. Connect the components as per the circuit diagram. Apply a sine wave with input voltage Vi = 10 Vpp . Draw the waveforms on a graph sheet. Repeat the above procedure with Vref = --3v and Vref = 0v. f = 1 kHz Vref = 3V Observe the input and output waveforms in CRO. EXPETED WAVEFORMS: Input and output waveforms Fig. 4.PROCEDURE: 1.
(b) When Vref = . (c) When Vref = 0V POST-LAB:1 verify the values obtained for adder and subtractor 2. Verify whether the obtained readings matched to the theoretical values 3.3V Fig.Fig. Tabulate the values 4. subtractor and comparator are studied 13 . Draw the input output graph for comparator CONCLUSIONS: Hence the adder.
Draw an op-amp whose output is V1 +2V2 –3V3 –V4 . 14 . List different types of comparators. 8. 9. Explain the difference between inverting and non-inverting summing amplifiers. Design a scaling amplifier circuit that will amplify the first input by a factor of 2 and the second by a factor of 3. 2. What are the applications of comparator? 4. Draw the characteristics of an ideal comparator and that of a practical comparator. What is the other name for regenerative comparator? 5.QUESTIONS: 1. Design a summing amplifier to add three DC input voltages. 10. 6. The output of this circuit must be equal to two times the negative sum of the inputs. Draw the non-inverting adder circuit diagram. 3. Design an averaging circuit with 4 dc inputs 7.Use inverting configuration for the scaling amplifier.
CIRCUIT DIAGRAM A) differentiator 15 .amp. Connecting Wires-as per the requirements. Function Generator-01 4.10kΩ 6. 2. What is the ideal Integrator 4. Resistors: 1.EXPERIMENT . 2.02 INTEGRATOR AND DIFFERNTIATOR USING IC741 AIM: 1. To study the integrator circuit using Ic 741 op. IC-741 op-amp. What is the output of an integrator when i/p is squre wave.amp PRELAB: 1.0kΩ. 3. DUAL Regulated Power Supply -01 2. To study the differentior circuit using Ic 741 op. What is the ideal differentiator APPARATUS: 1. CRO-01 3. Breadboard -01 7. 5. What is the output of an Differentiator when i/p is Triangle wave.
2kOhm_5% 7 3 6 2 4 741 V2 12V R4 10kOhm_5% A B R1 C1 1 5 U1 XSC1 G T 220Ohm_5% 100nF V3 1000Hz 5V R3 1.0kOhm_5% V1 12V 7 1 5 U1 3 R2 V3 1.0kOhm_5% 100Hz 5V 6 2 4 V2 12V 741 A B G T XSC1 10uF PROCEDURE A) Differentiator 16 .V1 12V R2 1.2kOhm_5% B) Integrator R1 C1 1.
. 6. Connect the components on the breadboard according to the circuit diagram. 6.4 and –ve to the ground of the ch-1. And Connet –ve terminal to pin no-07 and +ve to ground of ch-02 5. Apply the input as squar wave from the from the function generator according to the RC time constant.06. 4. Connect the components on the breadboard according to the circuit diagram. Apply the input as squar wave from the from the function generator according to the RC time constant.function generator and CRO. 2. Set the both channels of the power supply at 12v.no. B) Integrator 1. Connect +ve terminal to pin no. 2. Observe both waveforms and draw on graph paper. Set the both channels of the power supply at 12v. Observe both waveforms and draw on graph paper. 7. 7.. Switch on the power supply.function generator and CRO. Connect +ve terminal to pin no. 3. 3. 4.1.no. At ch-1 display the input waveform and ch-2 display output of the circuit from pin.06. 5. Switch on the power supply.Because the differentiator circuit is high pass filter where RC<<T.Because the differentiator circuit is high pass filter where RC>>T. 8.4 and –ve to the ground. At ch-1 display the input waveform and ch-2 display output of the circuit from pin. EXPECTED WAVEFORMS A) Differentiator 17 .
01F. Draw the characteristic curves for both LPF & HPF 4. EQUIPMENT: C. What is meant by frequency characteristics? COMPONENTS: IC 741.O Function generator Multimeter 18 . Tabulate the values 2.R. integrator& differentiator are studied. PRE-LAB :1. C = 0. What is meant by cut off frequency? 2. Draw the corresponding graphs Conclusion: Hence. R = 15k Ω.B) Integrator POST LAB: 1. R1 = Rf = RL = 10 k Ω . EXPERIMENT – 03 ACTIVE LPF & HPF BUTTERWORTH ( SECOND ORDER ) OBJECTIVE: To design and study the second order a) Low pass Butter worth filter b) High pass Butter worth filter Using IC 741. What is meant by bandwidth? 3.
Choose a value for the fH 2. AF = 1 + R ( since non .586 design the circuit using the formulas fH =1/ 2π√R2R3C2C3 . For 1kHZ upper 3-dB frequency and pass band gain of 1. Compare theoretical and practical upper 3-dB frequencies.inverting ).log graph sheet and indicate pass band and stop band. 3. 5. To simplify the design calculations Set R2=R3=R&C2=C3=C then choose C< | μF 19 . LOW PASS FILTER ( LPF ) CIRCUIT DIAGRAM: PROCEDURE: 1. Plot the frequency response on the semi . Apply Vi = 2 Vpp and vary the frequency from 100 HZ to 100 kHZ . In the high pass filter all the frequencies below the cut-off frequency are attenuated. Calculate upper 3-dB frequency from the graph. The pass band gain and the cut-off frequency are calculated.THEORY: In the low pass filter the higher end frequencies above the cut-off frequency are attenuated. DESIGN PROCEDURE: 1. 1 RF 2. 4.
Calculate the value of R using R = 1/2πfHC OBSERVATIONS: Tabular form: S.3.No Frequency(Hz) Output voltage(Vo) Av= Vo Vi Av in dB = 20 log10Av EXPECTED GRAPH: HIGH PASS FILTER ( HPF ) CIRCUIT DIAGRAM: 20 .
No Frequency(Hz) Output voltage(Vo) Av= Vo Vi Av in dB = 20 log10Av 21 .0kOhm_1% R1 33kOhm_5% R2 33kOhm_5% 0 PROCEDURE: 6.log graph sheet and indicate pass band and stop band. Calculate the value of R using R = 1/2πfLC OBSERVATIONS: Tabular form: S. 1 RF 7. Plot the frequency response on the semi . Apply Vi = 2 Vpp and vary the frequency from 100 HZ to 100 kHZ . Choose a value for the fL 5. DESIGN PROCEDURE: 4.54V_rms 1kHz 0Deg 3 C2 2 4 2 3 U1 XSC1 G 90% 6 1 A B T 4. 8. AF = 1 + R ( since non .586 design the circuit using the formulas fL =1/ 2π√R2R3C2C3 .7nF 7 1 5 LF351D 7 V3 12V R3 10.R4 27kOhm_5% R5 Key = a 20K_LIN V2 12V 4 6 C1 V1 5 4. 9.7nF 5V 3. To simplify the design calculations Set R2=R3=R&C2=C3=C then choose C< | μF 6. Calculate lower 3-dB frequency from the graph.inverting ). For 1kHZ lower 3-dB frequency and pass band gain of 1. 10. Compare theoretical and practical lower 3-dB frequencies.
Butter worth and chebyshev filters. Why active filters are preferred? 2. What is the roll-off rate of a first order filter? 4. Define Bessel. What is a Sallen-key filter? 6. 3. and compare their 22 . Tabulate the values 3. Calculate the gain in db. Discuss the disadvantages of passive filters. Draw the frequency vs gain curve 4.EXPECTED GRAPH: POST-LAB :1. From the graph obtain cut-off frequencies and bandwidth for both LPF & HPF CONCLUSIONS: The frequency response characteristics of HPF & LPF are obtained QUESTIONS: 1. 2. What are the advantages of higher order filters? 5.
C1 = C2 = C=0. 8. What are the applications of all-pass filter? 10. R1 = 30 KΩ. List the most commonly used filters. What is an all-pass filter? 9. What is meant by frequency stability 3. RF = 60 KΩ (100 KΩ pot).7.05µ F. Describe oscillator principle 2. 11. Draw the circuits of RC phase shift & wein bridge oscillator & their responses APPARATUS : R2 = R3 =R=3.1 KΩ. How are filters classified? EXPERIMENT – 04 OSCILLATORS USING IC 741 WEIN BRIDGE OSCILLATOR AIM : To design a Wein bridge oscillator for f = 1KHz and study its operation PRE-LAB :1. Response. 23 .
CIRCUIT DIAGRAM: R1 Rf -15v 4 2 741 3 7 1 5 6 Vo +15v R3 R2 C2 C1 FORMULA: fo = 1 2π RC PROCEDURE : 1.Rom = 15 KΩ . Connect the components as per the circuit diagram 2. CIRCUIT DIAGRAM: 24 . APPARATUS: R4 = R5 = R6 =R=1. RC PHASE SHIFT OSCILLATOR AIM : Design a phase shift oscillator for f0 = 500Hz & Study its operation. 3. Observe the output waveform at pin number 6.1µF Rf = 435KΩ (500 KΩ potentiometer) R1=15KΩ.5KΩ .C1= C2 =C3=C = 0. Calculate frequency of the output waveform .
Rf -15v R1 2 741 3 Rom 7 1 5 6 4 Vo +15v C1 C2 C3 R4 R5 R6 FORMULA: f0 = 1 2π 6 RC and Rf ≥29 R1 PROCEDURE: 1. Observe the output waveform at pin number 6. Connect the components as per the circuit diagram. 3. 2. Calculate frequency of the output waveform. EXPECTEDWAVEFORMS RESULTS&DISCUSSIONS: 25 .
26 .1μF . Knowledge of electronic device and circuits.7k Ω . must know the pin configuration of 555 IC 3. must know the internal circuit diagram for 555IC 4. Rc = 1. 2.01μF .1μF .8k Ω . Ra = 1k Ω . C = 0.EXPERIMENT . must have the knowledge of monostable & astable multivibrators COMPONENTS: 555 Timer . C1= 0. pulse and digital circuits lab. OBJECTIVE: To study the operation of monostable multivibrator using 555 timer and compare theoretical and practical results .05 IC 555 Timer-Monostable and Astable Operation Circuit . R = 4. C2 = 0. PRE-LAB :1. Rb = 1.2k Ω .
O Function generator Multimeter Bread board trainer kit THEORY: In this experiment the circuit for generating a square waveform is constructed the free running multivibrator concept is understood.1 RC 27 . The 555 Timer is used in number of applications. It can produce accurate and highly stable time delays or oscillations FORMULA : TP = 1. analogy frequency voltage regulators and time delay circuits. DC-toDC converters.BC 107 transistor.a ). EQUIPMENT: C. the duty cycle is calculated.R. it can be used as monostable. The IC 555 timer is 8-pin IC and it can operate in free. digital logic probes.running (Astable MV ) mode or in one-shot ( Monostable MV ) mode pin configuration is as shown fig (1. astable multivibrators.
3 and capacitor voltage at pin no.CIRCUIT DIAGRAMS: Vcc= +10 v Rc C1 Rb Vo ( To pin 2) Q1 BC107BP Ra Vi Figure 1: Trigger circuit. Observe negative going triggering pulses at the output of the trigger circuit and connect them to trigger input of IC 555. Connect the components as per the circuit diagram. Draw the output Vo at pin no. 6 on a graph sheet. 3. VCC 10V 8 4 R 7 6 2 5 RST VCC 3 DIS OUT THR 555 TRI CON GND 1 Vo C C2 Figure 2: Monostable multivibrator circuit PROCEDURE: 1. Measure the pulse width TP of the monostable multivibrator using CRO and compare with the theoretical value. 28 . 4. 2.
6KΩ. Connect the components as per circuit diagram using RA =3.25 KΩ observe the output waveform on CRO and slowly adjust the resistance box until 50% duty cycle VCC 10V 8 Ra 4 7 6 Rb 2 5 C1 RST DIS TRI CON GND 1 VCC OUT 3 THR 555 Vo C2 29 . Now replace RB by 7. Initially adjust the resistance box to 7.5KΩ.EXPECTED WAVEFORMS: PROCEDURE: 1. 2. RB =5. RA with a resistance box and connect a diode across RB 4.25 KΩ. 3. Observe and sketch the capacitor voltage waveform (pin-6) and output waveform (pin-3) measure the frequency & duty cycle of the O/P waveform.
Discuss some applications of timer in monostable mode? 5. Briefly explain the differences between the two operating modes of the 555 timer 4. What is the expression for pulse width of monostable multivibrator? 30 . What are the two basic modes in which the 555 timer operates? 3. Calculate the duty cycle CONCLUSIONS: Monostable and astable waveforms are verified QUESTIONS: 1. Calculate the time periods for both astable and monostable M.V 3. List important features of 555 timer 2. Verify the monostable and astable waveforms 2. Explain the function of rest pin in 555 timer 6.WAVE FORMS: POST-LAB :1. Define duty cycle 7.
R1= 10k Ω . APPARATUS: IC 741 . Draw input and output waveforms and transfer characteristic . which is at positive saturation V+ initially. Find the hysteresis voltage which is the difference between UTP and LTP. This is lower triggering point (LTP ). Observe the output voltage. 3. 6. observing the output.2 kΩ. 4. 31 . C1= C2= 0. 5. This is upper triggering point ( UTP ). R 1= R 2= 100KΩ. IC555. 2. Then slowly decrease the input while observing the output . from V-. Note down the input voltage at which reverse transition occurs in the output i.e. to V+ . CIRCUIT DIAGRAM : -15 v 4 Vi 2 741 3 7 1 5 6 R1 Vo +15 v R2 FORMULAS: UTP = R2 Vo R 2 + R1 R2 Vo R2 + R1 LTP = PROCEDURE : 1. Connect the components as per the circuit diagram.01µF. Apply a DC input voltage and increase it from 0 v slowly. Note down the input voltage at which output transition occurs from V+ to V-. R2= 2.EXPERIMENT – 06 SCHMITT TRIGGER AIM: To design a Schmitt trigger circuit using IC 741and IC 555.
Measure and sketch output and transfer characteristics.VLTP 7. From transfer characteristic measure LTP . 9. EXPECTED WAVEFORMS: Input and output waveforms: Transfer characteristics: 32 . UTP and hysteresis voltage VH. 8.VH = VUTP -. Apply a square wave input of 10 v at 1kHz.
which is at positive saturation V+ initially.(For this disconnect C1 capacitor). Observe the output voltage. observing the output.CIRCUIT DIAGRAM : PROCEDURE : 10. Connect the components as per the circuit diagram. 12. Apply a DC input voltage and increase it from 0 v slowly. 11. 33 .
13. Note down the input voltage at which output transition occurs from V + to V-.This is upper triggering point (UTP). 14. Then slowly decrease the input while observing the output. Note down the input voltage at which reverse transition occurs in the output i.e. from V -. to V+ . This is lower triggering point (LTP). 15. Find the hysteresis voltage, which is the difference between UTP and LTP. VH = VUTP - VLTP 16. Apply a sine wave input of 10v at 1kHz. 17. Measure and sketch output and transfer characteristics. 18. From transfer characteristic measure LTP, UTP and hysteresis voltage VH.
EXPECTED WAVEFORMS: Input and output waveforms:
EXPERIMENT – 07 IC 565 – PLL Applications. AIM: To study the phase lock loop using IC 565 and it’s application as frequencydivider to take input frequency given by an external signal source. PRELAB: 1. Name the IC used for PLL. 2. Name the counter used in experiment. 3. Name the IC of decade counter APPARATUS: 1. Function Generator. 2. Dual trace CRO. 3. IC logic trainer board.or normal breadboard. 4. Electronic components according to the circuit diagram. 565IC -01. 741 opamp -01 7490 Decade counter -01 Resistor 4.7kΩ 04 Resistor 10kΩ -01 Capacitor 0.001μf -01 5. Connecting Wires. 6. Dual regulated power supply -01 PROCEDURE: 1. Display the electronic components according to the circuit diagram to the circuit diagram on the IC logic trainer board.And apply the biasing voltage to the IC 565,IC 740 op.amp.and IC 7490 decade counter.
It means the frequency multiplication is taken place in this circuit. 5.and o/p at ch-02 of the CRO. 6. Display the i/p frequency at ch-01. The ratio in between both is 10:1 or 6:1. CIRCUIT DIAGRAM 37 . 4.7kΩ).001) and Rs(4.function generator and CRO.4 of IC565. Next give any signal (square wave)of variable frequency and observe the o/p at pin 12 of the decade counter IC-7490. 3.2. Compare both i/p and o/p waveforms.This is a square waveform the frequency of the VCO o/p is depends on the Ct(0. Check the VCO output at pin. Switch ON the power supply .
EXPECTEDWAVEFORMS 38 .
DC ammeter. 7905. (0-200) Ma CIRCUIT DIAGRAM Vin 0 to +40V DMM – + V R2 10kOhm_5% R1 22KΩ POT 6 1 8 14 5 7 13 IC 723 12 11 2 10 3 9 4 10Ohm_5% Vo 2V . What is meant by voltage regulator? 3.e 0 to + 40 V and 0 to – 40V using digital multimeter.EXPERIMENT – 08 VOLTAGE REGULATOR USING IC 723& THREE TERMINAL VOLTAGE REGULATOR 7805. By varying R1 measure the output voltage. A) Low voltage regulator using IC 723: 1. 3.7V R3 + 680Ohm_5% V DMM – 100pF Figure : Low voltage regulator using IC723 PROCEDURE:1. 39 . Calculate the theoretical voltage and compare it with practical value. 2.To study the operation of precision voltage regulator IC 723 and the operation of following three terminal IC voltage regulators: 7805. 3. 2. Digital multimeters ……… 2 Nos. What are the different types of voltage regulators? COMPONENTS AND EQUIPMENT REQUIRED :1. LM 317. Knowledge of electronic device and circuits. Connect the circuit as shown in Figure 1. i. Measure the output of the regulated power supply. pulse and digital circuits lab. 7905 OBJECTIVE:: . 2. and LM 337. Connect the trainer to the mains and switch on the supply. Voltage regulators trainer 2. PRE-LAB :1.
13. The output voltage is given by : V ref R 1 +R 2 R2 V ref R 2 where Vref is the voltage at pin 6. R1 is selected value. 1. The output voltage is given by : R R 1 2 where Vref is the voltage at pin 6.4. Calculate the theoretical voltage and compare it with practical value. 14. R2 is 10 K.1 K. R2 is 5. 12. Measure the output of the regulated power supply.1kOhm_5% 22KΩ + POT V – DMM Figure 2 High voltage regulator using IC723 PROCEDURE :1. Fixed voltage regulators: A) 7805(+5V) 3. i. Connect the circuit as shown in the figure to observe the line regulation. R1 is selected value.e 0 to + 40 V and 0 to – 40V using digital multimeter. Connect the circuit as shown in Figure 2. B) High voltage regulator using IC 723: 11. Vin 0 to +40V R3 680Ohm_5% 6 1 8 14 5 7 13 12 11 2 10 3 9 4 10Ohm_5% Vo R1 7 to 37 V IC 723 + V – DMM 100pF R2 5. Vin 0 to +35V 1 7805 2 3 +5V + V – + C DMM 22uF V DMM – Vo GND 40 . 2. By varying R1 measure the output voltage. Connect the trainer to the mains and switch on the supply.
V0 on y-axis and observe the load regulation. corresponding output voltage Vo and record them as shown below. IL Vo (V) Load regulation 9. 8. Vo and observe the line regulation. Plot the graph between Vin. measure the load current IL. By varying the load (250 Ω potentiometer in steps. Vin Vo 5.e. 41 . Plot the graph between IL on x-axis. Vin 0 to +35V DMM + V – 1 7805 2 3 C 22uF- + A – DMM + V – +5V (0-200) mA 250Ω POT Vo GND 7. Measure and record the output voltage Vo (No load) i. Connect the circuit as shown below to observe the load regulation. 6. Calculate load regulation using V0 ( no load ) −V0 V0 10. By varying Vin supply in steps measure the corresponding output Vo and record in a tabulated form as shown below.4. at zero (0) load current.
Repeat the above steps 7 to 10 for load regulation. 42 . Compare theoretical and practical results. 13. RESULTS :1. Vin + V – GND 2 7905 1 3 + DMM C 22uF V DMM – VO 12. (0-200) mA Vin 0 to -35V DMM + V – 2 7905 1 3 C 22uF- + A – DMM + -5V V – 250Ω POT Vo GND 14. Repeat the steps 4 and 5 above for line regulation.B) 7905 (-5V) 11. Connect circuit as shown in below for load regulation. Connect the circuit as shown in below for the line regulation.
5. What are the limitations of 3terminal IC regulators? 6. List different types of voltage regulators? 7. Design a high voltage and low voltage regulator using IC 723. What are the features of IC723? 43 . 2. List the characteristics of 3 terminal IC regulators? 5. QUESTIONS: 1. 4. What voltage options are available in 78Xxvoltage regulators? 3. What is the function of a voltage regulator? What are the limitations of three terminal regulator? What is a voltage reference? Why is it needed? Draw the functional block diagram of 723 regulator. What are the applications of 3 terminal IC regulators? 10. What voltage options are available in 79Xxvoltage regulators? 4. What is the function of a voltage regulator? 2. Define line and load regulation of a regulator. CONCLUSIONS: Compare theoretical and practical results. 1.POST-LAB :1. What are the advantages of adjustable voltage regulators over the fixed voltage regulators? 9. What is a voltage reference? Why is it needed? 8. 3.
This assures that the A/D is not trying to hit a moving target. 44 . Afterwards the switch is opened and the capacitor retains its charge. (b) A practical S/H circuit. real world signals may fluctuate rapidly.1(b).EXPERIMENT – 09 Sample and Hold Circuit using LF398 IC Objective 1. A practical implementation of the S/H circuit is shown in figure 6. Equipment Digital Communications Panel (SIP397-1) Power Supply Base (S300PSB) Function Generator Oscilloscope Frequency Counter Digital Multimeter Basic Information Theory A/D circuits require the input signal to remain constant during the conversion process. regardless of fluctuations of the input. until released to follow the input again. It then maintains the output as steady as possible. The resulting output is shown in figure 6. however. The switch is a FET whose gate is controlled by the clock pulse. The switching rate is controlled by a clock signal whose frequency should satisfy the Nyquist sampling criterion.1(a).2-b. The Sample and Hold (S/H) is a device that makes its output follow the input until it is told to hold this value. When the switch S is closed. This alternation between sample and hold modes is repeated as long as the switch keeps toggling. the hold stage. the S/H circuit consists of a switch (S) and a capacitor (C) as in figure 6. In its simplest form.To evaluate and analyze an implementation of a sample and hold (S/H) circuit. the capacitor C is charged to the value of the input voltage. Buffers are placed at the input and output to isolate the circuit. the sample stage. (a) (b) Figure (a) A simple S/H circuit.
Things are complicated further if the original signal is composed of many frequencies. Unfortunately. a new signal will appear instead of the original signal. sampling at a rate higher than the Nyquist (over-sampling). In reality this is not possible since we do not know the frequency of the original signal and we do not know if aliasing has occurred in the first place. 2. 45 . if a signal was sampled at a rate less than double its maximum frequency aliasing will occur. Much depends on the quality of the charging capacitor. The S/H has three sources of error: 1. the sampling rate is increased. The absorption of the dielectric used in the hold capacitor is extremely important. the value being held should remain constant. the sampled signal can be slightly off.Signal Droop: The voltage being held on the capacitor starts to slowly decrease over time if the signal is not sampled often enough. see figure 6.e. It is responsible for regulating the hold step.Signal Feedthrough: When the S/H is not connected to the i/p signal. This is called the aperture time. It must be sampled at a minimum of 4kHz. Therefore we must make sure aliasing does not occur in the first place. This is accomplished by two things. (c) Capacitor droop. This new frequency looks like it is folded back around the original signal. Polystyrene and polypropylene capacitors are best suited for S/H circuits. The frequency of the new signal will be at 1kHz.Finite Aperture Time: The S/H takes a period of time to capture a sample of the signal.2(c). If by mistake this signal is sampled at 3kHz. To reduce the first and second sources of error. causing the voltage being held to change slightly. and by limiting the upper frequency of the original signal through a low pass filter (anti-aliasing filter). Since the signal will vary during this time.Figure (a) Original signal. This will appear as a new signal at a different frequency. the acquisition time and the droop rate. I. For example if the signal to be sampled has a frequency of 2kHz. It appears that since we know what has happened we can recover the original signal. Aliasing If the Nyquist rate for sampling is not satisfied. some signal does bleed through the switch to the capacitor. (b) Sample and hold cycles. 3. some below the Nyquist rate and some above. The third source of error is reduced by selecting a special kind of capacitor. Lossy standard capacitors are slow which reduces the sampling rate.
to the input of the output amplifier B. The external capacitor is charged from a current source through the logic controlled switch.Clocked sampling for a continuous signal 46 . and a digital switch. or AC through Vin.The LF398 S/H Integrated Circuit The LF398 is a basic and common S/H monolithic IC. Selection of input is through switches c7 and c8. of FET type for high input and low output resistances. Procedure Part A. Amplifier C is a digital switch. The hold capacitor is connected externally. In the hold mode. The hold capacitor 4 with different values is selected through switches c1 and c2. figure 6. The sample and hold modes are chosen as continuous sample mode by switch c6 and a reset switch. or clocked S/H through switches c4 or c5. the capacitor is connected to the output of the input amplifier A. the charge on the capacitor follows the analog input signal. the input amplifier is disconnected and the capacitor holds the charge. The output of amplifier B is fed back to amplifier A. It consists of an input and output buffer amplifiers. The capacitor is discharged by the follower amplifier. The analog input is selected to be DC (+5 to -5V) through a pot.3. which is turned on when the logic input drops below the reference voltage.3 is built around the LF398 IC. and during the hold mode. During the sample mode. Figure LF398 block diagram and S/H experiment circuit connections The Sample & Hold Experiment Circuit The experiment circuit in figure 6. A resistor is connected in parallel to the hold capacitor through switch c3 to clarify the effect of capacitor droop. During the sample mode. Amplifier B is a unity gain follower. Amplifier A is bipolar with low output offset voltage and wide bandwidth.
8kHz at TP6 (in section B. 3.SAMPLE/HOLD). 4.Close switches b4 & c5 to feed a sampling clock to the LF398 IC. and use it as the trigger for the oscilloscope. ………………………………………………………………………………………………… ………………………………………………………………. Measured No.5ms/div and find the alias frequency. Record this clock. 9. And connect it to the input of the IC at TP5.Increase the input frequency to 800Hz.Set the oscilloscope to 0.1. Clock Amplitude (V) Frequency (kHz) 6.Count the number of samples/cycle.Set the function generator to 3VPkPk sine wave at 200Hz.Record the sampling output at TP7 through ch2 of the oscilloscope.Connect 30nF hold capacitor to pin 6 of the IC by closing switch c1.Set the supply voltages on the power supply base to +10V. Measured No. Measured Theoretical Alias Frequency 47 Theoretical .. Also connect ch1 of the oscilloscope to TP5.Increase the input frequency to 5kHz. Adjust the Hold-Off on the oscilloscope for best display. 2... of samples/cycle 8.Universal Clock section of the test board) to get a sampling frequency 4. Repeat step 6. of samples/cycle Theoretical 7. Adjust R1 potentiometer (in section A. Describe the display and explain what has happened. 5.
Change the input signal to a triangular wave at 400Hz. open sw. c1 and close sw c2 and c3. 2.Capacitor droop observation 1.Part B. Record the sampled output. Record the output. add k resistor in parallel with the 0.003F capacitor. ………………………………………………………………………………………………… ………………………………………………………………………………………………… ………………………………………………………………………………………………… ……………………………………………………… 48 .Record the o/p at TP7.To simulate a lossy capacitor. 4.Compare and describe what happens to the shape of segments between steps 1 & 4. 3.
2. What is the function of VCO? COMPONENTS AND EQUIPMENT REQUIRED :1.O/P Input IC 566 5 7 3 1 VC R2 Square . Voltage Controlled Oscillator trainer 2.1uF 10K 49 . Digital multimeter. Knowledge of electronic device and circuits.O/P C 1KpF 10KpF 0. What is a VCO? 3.5K 10K 15K 1uF R 6 P1 1000pF 8 4 10K Triangle . pulse and digital circuits lab. CIRCUIT DIAGRAM :Figure 1. Pin diagram of IC 566 Ground NC Square wave output Triangular wave output 1 2 3 4 8 7 NS/SE 6 566 VCO +V C R Modulation input (VC) 5 Figure 2. Typical connection diagram of the VCO +12V R1 7.EXPERIMENT – 10 IC 566 – VCO APPLICATIONS OBJECTIVE: :-To study the operation of Voltage Controlled Oscillator (VCO) using IC 566. POST-LAB: 1. Dual trace oscilloscope 3.
List the basic building blocks of VCO? 2. 2. Expected Output waveforms PROCEDURE :1. Connect digital Multimeter to VCO input. Connect dual trace oscilloscope to square and triangular outputs. 10K and 15K). POST-LAB:1.5K.fiigure 4. Mention the applications of voltage-controlled oscillator. 2. Why it is called as Voltage controlled oscillator. Switch on the trainer. How do you vary the vco frequency. C. By varying the voltage at VCO input (with the help of potentiometer given ) observe the output signal on CRO and measure the output frequency . Repeat the steps 3 to 7 for different values of R. What are the applications of VCO? 4. 1. 3. QUESTIONS: 1. Connect one of the range resistors (7. Tabulate the theoretical and practical readings for different sets of R and C. Briefly explain the role of LPF in VCO? 3. 3. What is a VCO? 50 . Compare output frequency with theoretical value given by : f0 2(+V-Vc)/(RC(+V)) 4. 3. 2. CONCLUSIONS: 6.
5. What waveform is generated at pin4 of IC 566? 8. What waveform is generated at pin 3of IC 566? 7. Write expression for frequency of 9. What are the features of IC 566 VCO? 51 . What is the difference between the saw tooth wave and the triangular wave? 6. What is the other name of VCO? 10.
PART.B 52 .
Knowledge of IC 74LS74 and 74LS73 pin diagram.EXPERIMENT-01 D FLIP-FLOP(74LS74) AND JK MASTER-SLAVE FLIP-FLOP (74LS73) OBJECTIVE: To verify the functionality of D Flip-Flop 74LS74 and JK Flip-Flop 74LS73 PRELAB: 1. 2. 3. D FLIP-FLOP PIN DIAGRAM: LOGIC SYMBOL: 53 . 4. Must know the data sheet of IC 74LS74 and 74LS73. Draw the internal diagram of IC 74LS74 and 74LS73. Knowledge of basic operation of D Flip-Flop anf JK Flip Flop.
FUNCTIONAL TABLE: 54 .
JK FLIP FLOP PIN DIAGRAM: 55 .
The Basic JK Flip-flop The Master-Slave JK Flip-Flop CONCLUSION : The Logic Table of D and JK F/F Has been Verified 56 .
2. 4. Wire the circuit diagram shown in above figure. 3. Record the counter states for each clock pulse.EXPERIMENT – 02 DECADE COUNTER (74LS90) AND UP-DOWN COUNTER(74LS192) AIM: To construct and verify the working of a single digit decade counter using IC 7490 and up-Down Counter74LS192. Knowledge of basic operation of up-Down Counter and Decade Counter. Record the counter states for each clock pulse. Now Construct decade counter using J – K F/F’s and record the counter states. Must know the data sheet of IC 74LS192 and IC7490. APPARATUS: 1. 5.(14) 3. DECADE COUNTER (74LS90) CIRCUIT DIAGRAMS: PROCEDURE: 1. Connect the 1Hz clock to pin CPO. Connect the reset terminals (MR1 & MR2) to high and set terminals (MS1 & MS2) to zero and observe the output. Draw the internal diagram of IC 74LS192 and IC7490. Knowledge of IC 74LS192 and IC7490 pin diagram. 7. 2. Now connect set and reset inputs to zero and observe the outputs. 8. 4. Design mod 6 counter using IC 7490 as shown in fig 2. 6. 57 .
TRUTH TABLE: EXPEXTED WAVEFORMS: 58 .
What is the modulus counter? 4. Design a divide –by-96 counter using 7490Ics? 59 .Verified the working of a single digit decade counter using IC 7490.UP-DOWN COUNTER(74LS192) PIN DIAGRAM: Vcc 16 A 15 CLR 14 BO 13 CO 12 LOAD 11 C 10 D 9 A CLR BO CO LOAD C D QD B QB QA 74192/74193 DOWN UP QC 1 B 2 QB 3 QA 4 5 6 QC 7 QD 8 Gnd DOWN UP LOGIC SYMBOL: UP 4 3 DOWN QA 14 2 CLR QB 11 6 LOAD QC 7 QD 15 A 1 13 B BO 10 12 C CO 9 D 5 74192/74193 CONCLUSION:. What is BCD counter? 8. What is up –down counter? 6. How many numbers of flip-flops are there in decade counter? 5. What is the maximum count? 9. If the counter has n-flip-flops. What is the difference between Register &counter? 7. Which flip. Design Mod 6 counter using JK F/F’s? 3.flops are used in counter? 10. QUESTIONS:1. Design Mod 7 and Mod 5 counter using IC 7490? 2.
Connecting wires. Apparatus : 1.EXPERIMENT – 03 IC 74195 UNIVERSAL SHIFT REGISTER Aim : To study the operation of the shift register using IC7495 . 60 .Shift register kit 2.
Apply 1 Hz CLOCK CP input to 9. Put the 6th pin in high and 1st pin in low position. 6. Construct 4 – bit left shift register as shown in fig. 5. Connect the output logic level indicators to the outputs of each stage of shift register.PROCEDURE: 1. In left shift register 2&12. Observe the left shifting through the shift register.4&10 pins shorted and given to the Output. 3&11. 2. 63 . 3. 4. Switch ON 5th pin some time and after off it.
EXPERIMENT – 04 3 TO 8 DECODER Aim: To verify operation of the 3 to 8 decoder using Ic 74138. 2) Patch chords .Two active low and one active high.The IC 74138 accepts three binary inputs and when enable provides 8 individual active low outputs . Theory: A decoder is a combinational circuit that connects the binary information from ‘n’ input lines to a maximum of 2 n unique out put lines . CIRCUIT DIAGRAM: 64 . The device has 3 enable inputs . Apparatus : 1) 3 to 8 decoder Ic 74138 kit.
TRUTH TABLE: LOGIC DIAGRAM: 65 .
Implement a full subtract or using IC 74138? 10. 3. What is the difference between decoder & encoder? 3. using switches. What is even parity & odd parity? 7. What is the difference between decoder and demux? 66 .and C.G2B. 4. Which gate can be used as parity generator & checker? 8.Verified the Operation of 3 to 8 Decoder. Change the values of G1. Observe status of Y0. 2.G2A. to Y7 on LED’s. Verify the truth table. For n. What are the different codes & their applications? 5.B.2n decoder how many i/p lines & how many o/p lines? 4.A. Make the connections as per the circuit diagram . Using 3:8 decoder and associated logic. RESULT:.PROCEDURE :1. QUESTIONS:1. What are the applications of decoder? 2. What are code converters? 6. implement a full adder? 9.
3 .2 and 3 for various inputs A0 . A3 and B0 . 2. which compares two signals A and B and generates three logical outputs. A=B and A<B . whether A > B.To study the operation of 4-bit Magnitude Comparator using Ic7485. A=B .from the logic input switches. B1 . and A<B on logic indicators. The A = B Input must be held high for proper compare operation. Pin 3 of IC 7485 should be at logic 1 to enable compare operation. Apparatus :. Power supply . 2 . B2 . 4 . B1 . A2 . which compares two 4-bit words . Observe the output A>B. A2 . A = B. Theory :Magnitude Comparator is a logical circuit . or A < B . Connect the circuit as shown in fig. Feed the 4-bit binary words A0. A3 and B0 . A1 . B2 . IC7485 4-bit Comparator kit. The outputs must be 1 or 0 respectively.A1 . B3 and observe the outputs at A>B .1 . 67 . CIRCUIT DIGRAM: PROCEDURE: 1. Repeat the steps 1 . IC 7485 is a high speed 4-bit Magnitude comparator .EXPERIMENT – 05 4 – BIT COMPARATOR 74LS85 Aim:. B3 .
Design a 2 bit comparator using a single Logic gates? 9.bit Magnitude comparator using IC 7485 QUESTIONS : 1. and one gate? 8. What are different arithmetic comparisons? 5.VERIFICATION TABLE: RESULT: Verified the operation of the 4. What are the applications of Comparator? 3. Design a 24 bit comparator using a six numbers of IC 7485? 68 . What is Comparator? 2. Design a 5 bit comparator using a single IC 7485. Design a 8 bit comparator using a two numbers of IC 7485? 10. Which logic is used as 1 bit comparator? 4. Can we use subtractor & divider as comparators? 6. What is the significance of 74 on IC’s? 7.
Knowledge of IC 74151 and IC 74LS155 pin diagram. Knowledge of basic operation of Multiplexer and Demultiplexer. CONNECTION DIAGRAM: TRUTH TABLE: 69 . Draw the internal diagram of IC 74151 and IC 74LS155. 4. Must know the data sheet of IC 74151 and IC 74LS155. 2. 2.EXPERIMENT – 06 8X1 MULTIPLEXER (74151) AND 2X4 DEMULTIPLEXER(74155) AIM: To verify the truth table of a given 8 to 1 Multiplexer and 2 to 4 De-Multiplexer using IC 74151 and IC74155. 3. Connecting patch chords. 8 to 1 Multiplexer Trainer kit . PRELAB: 1. 8X1 MULTIPLEXER (74151) APPARATUS: 1.
Apply logic 1 to I0 input (pin 4) by using the switch. 4. Apply logic 0 to I0 70 . By using pulsar switch reset the control signals (Q2 Q1 Q0 ) to 0 0 0 3.LOGIC DIAGRAM: PROCEDURE: 1. Switch on the trainer by connecting power chord to the AC mains 2. Connect the output terminals (pin 5) to the output LEC indicator. The output LED indicator glows 5.
? 71 . 2X4 DEMULTIPLEXER(74155) APPARATUS: 1. 8. QUESTIONS: 1.gry code connecter using 8:1 muxes? 10. What are the applications of multiplexer & demultiplexer? 3. What is the difference between multiplexer & demultiplexer? 4. How to get higher order multiplexers? 6. Verify the truth table by changing the control 3 signal states using pulsar switch from 000 to 111. 2. The output LEC indicator is off.input (pin 4) by using the switch. 9. Implement a 8:1 mux using 4:1 muxes?. 7. Implement full subtractor using demux?. In 2n to 1 multiplexer how many selection lines are there? 5. Connecting patch chords. What is multiplexer & demultiplexer? 2. Design a BCD-to. Draw and explain the design of a32:1 mux using 8:1 MUX and 4:1 MUX. Design full adder using 8:1 Mux Ics?. PIN DIAGRAM: LOGIC SYMBOL: Vcc 16 2C 15 2G 14 A 13 2Y3 12 2Y2 11 2Y1 10 2Y0 9 2 1G 1 1C 13 3 14 15 A B 2G 2C 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 7 6 5 4 9 10 11 12 2C 2G A 2Y3 2Y2 2Y1 2Y0 1Y0 1C 1G B 74155/74156 1Y3 1Y2 1Y1 1 1C 2 1G 3 B 4 1Y3 5 1Y2 6 1Y1 7 1Y0 8 Gnd 74155/74156 RESULT: The truth table of 8 to 1 multiplexer and 2 to 4 Demultiplexer has been verified. 6. 2 to 4 Demultiplexer Trainer kit .
like a Chip Select 72 .e. PIN DIAGRAM: OPERATION:• RAM IC 7489 is 16 words x 4-bit Read/Write Memory. • The memory Enable pin is used to select 1. APPARATUS: . 2. • The Truth Table for the RAM IC 74189 is given below. Connecting wires.EXPERIMENT – 07 & 08 STUDY OF RAM IC 74189 AIM: To study the operation of the RAM Ic7489.of-n ICs i.1. RAM IC 74189 Trainer kits.
the content in the new location is also replaced with 0h. This is to indicate that the content is 0h. 8. Assume that the following data has to be written on to the RAM. 1. Set the desired address (any address at random) using the address bit switches. Write Operation: 1.The RAM IC 7489 does not come with a ‘ Clear Memory signal. Position the ‘ Stack/Queue’ switch in the ‘ Queue’ position. Set the data bits to 0h (clearing the content) 7. 3. but not always. Position the ’ Read/Write ‘ switch in the ’ Write ’ position to enable the entry of data in to the RAM. 5. Observe that the LEDs (D3 to D0) glow. data entry (Write operation) and data verification (Read operation). Position the ‘Set Address’ switch in the ‘1’ position to allow random access of memory. This means that it will lose the data stored in it. The address and data are given in the hexadecimal format. Position the ‘ Increment/Decrement ‘ switch in the ‘Increment’ position. 6. 7. The ‘ Read/Write ‘ switch is used to write data on to the RAM. The memory has to be cleared manually.signal. However. Refer the truth table above and observe that the data outputs of the RAM will be compliments of the data inputs. • The address lines are given through an up /down counter with preset capability. Set the address bits to 0h (first byte in the memory) 4. 2. the memory enable pin is permanently held low. • The set address switch is held high to allow the user choose any location in the RAM. 73 . 4. PROCEDURE: This experiment has 3 stages – Clearing the memory. 9. 8. 10. Press the ‘Clock’ to increment the counter to the next address. • The address and data bits are used to set an address and enter the data. Position the ’ Read/Write ‘ switch in the ’ Write ’ position to write data on to the memory. This is because the data is written on to the RAM. Position the ‘Stack/Queue’ switch in the ‘ Queue’position. 3. and the data bits are set to the 0h. this dose not means that the content of the memory becomes 0h. For simply city. Set the desired data (refer table for the data to be entered in each location) using the data bit switches. 6. CLEARING THE MEMORY: The RAM IC 7489 is a volatile memory. As the ‘Read /Write ‘ switch is already in the ‘Write’ position. using the address bits. Repeat step 8 until the data in all the memory locations have been cleared. Position the ‘Set Address’ switch in the ‘1’ position. 2. Observe that the data is indicated by the LEDs (D3 toD0). on loss of power. Position the ‘Set Address’ switch in the ‘0’ position to disable random access and enable the counter. Also observe that the data is indicated by the data outputs is the compliment of the data input (refer truth table condition ME =L and WE=L) . 5.
9. 2. Which can be used as 1-bit memory? 6. 6. Position Read/Write ‘ switch in the ’ Read’ position. 4. What are sequential access memories? 10. 4. to disable unauthorized entry of data. 2. make a note of the location where data is entered. What are the parameters of the RAM? 8. 7. to disable data entry. Position the ’ Read/Write ‘ switch in the ’ Read’ position. 3. This is to make sure that we are not re –entering data in the same location. Observe that the data entered in the location is indicated by the LEDs (D3 toD0). RESULT: Operation of the RAM Ic7489 has been verified. 5. Position the ‘Stack/Queue’ switch in the ‘Queue’ position. After each data entry. 12. 3. What are charge-coupled devices? 74 . What is the RAM? . What are the different types of the ROM? . Set the desired address (any address at random). Position the ‘Set Address’ switch in the ‘0’ position to allow random access of memory. Repeat steps 4 and 5 until data has been entered in all the addresses listed in the above table 11. 10. This completes data entry. What is refreshing of memory? And where it is required? 9. This is because the data was written during the data entry procedure. QUESTIONS: 1. What is the difference between static RAM &dynamic RAM? 5. READ OPERATION: 1. Give the applications of the RAM? . What is the difference between RAM &ROM? . Also observe that the data indicated by the data out puts is the compliment of the data input (refer truth table condition ME=L and WE=H).
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