# Pass-Transistor Logic

B Switch Network B Out A Out B

Inputs

• N transistors • No static consumption

NMOS-only switch C=5V A=5V B CL A=5V Mn M1 C=5V M2 B VB does not pull up to 5V. but 5V .VTN Threshold voltage loss causes static power consumption .

Solution 1: Transmission Gate C A C B A C B C C=5V A=5V B CL C=0V .

0 .2 Rp R (Ohm) 10000.0 1.0 Req 0.0 Rn (W/L)p =(W/L)n = 20000.0 0.8/1.0 1.Resistance of Transmission Gate 30000.0 5.0 4.0 2.0 Vout 3.

Pass-Transistor Based Multiplexer S VDD S VDD S A M2 S M1 F B S GND In1 S S In2 .

Transmission Gate XOR B B M2 A M1 B B A F M3/M4 .

Delay in Transmission Gate Networks 5 In 0 V1 Vi-1 C 0 (a) Req In V1 C Req Req Vn-1 C Req 5 Vi C 5 Vi+1 0 C Vn-1 C 5 Vn 0 C Vi C Vi+1 C Vn C (b) m Req In C CC C C CC C Req Req Req Req Req (c) .

Elmore Delay (Chapter 8) Vin R1 C1 1 R2 C2 2 Ri-1 Ci-1 i-1 Ri Ci i RN CN N Assume All internal nodes are precharged to VDD and a step voltage is applied at the input Vin N N = N N i  R i  Cj =  C i  R j i=1 j=i i=1 j=1 .

Delay Optimization .

Transmission Gate Full Adder P VDD A A B VDD Ci Ci A Setup A P A P B Ci P Ci P A P Ci P VDD S Sum Generation VDD Co Carry Generation .

Larger Capacitance • Other approaches: reduced threshold NMOS .(2) NMOS Only Logic: Level Restoring Transistor VDD Level Restorer Mr B A Mn X M1 M2 Out VDD • Advantage: Full Swing • Disadvantage: More Complex.

00 2 t (nsec) 4 6 (a) Output node (b) Intermediate node X .0 1.0 1.0 Vout (V) 5.Level Restoring Transistor 5.0 -1.00 2 t (nsec) 4 6 -1.0 with VB 3.0 without VX with without 3.

Solution 3: Single Transistor Pass Gate with VT=0 VDD 0V VDD 5V VDD 0V Out 5V WATCH OUT FOR LEAKAGE CURRENTS .

Complimentary Pass Transistor Logic A A B B Pass-Transistor Network F (a) A A B B Inverse Pass-Transistor Network F B B B B B B A B A B AND/NAND F=AB F=AB A B A B OR/NOR F=A+B F=A+B A A A A EXOR/NEXOR F=AÝ F=A Ý (b) .

4 Input NAND in CPL .