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3D IC Technology Delivers The Total Package
Roger Allan | Contributing EDITOR
Burgeoning market demands for cost-effective, higher-density smaller packages bank their hopes on a flurry of recent advances made in materials, processing procedures, and interconnects, as well as a greater variety of packaging approaches.
never-ending parade of refinements to IC packaging gives engineers more choices than ever to meet their design requirements. With more radical approaches lurking on the horizon, that mix will become even richer. Today, though, squeezing more functions into smaller spaces at a lower cost dominates, leading designers to stack more chips atop each other. Thus, we’re seeing the rapid ascent of 3D IC packaging. The impetus behind 3D IC technology’s rise comes from the consumer market’s use of more sophisticated interconnects to connect silicon chips and wafers. These wafers contain chips with continually shrinking line dimensions. To scale down semiconductor ICs, finer line drawings are made on 300-mm wafers. Although most mass-produced ICs today are based on 55-nm design nodes or less, these design rules will shrink to 38 nm or smaller, and then down to 27 nm by 2013, according to forecasts by market forecaster VLSI Research Inc. (Fig. 1).
300-mm wafer forecast (thousands of wafers/week)
1200 1000 800 600 400 200 0 2009 2010 2011 2012 2013 Wafer fabrication on advanced technology nodes >27 nm >27 nm but <38 nm ≥38 nm but <55 nm
These downscaled IC designs accelerate the need for highdensity, cost-effective manufacturing and packaging techniques, which will invariably challenge IC manufacturers to minimize the higher cost of capital equipment investments. Many 3D applications still use traditional ball-grid-array (BGA), quad flat no-lead (QFN), lead-grid-array (LGA), and small-outline transistor (SOT) packages. However, more are migrating to two main approaches: fan-out wafer-level chipscale packaging (WLCSP) and embedded-die packaging. Presently, fan-out WLCSP is finding homes in high-pincount (more than 120 pins) applications that use BGAs. Embedded-die technology favors the use of lower-pin-count applications that embed chips and discrete components into printed-circuit-board (PCB) laminates and use microelectromechanical-system (MEMS) ICs (Fig. 2). Researchers at Texas Instruments believe that WLCSP is heading toward a standardized package configuration. It could include a combination of WLCSP ICs, MEMS ICs, and passive components interconnected using through silicon vias (TSVs). The TSV’s bottom layer can be an active WLCSP device, an interposer only, or an integrated passive interposer. The top layer may be an IC, a MEMS device, or a discrete component (Fig. 3). No matter the package type, though, as pin counts and signal frequencies increase, the need to pre-plan the package option becomes more critical. For example, a wire-bonded package with many connections may require more power-supply buffers on the chip due to high levels of inductance. The type of bump, pad, and solder ball placement also can significantly impact signal integrity.
TSVs: Hype Or Reality?
1. Future packaging trends include greater use of 300-mm wafers as IC design nodes shrink further. This will drive the adoption of 3D ICs for greater chip densities. (courtesy of VLSI Research)
TSV technology is not a packaging technology solution, per se. It’s simply an important tool that allows semiconductor die and wafers to interconnect to each other at higher levels of density. In that respect, it’s an important step within the larger IC packaging world. But TSVs aren’t the only answer to 3D packaging advances. They represent just one part of an unfolding array of materials, processing, and packaging developments. In fact, 3D chips that employ TSV interconnects aren’t yet ready for large volume productions. Despite making some progress, they’re limited to mainly CMOS image sensors, some MEMS devices, and, to some degree, power amplifiers. More than 90% of IC chips are packaged using tried-and-true wire-bonding means. Speaking at this year’s ConFab Conference, Mario A. Bolanos, manager of strategic packaging research and external collaboration at Texas Instruments, outlined a number of challenges facing the use of TSVs in 3D chips. These include a
These typi.no-lead (QFN) packages. ICs. After bonding. insuf. as well as dealing with stress effects issues. copper pillars. and (WLP) using through-silicon vias (TSVs) together with embedding chips into various substrates.A. including water and environmenrity of the wafer structure. which provides intellectual property (IP) for 3D integration technology. Given the fragility of such very thin wafers. 3.(EPFL) and the Swiss Federal Institute of Technology (ETH). 5). Alchimer modeled TSV costs and space Fan-out WLP consumption using an existing 3D stack Integrated for mobile applications. by means of microfluidic MEMS technology (Fig. Future 3D IC packaging approaches will embody techniques such as wafer-level packaging interconnected by about 1000 TSVs. Recent packaging developments include the use of TSVs for interconnects. has demon3D WLP 3D IC strated that TSVs with aspect ratios (height with TSV to width) of 20:1 can save IC chipmakers Flip-chip MEMS more than $700 per 300-mm wafer compared with aspect ratios of 5:1 (see the table). along with Switzerland’s École 0812EE_F2 lack of electronic design automation (EDA) tools. The collaborative effort. 10:1. typically sities ranging from 100 to 10. and other components will be joined by passive make the 3D packaging challenge even more difficult. elec. considering the fabrication. the processor die was calculated for aspect (courtesy of Yolé Développment) ratios of 5:1.surfaces will pipe coolants. ficient yield and reliability data involving thermal issues. and a DRAM chip made PCB on a 65-nm process node. Progress marches on for a number is true regarding standardization of the TSV assignment of of flip-chip wafer-bumping technologies.is developing micro-cooling techniques for 3D ICs. They see a threefold to fourfold increase in costs when going from 45-nm design nodes to 32. a NAND memory chip. Nanowafer bonding and de-bonding equipment to ensure the integ. system-in-package (SiP). the wafer undergoes a TSV circuit in the form of steam. cal steps result in higher yield levels for more cost-effective Wire Bonding And Flip Chip mass production.. If enough IC manufacturers work on these of eutectic flip-chip bumping. This was accomplished by reducing the die area need for interconnection. and mask costs.and 28-nm designs. known as CMOSAIC. particularly at high processing tally friendly refrigerants. which are built on silicon wafers 3D stack architecture of multiple cores with interconnect densome 750 µm thick. process. Electronic Design Go To www. High process temperatures greater package-on-package (PoP) methods. a provider of nanometric deposition films used in semiconductor IC interconnects. (courtesy of Texas Instruments) where TSV technology steps in. followed by a de-bonding step.000 connections/mm2. than 200°C to 300°C aren’t feasible for the economic imple. many semiconductor IC experts view the industry at a crossroads of having to choose 2D (planar) and 3D WLCSP with TSV designs. and lead-free issues. The stack includpassive devices ed a low-power microprocessor. design.. is considering a Unlike conventional ICs. IBM. MEMS devices. This is components using wafer-level chip-scale packaging (WLCSP) and through0812EE_F3 silicon vias. including the use wafer locations. Nevertheless.state. where it’s pumped back to the chip for cooling.to absorb the heat and draw it away. yield losses and known-good die (KGD) data. Once the liquid leaves the tion processes. Wire-bonding and flip-chip interconnect technologies cerCurrently. more progress can be made on expanding the roles of soldering. there’s a lack of TSV standards on bonding and process temperatures and related reliability levels. and 20:1. mentation of TSVs. Ziptronix Inc. within a few millimeters of the chip temperatures and stresses during the etching and metalliza. The IBM/Swiss team plans to design microchannels with about 100 µm thick or less. Much needed improvements in lithography and chemical vapor polishing.EngineeringEssentials Fan-out WLP/chip embedding in substrates France’s Alchimer S. The chips are 2.com 3 . using tromigration and thermo-mechanical reliability. MEMS.electronicdesign. connect (DBI) technology to Raytheon Vision Systems. licensed its direct-bond-interIC. The company says that its low-temperature oxide bonding DBI Passive technology is a cost-effective solution for 3D ICs (Fig. and variations thereof. and compound TSVs. 4). the need arises for highly specialized temporary single-phase liquid and two-phase cooling systems. The same tainly aren’t sitting idle. a condenser returns it to a liquid back-side process. the need for Polytechnique Fédérale de Lausanne cost-effective manufacturing equipment and processes. etc. 3D ICs require very thin wafers.
which involves IBM and two Swiss partners. giving designers much greater freedom in creating attractive designs that satisfy the diverse styles and thin-focused tastes to today’s consumers.4 mm to 0.4 mm for the bottom of the PoP structure and 0. This is part of the CMOSAIC project.6-mm high.5 M icr el CMOS circuitry TSV 0. (courtesy of Ziptronix) At the packaging level. in 2003. the new packaging technology can be adapted to other multichip packages (MCPs) configured as SiPs and PoPs.80% 0812EE_F5 Average TSV density = 16 TSVs/mm2. Then the redistribution layer on top is etched from the copper.5 0. ay er er Pr oc so es r mo rl yl ay M e 3D stack An g alo cir cu s its c RF irc uit Silicon Consumption As A Function Of TSV Aspect Ratio TSV aspect ratio 5:1 10:1 20:1 nn TSV size (diameter × depth. Using BGA packages in stacked-die configurations with wire bonds is nearly a decades-old practice. “This packaging development provides the best solution for combining higher density with multifunctionality in current mobile product designs. Certain 3D approaches like the PoP concept warrant special attention when it comes to high-density and high-functionality handheld products. Samsung Electronics Ltd. according to the company. Liquids using MEMS microchannels will perform the cooling. µm) 40 × 20 20 × 200 Keep-out area (2. multi-die.5 mm for the top.10% 10 × 200 2. STMicroelectronics demonstrated a stack of 10 dice using BGAs.5 × diameter. Designers must carefully consider two issues: thermal cycling and drop-test reliability performance. Samsung devised an ultra-thinning technology to overcome the conventional technology limits of an IC chip’s resistance to external pressure for thicknesses under 30 µm. die size = 8 × 8 mm Courtesy of Alchimer S. Designed initially for 32-Gbyte memory sizes.9 12. Key to the package’s creation is the use of 30-nm NAND flash-memory chips. This set of memory die uses Ziptronix’s direct-bond interconnect (DBI) low-temperature oxide-bonding process for 3D ICs. followed by an interconnect metallization over the memory die edge. vice president for Samsung’s package development team. then adhesively bonding it to a thin substrate. The resin is cured. memory. µm) Total TSV footprint (mm2) Footprint relative to IC area 100 7.” says Tae Gyeong Chung. eight-chip package for use in high-density memory applications. 3D configurations have been well known for many years. Future 3D IC stacks may contain processor. and analog and RF circuitry. and interconnect vias are laser-drilled down to the contact pads and plated with a metal. This is all overlaid with resin-coated copper (about 80 µm for the resin layer and 5 µm for the copper surface). Electrical contact between memory and logic elements is made via etching memory and logic bond pads. For example.5 mm to 0. This becomes more critical as we move from interconnect pitches of 0.3% 50 2 3. it features half the thickness of conventional eight-chip memory stacks and delivers a 40% thinner and lighter memory solu- tion for high-density multimedia handsets and other mobile devices. each measuring just 15 µm thick. In addition. Germany’s Fraunhofer IZM has developed a chip-inpolymer process that imparts shock and vibration protection to the chip and lends itself to shorter interconnect distances to enhance the chip’s performance. 5. (courtesy of the École Polytechnique Fédérale de Lausanne) oc ha Electronic Design 4 .EngineeringEssentials 4. Both are functions of the packaging materials’ quality and reliability. The process starts by thinning the chip. Market developments are also shaking up the QFN package arena. logic.A. has unveiled a 0. The die are bonded face down to the face-up logic wafer and thinned to about 10 µm. a record at the time. all of which are interconnected with through-silicon vias (TSVs).
Gold wire Mold resin Gold wire Don’t Be Intimidated By Low-Power RF System Design Louis E. which includes board (PWB) inside a multi-layer PWB using unique buried bumped interconnections. The use of polymer-embedded QFNs. which are formed by screen printing. Malaysia’s Unisem Berhad has unveiled a high-density lead. PWBs interconnect between arbiassembly practice. The (PWB) inside a multi-layer PWB.improve the thermal-cycling and drop-test reliability shortframe technology. The 700 pins inside PWBs is scheduled for this year. alloys. 6).by 5-mm chip that’s thinned to about 50 µm. Li. 72-lead QFN pack. But what if you aren’t a wireless engineer? Don’t worry. trical-conductivity paste. Half-etching Fraunhofer and 10 other European indus. The company says that it offers materials will help to advance 3D ICs using PoPs.electronicdesign. and excellent soldermance IC chips that are wire-bonded to a printed wiring board ability over a range of surface finishes. resulting in lower manuniches held by other types of packages. Although PoP a cost-effective replacement for a two-layer FPGA package. Dai Nippon Printing has successfully embedded high-perfor. It is also suits a broad range of packaging applications. The cost is reasonable. and you add unexpected value and flexibility to the product. It also reduces the amount of gold wires for connections. Half-etching the base metal of the leadframe and making its and high-frequency compatibility. is to and the leadframe it’s attached to. which offer advantages over SnAgCu materials. citing unique buried bumped technology is based on the use of PCB manufacturing and interconnections for its success. Mass production of ICs with more than contains a 5.com 5 . is part of the 6. the potential exists. 0812EE_F6 The goal of HERMES. to allow for more functional integration and higher density.com dding wireless connectivity to any product has never been easy. These technologies are all proven and readily available in chip or module form. high-power capability.CSPs via in-pad joints. The 84 I/Os on the and passive components can be handled. good coalescence. (courtesy advance the embedding of chips and of Dai Nippon Printing) components. thin appliances housing microcontroller ICs. Both active package itself measures 100 by 100 mm. Multicore LF620 lead-free solder paste “This package offers a better footprint with higher I/O density and better thermal and electrical performance. the leadframe grid array (LFGA). Fraunhofer the leadframe it’s attached to. The embedded QFN facturing costs (Fig.need for a lead-free compound to handle large high-density 3D age in a body size of 5. The Henkel Corp. The no-clean thinner and. The QFN package was selected because it’s more common in inner leads longer will close the distance between the chip and small. offers a much better yield at halide-free and lead-free material is formulated with a new activator chemistry. trary layers (via hole connections) with bumps made of high-elechighlighting fine-pitch interconnection. so it exhibits extremely low voiding in front-end assembly. it can house a 10.L.5 mm2. without the need for specialized equipment or other delays.frenzel@penton. Work is underway to develop epoxy flux materials that chip are at a 100-µm pitch (400 µm on the package). as well as on standard available silicon dies. even when a wireless solution doesn’t seem to make sense. it has shorter wire-bond lengths. the package’s developer. there’s a In addition. as well as drastically reduce the researchers believe that QFNs will take over many application amount of gold wires for connections.” says T. Such BGA-comparable densities. that offers comings of conventional tin solder copper (SnAgCu). manufacturing employs commonly used tin-lead (SnPb) solder Compared to a QFN package. However. Selecting a Technology The table lists a marvelous collection of wireless options. most importantly. PoP structures for consumer electronics products.the base metal of the leadframe and lengthening its inner leads shrinks the distance between the chip trial and academic organizations. both active and passive. Dai Nippon Printing embedded high-performance IC chips can be wire-bonded to a printed wiring HERMES project. the wireless chip and module companies have made such connectivity a snap. because in many A cases.by 10-mm.EngineeringEssentials This process has been optimized in commercial production of standard packages like QFNs. No license is required since most operate in Electronic Design Go To www. Frenzel | Communications Editor lou. Land Die pad Silicon chip Land Die pad Silicon chip essentially quad packs with no leads with the leads being replaced by pads on the chip’s bottom surface.
It also is the fastest. The table only provides the main options and enough information to get you started. It offers a data rate of 62. used in home automation. because you can optimize the design to your needs rather than adapt to some existing overly complex protocol. the battery or other power.5 kbits/s and has a range of 10 to 50 m. but it’s complex and may consume too much power. but that’s expensive and takes time. Cypress Semiconductor’s proprietary WirelessUSB option operates in the 2. Factor in some rework time if you fail the tests. With solid high-frequency or RF experience.or 915-MHz chips or modules. These cellphone modules use available cellular network data services like GRPS or EDGE in GSM networks (AT&T and T-Mobile) or 1xRTT and EV-DO in cdma2000 networks (Sprint and Verizon). operates on 908. the first step should be to estimate your path loss. and electromagnetic interference/ electromagnetic compliance (EMI/EMC) test gear with antennas and probes. It offers a range of up to about 30 m with data-rate options of 9600 bits/s or 40 kbits/s. too (see “Wireless In The Works” at www.4 standard. Considerations and Recommendations If longer range and reliability are top priorities. you can play around with things like transmitter power output. Once you know your path loss. You will need to do the interfacing yourself and sign up with a carrier or an intermediary company that lines up and administers cellular connections. When considering wireless for your design. For very long-haul applications that require reliability. Any product you design will have to be tested to conform to the FCC Part 15 standards. and 868. and cable Build vs. Lower data rates also survive better in high-noise environments. Some of the wireless standards have relatively complex protocols to fit special applications. ED Online 21847). which doesn’t include the mesh or other features. Lower data rates will typically result in a more reliable link.4 GHz. and its mesh-networking option makes it a good choice if a large network of nodes must be monitored or controlled. The FreeWave MM2-HS-T 900MHz radio targets embedded military and industrial applications.com. scientific and medical (ISM) band products using 433.11 is designed for local-area-network (LAN) connections and is relatively easy to interface to Ethernet. With less experience. Mesh capability is in the mix. This is strictly physics.EngineeringEssentials the unlicensed spectrum.gov. receiver sensitivity. It’s a good way to go.applications. Almost always. When self-designing. making it a good option for less complex projects. Most modules are pretested. except for Ultra-Wideband (UWB) and the 60-GHz standard. The tricky part is the layout. which will be considerably greater at lower frequencies. Analog Devices’ ISM band radio antenna gains.fcc. So. 2. stay with the lower frequencies—915 MHz is far better than 2. If you’re looking for something simple. For a more in-depth look. Its underlying base is the IEEE 802.42 MHz in Europe. consider doing the design on your own. this option offers greater reliability and longer range. To estiDeciding whether to build or buy is a crucial control as well as smart-metering mate the path loss between the transmitter step when it comes to adding wireless. you won’t be sorry when you need to transmit a few kilometers or miles. As for data rates. try industrial. Wi-Fi 802. It’s a complex protocol that can handle some sophisticated operations. Many products require you to invent your own protocol. Still. the transmit/receive switch. It’s gen. 1. Buy chips suit home automation and losses to zero in on hardware needs. The only downside is antenna size. you should have a copy of Part 15 handy. try: Electronic Design . Your analysis of the radiowave path is essential for a solid and reliable link. It’s widely available in chip or module form.4-GHz band and targets human interface devices (HIDs) like keyboards and mice. check out the organizations and trade associations associated with each standard. it will require higher power and the highest possible directional gain antennas.S.42 MHz in the U.electronicdesign. erally a matter of experience. and packaging. field strength meter. think slow. and aggravation. CFR 47. and 433 MHz is even better. consider a machine-to-machine (M2M) option. For example. Primary design issues will include antenna selection. The Z-Wave proprietary standard from Sigma Design Zensys. Some vendors supply the software tools for that task. grab any reference designs available from your chip supplier to save time. and receiver. impedance matching with the antenna. Arm yourself with the right equipment.S. They also operate under the rules and regulations in Part 15 of U. so it pretty much comes down to the packaging and interfacing with the rest of the product. You can find it at www. Most modules will take care of these elements. An outside firm also could perform the testing. Though more expensive. you’ll start with an available chip. Some basic rules of thumb will give you a good approximate figure to use. it’s probably better to buy existing modules or boards. money. Though not impossible at 2. especially the spectrum analyzer. Factoring in the testing time and cost is another essential design step.15.4 GHz. You can gain distance by dropping the data rate. RF power meters. ZigBee is great for industrial and commercial monitoring and control.
Another formula is: dB loss = 20log(4π/λ) + 20log(d) Wavelength (λ) and range or distance are both in meters. The loss increases about 6 dB for each doubling of the distance. 418. and the range or distance (d) is in miles. add the fade margin. perhaps 5 dB.56 MHz 900 to 928 MHz. GR is the receive antenna gain. A fade margin figure is just a guess. It is usually given in dB. Some conservative designers say it should be 15 dB. In most installations. The cable loss at UHF and microwave frequencies is surprisingly high. The formula also indicates why lower frequency (longer wavelength) provides greater range (λ = 300/fMHz). audio. while others say 10 dB is acceptable. This is 1. seek out special lower-loss cable. λ is the wavelength in meters. Receiver sensitivity also is usually quoted in dBm. 20 dBm (100 mW). and d is the distance in meters.64 for a dipole or ground plane antenna. BPSK/QPSK ASK OFDM OFDM DSSS/CCK. this is free space loss without obstructions. cell-phone transactions Industrial and factory automation Tracking. Also. sensor data Short data transfer Industrial monitoring and control. Add that to your path loss and adjust everything else accordingly. 54.11a/b/g/n ZigBee/ 802. shipping Video. This is especially critical when using antennas on towers where the cable run could be long. 13. you may get away with less. PT is the transmit power in watts. The transmit and receive gains are power ratios. is usually given in dBm. As a result. CDMA 1xRTT ASK DSSS. Both formulas deliver approximately the same figures. Typical figures are in the –70. One last thing to factor in is cable loss. FSK.1 to 6 GHz 2. If unusual weather or other conditions aren’t expected. 433. you will use coax cable to connect the transmitter and receiver to the antennas. 2 dB for windows. GT is the transmit antenna gain. but it must be converted to a power ratio. When finalizing a path loss. and 30 dBm (1 W).4 GHz or more. So.4 10 km <1 ft Up to several miles <2 m 10 m 10 m 100 m 100 m Electronic Design Go To www. video WLAN Monitoring and control. solar events. OFDM OQPSK Main applications Cell headsets. 100+ Mbits/s 250 kbits/s Modulation FHSS/GFSK Baseband OOK/ASK. backhaul Wireless USB. transmitter power and receiver sensitivity will be sufficient to overcome these temporary conditions. 250 kbits/s <300 kbits/s 106 to 848 kbits/s 1 kbit/s to 2 Mbits/s <100 kbits/s 3 Gbits/s 480 Mbits/s 11. and 10 dB for exterior structure walls. some corrective figures must be added in.EngineeringEssentials dB loss = 37 dB + 20log(f) + 20log(d) The frequency of operation (f) is in megahertz. 2. It costs a bit more. If obstructions are involved. 915 MHz 60 GHz 3. Any directional antenna like a Yagi or patch will have directional gain. Transmitter output power. You Low-Power. or unusual noise and interference. 2. Remember. DSSS w/BPSK/QPSK GSM/EDGE.electronicdesign. Short-Range Wireless Technologies for Data Transmission Technology Bluetooth IR ISM Frequency 2. 902 to 928 MHz. sensor networks M2M NFC Proprietary RFID 60 GHz UWB Wi-Fi. be sure to minimize the cable length. Another handy formula to help estimate your needs is the Friis formula: PR = PTGRGTλ2 /(16π2d2) PR is the received power in watts. 802. another key figure. telemetry Remote facilities monitoring Credit card. This “fudge factor” helps ensure good link reliability under severe weather. Average loss figures are 3 dB for walls. Some common figures are 0 dBm (1 mW).4 GHz Cellular bands 13.56.4 and 5 GHz 2.to –120-dBm range.4 GHz 125 kHz.4 GHz 875 nm 315.15. It can be several dB per foot at 2. This is the smallest signal that the receiver can resolve and demodulate.4 GHz Maximum range 10 m <1m 10 km Maximum rate 3 Mbits/s 16 Mbits/s 1 to 115 kbits/s. 10 dBm (10 mW). but coax cable with a loss of less than 1 dB per foot is available if you shop around.com 7 .
tions. Two design issues remain—the antenna and its standard L. making it a true single-chip wireless solution. design your own for everything. you may need to design the 1008EElowpower-FIGURE 3 impedance matching network between the transceiver and the This figure should be greater than the receiver sensitivity. Most chip companies will offer some recommendaplay with all of the factors to zero in on the final specifications tions that deliver proven results.indicate radiated power measured in microvolts per meter cle. as is a simple copper loop on the printed circuit board Transmit power (dBm) + transmit antenna gain (dB) + receive (PCB). Otherwise. or π LC network to do the job. There are many sources for antennas. can offset the loss with a gain antenna. A field strength meter makes the measurement at 8 Electronic Design . and smart-energy applications.4.15.768-kHz crystal oscillator Debug interface Sleep timer Sleep-mode controller 32/64/128/ 256-kbyte ﬂash 8051 CPU core Memory arbitrator 8-kbyte SRAM IRQ control ADC audio/DC 8 channels Flash write AES encryption and decryption Radio registers CSMA/CA strobe processor Radio data interface FIFO and frame control Demodulator Automatic gain control Modulator Timer 2 (IEEE 802.6 V) DCOUPL 32-MHz crystal oscillator RESET_N XOSC_Q2 XOSC_Q1 P2_4 P2_3 P2_2 P2_1 P2_0 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 Timer 1 (16 bits) USART 2 USART 1 I/O controller Direct memory access 32. T. Follow the manufacturer’s recommendations for the antenna gain (dB) – path loss (dB) – cable loss (dB) – fade best results. One final hint about testing: Part 15 uses field strength to The antenna requires a separate discussion beyond this arti. the ceramic type is popular. With all of this information. ZigBee. compute the final calculation: When building an antenna into the product. The CC2530 SoC from Texas Instruments fits 802.EngineeringEssentials Digital Analog Mixed Reset Watchdog timer High-speed RC oscillator 32-kHz RC oscillator Clock multiplexer and calibration On-chip voltage regulator Power-on reset brownout VDD (2 to 3. but it’s still optimal to most likely will come with an antenna and/or antenna suggesminimize the length and use the best cable. margin (dB) If it’s a single-chip design. impedance matching.15. RF4CE. It has an 8051 microcontroller on board. The most common is quarter-wave or half-wave vertical.4 MAC timer) Timer 3 (8 bits) Frequency synthesizer Receive chain Transmit chain Timer 4 (8 bits) RF_P RF_N 3. A wireless module (µV/m). Now antenna.
buffer memory.15. which is a close approximation.8 by 36 by 9. reduce costs. Zigernet that supports TCP. and other powerful power is consumed. and d is the distance in meters ADF7023 target these smart-grid and home/building autofrom the transmit antenna to the field strength meter antenna.integrated image rejection scheme. a fractional-N phase-locked loop (PLL). 868. pro. including automatic meter reading.6 V.frequency control (AFC) loop.It fully complies with ETSI-300-200 and has enhanced digital mance spread-spectrum and licensed radios for critical data baseband features specifically designed for the io-homecontrol transmissions. lets you convert between Studio supports both devices.8 to 3. Both radios fit many industry. and current. Other on-chip features include an extremely low-power. remote terminal units (RTUs). G is the antenna gain. packet grammable logic controllers (PLCs). The combination delivers unmatched overload immu.Wireless MBus technology for the remote reading of gas and trial monitoring and control. industrial-grade wireless security. the CC2530 combines a fully integrated. In addiAnalog Devices fit well in smart-grid and other applications tion. high-perfor. The MM2-HS-T is ideal for embedded applications that require high data rates.com 9 . and a battery-voltage monitor.6 mm and weighs 8-bit RISC communications processor. patent-pending. which is the industrum technology prevents detection and unauthorized access. and 915 MHz. 3). Its military applications where it’s necessary to transmit large power-supply range is 1.trols. 8 kbytes of RAM. medical devices. and Smart Energy applications. government. and robots and unmanned management/validation. The ADF7023 low-IF transceiver operates in the license-free ISM time. over-the-air and 256-bit AES encryption is available. Each unit can be used in a security net. and 869. high-perforoperating on the short-range ISM band for remote data mea. A mation applications. The ADF7022 and ADF7023 low-power transceivers from download to support in-system reprogramming. The TI CC430 wireless platform consists of TI radio chips.mance RF transceiver with an 8051 MCU. RF Also. for storing measure. Furthermore. such as video and long distances (up bands at 433. such as media access. The following for.performed by a microprocessor. The ADF7022 is a highly integrated frequency-shift-keying/ simplified approximation at a common FCC testing distance of Gaussian frequency-shift-keying (FSK/GFSK) transceiver 3 m with a transmit antenna gain of one is P ≈ 0.4 radios to carry IPv6 packets. The CC2530 from Texas Instruments is a true system-on-anity and sensitivity. try’s first ZigBee RF4CE-compliant protocol stack. fully 14 g (Fig. (RF4CE is the serial communications.electronicdesign. smart meters to be installed worldwide.EngineeringEssentials specified distances. and remote conensure the transmitter is within the rules. including multiple high-resolution images both transmit and receive modes. consumption and eases both the computational and memory users can send significantly more data in a shorter period of requirements of the host microprocessor. dowloadable ADIsimSRD Design mula. They operate in the 900-MHz band and use direct. and it consumes less power in amounts of data. Both radios offer RISC-based signal demodulation with lator (VCO).chip solution (SoC) tailored for IEEE 802. The ADF7022 and V is the field strength in µV/m. the company’s MSP430 16-bit embedded controller transceivers are needed for the secure and robust transmission can implement the IETF standard 6LoWPAN. repeater. and for communicating with utility computers over Thus. Applications for the ADF7022 and ADF7023 include indus. and packet retrieval to and from data vehicles. The MM2-HS-P includes industrial-grade high-speed Eth. it also determines what time and price are supporting features and peripherals (Fig. FreeWave Technologies has a line of reliable. 868. depend. Smart-grid technology not only measures how much 32/64/128/256 kbytes of flash memory. This allows the host microprocessor to remain sequence spread spectrum (DSSS).software that enables 802.electronics equipment. the device can assume complex tasks typically OEM products like sensors. FreeWave’s proprietary spread-spec.15. ment data. 1). Also. digital received signalend incorporating multi-stage surface-acoustic-wave (SAW) strength indication (RSSI). and video along with data. to monitor and conV2/120π ≈ PG/4πd2 trol energy usage.the new RemoTI stack for ZigBee RF4CE. It offers a low transmit-and-receive to 60 miles). an automatic filters. Larger memory sizes will allow for on-chip. low-power wireless devices and networks can access the Internet. the platform can implement Europe’s wireless networks. One particular hot area for RF transceivers involves utilipower and field strength: ties that are building advanced metering infrastructures. a 10-bit a matched filter and a gallium-arsenide (GaAs) FET RF front analog-to-digital converter (ADC). or master/slave unit. slave.forthcoming wireless remote-control standard for consumer work as a master. and MM2-HS-P (Ethernet interface) come ready to embed in As a result. a voltage-controlled oscilprint. temperature sensors.85 MHz in the license-free ISM band. and increase reliability for the delivery of electricity from utility companies to consumers.25. enabling longer battery life. best to save energy. The result can be converted to watts to systems. The MM2-HS-T measures 50. Analog Devices’ free. and Bee RF4CE. Electronic Design Go To www.3 V2. in power-down mode. security systems. The high-speed MM2-HS-T (TTL interface) wireless communications protocol. surement.23 Mbits/s. designed for operation at the three io-homecontrol channels of Some Example Products 868. ZigBee.) Its 64-kbyte and up versions support ing on its programming. Analysts expect more than 150 million where P is transmitter power in watts. The MM2-HS-P shares a similarly small foot. as well as data rates in 2FSK/GFSK up to 250 kbits/s.4.95. wireless networks and telemetry electric meters. which is the of this information over short distances. it significantly lowers power Thanks to the radios’ over-the-air speed of 1.
which may involve modulation. The TX and RX simply make the information signals to be transmitted compatible with the medium. while some systems require modulation. consider the information to be non-return-to-zero (NRZ) binary data. and a transmission medium (Fig. Encoding may be optional in this simplified model of a communications system. Radio communications also started out digitally. Though the principles are generally well known. That same bit Full duplex means simultaneous (or at least con0909EE_F3 stream. has gone digital. 0 multiplexing) techniques. current) TX and RX. lectronic communications began as digital technology with Samuel Morse’s invention of the telegraph in 1845. 0909EE_F2 Communications may also be synchronous or asynchronous. ﬁber. Here. found only in the legacy telephone system. 3. when transmitted in a four-level PAM format. Communications falls into one of two categories—baseband or broadband. 1V half duplex.EngineeringEssentials Digital Communications: The ABCs Of Ones And Zeroes Louis E. Nearly everything else. In this article. but cellular data is 2. and issues. Baseband is the transmission of data directly over the medium itself. Then analog communications emerged with the telephone and amplitude-modulation (AM) radio. The brief dots and dashes of his famous code were the binary ones and zeroes of the current through the long telegraph wires. Cable TV and DSL are probably the best examples. with Morse code producing the off and on transmission of continuous-wave spark-gap pulses. simply. The bit time in this NRZ binary data signal determines data rate as 1/t. or. Frenzel | Communications EDITOR lou. The medium could be copper cable like unshielded twisted pair (UTP) or coax. CB/family and shortwave radios. a receiver (RX). and some lingering two-way mobile radios. which dominated for decades. May include modulation Data in Encoding (optional) TX Medium (copper. communications links are simplex. (a) (b) Time Duplex is two-way communications. Cell phones and Internet communications are digital.com Don’t be left in the analog dust. an 8-bit serial data word in NRZ format is to be transmitted (a). amateur. 1). Half duplex uses alternating TX and RX on the same channel. broadcasting. 10 Electronic Design . In all cases. including TV. Simplex links involve 0V 11 00 10 01 Time one-way communications. also broadband. 2V 1 1 0 0 1 0 0 1 0 Furthermore. Broadband 1 implies the use of modulation (and in some cases. doubles data rate (b). such as sending serial digiOne bit interval tal data over an RS-485 or I2C link. while asynchronous methods use start and stop bits as in 3V 1 RS-232 and a few others. or full duplex. products. Noise rather than attenuation usually determines if the communications medium is reliable. the signal is greatly attenuated by the medium and noise is superimposed. Some systems use a form of coding to improve reliability. veteran members of the industry may have missed out on digital communications schooling.Avoid noise and other transmission errors using these digital modulation schemes and error-correction techniques. The Fundamentals All communications systems consist of a transmitter (TX). as in any telephone. or free space for wireless. AM and FM radio broadcasting. Wireless networks are digital. radio) RX Decoding Data out E Noise 0909EE_F1 1.frenzel@penton. Today. Noise is the main restriction on range and reliability. trends. fiber-optic cable. The original t 10-Mbit/s Ethernet was baseband. Synchronous data is clocked as 1 µs in SONET fiber-optical communications. analog is slowly fading away. Becoming familiar with the basics broadens one’s perspective on the steady stream of new communications technologies.
Also example.35/0. Networking level or binary signals. 35/tR Electronic Design Go To www. Data Rate . However. 3a). Point-to-point. For Assume we want to transmit the serial 8-bit byte (Fig. the theoretical maximum data rate The big question is how much bandwidth (B) is needed to in a 6-MHz channel is: pass a binary signal of data rate C. Therefore. two bits per level can be transmitted (Fig. the four levels (0. giving a symbol rate—also called the baud rate—of 1 Msymbol/s. This will require a minimum bandwidth of: B = 0. data rate in a noise-free channel is just half the data rate or: 3b). Shown are phase-shift keying (PSK) constellation diagrams for binary PSK (a).electronicdesign. Note that it takes just half the time to transmit the As an example.to 12 Mbits/s. Therefore: C = 1/t C = 2B(3.32)log10N or capacity C is the reciprocal of the bit time (t) (Fig. As it turns out. If multiple levels are transmitted. 2): Here. A signal with a bit time of 100 ns bandwidth of 6 MHz is as given above: has a data rate of: C = 2(6)(3.32)log10N C is the channel capacity or data rate in bits per second and For binary or two-level transmission.ai Digital communications sends bits serially—one bit after anothM indicates the number of multiple voltage levels or symer. They all don’t necessarily the data rate can be expressed as: work for all media. B = C/2 This technique is called pulse amplitude modulation (PAM). and 8PSK (c). bols transmitted. and 3 V) transmit the same byte 11001001. point-to. the baud rate is 1 Mbaud. onds (µs). but the actual bit rate is twice that. B = 0. Multiple voltage levels can be transmitted over a B is the 3-dB bandwidth in megahertz and tR is in microsec. quaternary PSK (b). a rise time of 10 ns or 0. so use the conversion where: Multiple-input multiple-output (MIMO) wireless also implements two or more parallel bit streams. Calculating the base 2 logarithm is a real such as four-pair UTP CAT 5e/6 or parallel fiber-optic cables. In this example. C = (2B)log2M 0909EE_F4. and mesh. This formula factors in the effect of Fourier theory.Versus Bandwidth Topology is also fundamental. a 6-MHz bandwidth will allow a data rate up same amount of data. 2. In any case. 1. Hartley also said that this figure holds for twomultipoint. C = 2B or 2 Mbits/s. let’s consider multilevel transmission schemes.baseband path in which each level represents two or more bits. The symbol R for rate is also used to indicate data speed.EngineeringEssentials 90º 90º 10 11 101 1 0 180º 0º 180º 001 00 (a) 270º (b) 270º 01 (c) 90º 100 110 111 0º 011 180º 0º 000 270º 010 4. you’ll often find multiple serial paths being used.32)log104 = 24 Mbits/s time (tR) of the bit pulse that determines the bandwidth: To explain this.01 µs needs a bandwidth of: assume a clock of 1 Mbit/s for a bit period of 1 µs. it’s the rise C = 2(6)(3. rings. the data rate for a t is the time for one bit interval.01 = 35 MHz B = C/2 = 1 Mbit/s/2 = 500 kHz A more precise measure is to use the Shannon-Hartley theorem. and multipoint-to-point are common. log10N is just the common log of a number N. then features buses.32)log102 = 12 Mbits/s C = 1/100 × 10–9 = 10 Mbits/s With four voltage levels.com 11 . Or the maximum possible data rate for a given bandwidth is: The time for each level or symbol is 1 µs. pain. the basic data speed log2N = (3. Each level is called a symbol. Hartley said that the least bandwidth needed for a given With four levels.
and Long-Term Evolution (LTE). The S/N physics. eight bits of data can be transmitted in 8 µs using binary data. lightning) or even the stars. analog signals are continuous. Solving for M: designated R) is the reciprocal of t. you can see how Eb/N0 is related to S/N: M = √(1 + S/N) 0100 0110 0101 0111 Take a 40-Mbit/s data rate in a 6-MHz channel. For instance. if the S/N is 100. That’s because the signal transmitted is usually during a short period. It’s a measure of the noise level and will affect the received bit error rate (BER). In a wireless link. Noise comes from many different sourcor: es. especially noise. twice the data. 0909EE_F5. while other forms of noise The S/N is a power ratio and is not measured in dB. Bandwidth narrowing obviously will affect data rate..g. C/N is usually noise. Other sources of noise include signals picked up on a cable used at baseband or after demodulation. The levels or symbols could be represented by something other than different voltage levels. but Eb/N0 usually evaluspecifically say that multiple levels or symbols can be used. Typically. Also. With four-level PAM.32)log10(1 + 1) = 6 Mbits/s come from the atmosphere (e. Using these definitions. WiMAX.broad.ai data in 4-bit groups per symbol. Impulse noise from auto 100 to 1. S/N is ate interfering signals that we treat as noise. the 40-Mbit/s rate can be achieved with 10 levels. For a given bandwidth. The 60-Hz “hum” induced by power lines is another example. Shannon later modified this basic relationship to factor in the signalto-noise ratio (S/N or SNR): 1101 1100 1110 1111 1000 1001 180º 0001 0000 1010 1011 0º 0010 0011 tion (QAM) is a combination of different voltage levels and phase shifts. This will require multiple levels or symbols: M = √(1 + 100) = 10 Theoretically. is used in digital TV as well as wireless standards like HSPA. They can be different phase shifts or frequencies or some combination of levels. 12 Electronic Design . QAM. can be transmitted in the same 8 µs. the maximum data rate in a 6-MHz channel will be: ignitions. or 16 bits. you can also express Eb/ N0 and S/N in dB. Since data capacity or rate C (sometimes Here. It’s typically pronounced as E sub b Consider that: divided by N sub zero. its frequency spectrum is This last example is why many engineers use the conserva. signals produced by mixing in nonlinear circuits credefined as the S/N of a modulated or broadband signal. that translates to the higher data rate equivalent to 4 Mbits/s. and C = 6(3. Noise can be reduced by simply filtering to limit the bandtive rule of thumb that the data rate in a channel with noise is width. Recall that quadrature amplitude modula- Eb/N0= S/N (B/R) Bandwidth Efficiency Modulation type FSK BPSK QPSK 8PSK 8QAM 16PSK 16QAM Bandwidth efficiency ≤1 1 2 3 3 4 4 Remember.32) log10M expressed in joules. M is the number of levels or symbols. and frequencies. 270º The calculations of data rate versus bandC = (B)log2(1 + S/N) 5. and the energy is averaged over that time. It’s also important to point out that noise in a digital system roughly equal to the bandwidth C = B.32) log10(1 + S/N) = 2B(3. it emanates from thermal agitation. the data rate drops to: nals coupled from one pair of conductors to another within the same cable create “crosstalk” noise. phase shifts. then Eb is P divided by R. that’s because the Shannon-Hartley formulas don’t or C/N is used for analog systems. Eb/N0 is the ratio of the energy per bit to the spectral noise density. S/N also come from semiconductors. In this constellation diagram for 16QAM. N0 is noise power N divided by bandwidth B.EngineeringEssentials 90º What this means is that for a given clock rate. Channel Impairments Data experiences many impairments during transmission. inductive kicks from motor or relay turn on or off. Eb/ N0 is often determined at the receiver input of a system using modulation. 16 width assume the presence of additive unique amplitude-phase combinations transmit white Gaussian noise (AWGN). Energy Eb is signal power (P) multiplied by bit time t C = B(3. With an S/N of 20 dB or by capacitive or inductive coupling. The energy per bit is a more appropriate measure of noise in a digital system. Intermodulation distortion creates is referred to as the carrier-to-noise ratio or C/N. If the speed through a channel with a good S/N seems to defy is treated differently from that in an analog system. which is most harmful in the front end of a receiver. ates digital systems.32)log10(1 + 100) = 40 Mbits/s power-line spikes are particularly harmful to digital signals. The C = B(3.32)log10(1 + S/N) sources are resistors and transistors. SigWith an S/N = 1 or 0 dB. the modulation of choice to achieve high data rates in narrow channels. Because noise is usually random. noise can C = 6(3.
The definition of a “good” BER depends on the application and technology. compares them. Cable attenuation is a given thanks to resistive losses. but the 10–5 to 10–12 range is a common target. In wireless systems. the most widely used methods are some form of phase-shift keying (PSK) and QAM. XOR gate To modulator Chipping signal Clock Code generator Serial data signal Error detection and correction techniques can help mitigate bit errors and improve BER. Taking advantage of special mathematical encoding. the downsides are the added complexity of the encoding and the extra transmission time needed for the extra bits. FEC will enhance the S/N. with extra coding bits added along the way. These are added to the transmitted data. Common block codes include the Hamming. which are then added to the transmission. the coding gain is 20 – 8 = 12 dB. cell phones. Signals of different frequencies are delayed by different amounts over the transmission channel. if a system needs 20 dB of S/N to achieve a BER of 10–6 without coding. and transmission-line mismatches. For instance. and turbo codes. is just the percentage of the number of error bits to the total transmitted bits over a given time period. The receiver recreates these codes. Finally. Golay. Channel impairments ultimately cause loss of signal and bit transmission errors. Block codes operate on fixed groups of data bits to be transmitted. resulting in a distorted signal. and flash drives. The result is a significantly improved BER. The widely used I/Q method of modulation in a transmitter is derived 0909EE_F6 from the digital signal processor. Nonetheless. As such. the receiver can detect the failed bits and actually correct all or most of them. Modulation Almost any modulation scheme may be used to transmit digital data. The simplest form of error 8. an effect known as “coding gain.” Coding gain is defined as the difference between the S/N values for the coded and uncoded data streams of a given BER target. Reed-Solomon is widely used. If bit errors occur. Error Coding redundancy check (CRC). hard-disk drives. But in today’s more complex critical applications. most modern communications systems go much further by using sophisticated forward error correction (FEC) techniques. a check code sum. Different modulation methods have varying Eb/N0 values and related BERs. and then identifies errors. as is a newer form of block code called the low-density parity check (LDPC). BER. It’s usually considered to be the probability of an error occurring in so many bits transmitted. the data to be transmitted is translated into a set of extra bits.electronicdesign. Dropped or changed bits introduce serious transmission errors that may make communications unreliable. which is a direct function of S/N.EngineeringEssentials Mixers I DAC sin DSP Carrier cos Q Transmitted signal DAC 6. The original data may or may not be transmitted depending on the code type. 0909EE_F8 13 Electronic Design Go To www. BCH. Of course. This overhead is easily accommodated in more contemporary IC-based communications systems. filtering effects. Another common impairment is attenuation. or cyclical arrangement. One bit error per 100. Special modes like spread spectrum and orthogonal frequency division multiplexing (OFDM) are especially well adopted in the wireless space. an automatic repeat request (ARQ) message is sent back to the transmitter and the corrupted data is retransmitted. the BER is used to indicate the quality of a transmission channel. but ARQ-less systems will typically employ some form of it. signal strength typically follows an attenuation formula proportional to the square of the distance between transmitter and receiver. delay distortion is another source of impairment. The BER improves with the use of FEC for a given value of S/N. but only 8 dB S/N when FEC is used. The many different types of FEC techniques available today fall into two groups: block codes and convolutional codes. FEC is widely used in wireless and wired networking. Noise is the most common culprit in bit errors.000 transmitted is a BER of 10–5. If errors occur. Direct sequence spread spectrum (DSSS) is produced using this basic detection is to use a parity bit. Not all systems use ARQ. and storage media such as CDs and DVDs. Convolutional codes use sophisticated algorithms. like the Viterbi. An I/Q receiver recovers data and demodulates in the digital signal 0909EE_F7 processor.com . Mixers LPF sin Received signal Carrier local oscillator cos LPF ADC ADC I DSP Q 7. and Reed-Solomon codes.
allows multiple users to share a common bandwidth. and other processing of the signal. and sent to an I/Q demodulator (Fig. or 54 Mbits/s. Plain-old binary phase-shift keying (BPSK) is a favorite scheme in which the 0 and 1 bits shift the carrier phase 180°. Frequency-shift keying (FSK). The DSP software manages the modulation. In addition. For instance. 4-ary. uses a mix of different amplitudes and phase shifts to define as many as 64 to 1024 or more different symbols. It’s generally referred to as software-defined radio (SDR). (Forms of PSK and QAM are the most common. allowing for very high data rates in a narrow bandwidth (Fig. direct sequence spread spectrum (DSSS). The narrow-band digital data (several kilohertz) is then converted to a wider bandwidth signal that occupies a wide channel. or quadrature PSK (QPSK) uses sine and cosine waves in four combinations to produce four different symbols shifted 90° apart (Fig.5 kHz 52 sub-carriers 20-MHz channel Frequency 9. The bit streams are encoded in an I/Q or inphase and quadrature format using a mixer arrangement (Fig. QAM. Spread spectrum. depending on the data rate. Beyond QPSK is what’s called M-ary PSK or M-PSK. spreading the information over a wide spectrum. each 4-bit group is represented by a phasor of a specific amplitude and phase angle (Fig. video. PSK is the most widely used. The chipping signal is coded so it’s recognized at the receiver. 12. Spread spectrum can also be achieved with frequency-hopping spread spectrum (FHSS).EngineeringEssentials Amplitude-shift keying (ASK) and on-off keying (OOK) are generated by turning the carrier off and on or by shifting it between two carrier levels. BPSK is best illustrated in a constellation diagram (Fig. These methods filter the binary pulses to limit their bandwidth and thereby reduce the sideband range. With 16 possible symbols. For instance. In most applications. a multi-frequency FSK system provides multiple symbols to boost data rate in a given bandwidth. the data signal is spread over the entire band. 48. the range must be short and the signal strength high to obtain a decent BER. Figure 8 shows how the digitized serial voice. including some filtering. Further frequency translation may be needed. it reigns as the champion of getting high data rates in small bandwidths. The data is first encoded and then 0. 7). The signal is mixed with the sine and cosine waves. most digital modulation and demodulation employs digital signal processing (DSP).288 Mbits/s. demodulation. When using 16QAM. It doubles the data rate in a given bandwidth but is very tolerant of noise. The ultimate multilevel scheme. The spread-spectrum and OFDM broadband wide-bandwidth schemes are also forms of multiplexing or multiple access. They also use coherent carriers that have no zero-crossing glitches. The OFDM configuration used in IEEE 802. Subsequently. In this configuration. It’s referred to as code division multiple access (CDMA). 4a). Today. The receiver. QPSK. That effectively multiplies the data rate by four for a given bandwidth. which is very good in noisy applications. which is employed in many cell phones. 16QAM. The bottom line is that virtually any form of modulation may be produced this way.1 10–2 FSK 10–3 Bit error rate BPSK 10–4 DPSK 10–5 10–6 10–7 OOK 16QAM Sub-carrier width/spacing 312. four bits can be transmitted per baud or symbol period.25 MHz and the chipping signal is 1. knowing the hop pattern and rate. Each subcarrier is modulated by BPSK. 6). minimum-shift keying (MSK) and Gaussian-filtered FSK are the basis for the GSM cell-phone system. 4b). Both are used for simple and less critical applications. 18. the data is transmitted in hopping periods over different randomly selected frequencies. the I/Q data is translated into analog signals by the digital-to-analog converters (DACs) and sent to the mixers. Higher-level modulation methods like 16QAM require a better signalto-noise ratio or higher Eb/N0. 4c). or 64QAM. theoretically tripling the data rate in a given bandwidth. 8PSK allows transmission of three bits per phase symbol. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Eb/N0 (dB) 10. then filtered to create the I and Q signals. Since they’re susceptible to noise. It shows an axis where each phasor represents the amplitude of the carrier and the direction represents the phase position of the carrier. Quaternary. the antenna signal is amplified. or other data is modified to produce spread spectrum. 36. These signals are digitized in analog-to-digital converters (ADCs) and sent to a digital signal processor for the final demodulation. The resulting signals are summed to create the analog RF output. has several widely used variations. where it’s mixed with the carrier or some IF sine and cosine waves.11a/g permits data rates of 6. the carrier is continuous. can 14 Electronic Design . as long as you have the right DSP code. whose software produces the 0909EE_F9 correct bit streams. the serial data is sent to an exclusive OR gate along with a much higher chipping signal. the channel bandwidth is 1. downconverted. Therefore.) At the receiver. 9. 0909EE_F10 sent to the digital signal processor. OFDM also uses a wide bandwidth to enable multiple users to access the same wide channel. It uses many phases like 8PSK and 16PSK to produce eight or 16 unique phase shifts of the carrier. Most radio architectures use this I/Q scheme and DSP. 5). Thus. In this scheme. In cell-phone cdma2000 systems.
the tradeoff is data rate against BER in a given bandwidth. 10).tuite@penton. The table compares the relative efficiencies of different modulation methods. All new cell-phone and wireless broadband systems use OFDM because of its high-speed capabilities and reliable communications qualities. However. Multiple adjacent sub-channels are designed to be orthogonal to one another.or 50-Hz frequency—the way the voltage is supposed to be created with the turbines and generators at the power house.32 (bits/s)/Hz in a 20-MHz channel. different levels of QAM produce higher data rates in the same bandwidth. Add EDGE modulation and that jumps to 1. One could say “reactive” load. Maximum throughput for an 802. One measure of this is the BER per given Eb/N0 ratio (Fig. Unfortunately. where bandwidth efficiency is just data rate divided by bandwidth or C/B.com Most of the world mandates control of current harmonics. as are most power-line technologies. or different levels of QAM are used. A receiver hears only a low noise level. Sure. Therefore. That’s “power factor. Because each data signal is uniquely encoded by a special chipping-signal code. Broadband DSL is OFDM. Reconciling Power-Factor Correction Standards Leads To Solutions Don Tuite | Analog/Power EDITOR don. parallel slower streams. Simpler modulation schemes like BPSK and QPSK produce a lower BER for a low Eb/N0. 9).11g Wi-Fi radio is 54 Mbits/s in a 20-MHz channel for a spectral efficiency of 2. They overlay one another in the channel. 10. In OFDM. Electronic Design Go To www. making the spectral efficiency 0. although a higher Eb/N0 is needed for a given BER. The most common example of FHSS is Bluetooth wireless. Special correlators and decoders in the receiver can pick out the desired signal and demodulate it. and 20 MHz. It’s one way to compare the effectiveness of modulation methods. Remember 56k dial-up modems? They achieved an amazing 56 kbits/s in a 4-kHz telephone channel.” right? But isn’t it still a matter of “real” and reactive components at 50 or 60 Hz? Yes and no. Each stream modulates a very narrow sub-channel in the main channel. And taking it to new levels. the high-speed serial data stream gets divided into multiple slower parallel data streams. Does it make a difference? here’s a tendency to think of energy on the power lines in terms of its fundamental 60. power-factor correction (PFC) has traditionally been understood in terms of adding (in general) capacitive reactance at points in the power distribution system to offset the effect of an inductive load. BPSK. Again. Spectral Efficiency Spectral efficiency is a measure of how many bits can be transmitted at a given rate over a fixed bandwidth. Modulation methods vary in the amount of data they can transmit in a given bandwidth and how much noise they can withstand. Other data signals are processed the same way and transmitted in the same channel.93 (bits/s)/ Hz.11a/g Wi-Fi system uses an OFDM scheme to transmit data rates to 54 Mbits/s in a 20-MHz channel (Fig. allowing multiple uses to share the assigned bandwidth. the popular 802. Implementing OFDM can be difficult to implement. all of the signals are scrambled and pseudorandom in nature. but historically. from 52 in Wi-Fi radios to 1024 in cell-phone systems like LTE and wireless broadband systems such as WiMAX. it’s sometimes useful to include FEC in a comparison. North America specs 0. the data on one sub-channel doesn’t produce inter-symbol interference with an adjacent channel. Typical channel widths are 5.electronicdesign. the current lags the voltage if there’s a reactive load.com 15 . With so many channels. QPSK. depending on the desired data rate and the application’s reliability requirements. which is where DSP steps in.9 power factor. Though the measure usually excludes any FEC coding.7 (bits/s)/Hz. The number of sub-channels varies with each OFDM system. To illustrate. The result is a high-speed data signal that’s spread over a wider bandwidth as multiple.EngineeringEssentials reconstruct the data and demodulate it. Each group would transmit one voice or other data signal. T In power distribution. A standard. or (bits/s)/Hz. power engineers have been most concerned with motors as loads when dealing with power factor.53 (bits/s)/Hz. and their spectral efficiency was 14 (bits/s)/Hz. it’s possible to divide the sub-channels into groups. the forthcoming LTE cell phones will have a spectral efficiency of 16. Correction could take the form of a bank of capacitors or a “synchronous condenser” (an unloaded synchronous motor). Spectral efficiency is stated in terms of bits per second per hertz of bandwidth. making them more reliable in critical applications. Spectral efficiency shows just how much data can be crammed into a narrow bandwidth with different modulation methods. digital GSM cell phone does 104 kbits/s in a 200-kHz channel. that conceptualization is a bit oversimplified.
and excite eddy currents exhibit non-zero source impedance. At least for domestic consumers. their input rectifiers are the largTime est contributor to mains-current harmonic distortion. 16 Electronic Design . PFC harmonics also cause losses and dielectric stresses in factors less than unity? Part of the problem is economic. As the power lines effect on power lines. These applications impedance and voltage can range in scale from battery chargers for portable devices to current big-screen TVs. the average current is higher. Once the voltage crosses that point. the average 0923_EE_F2 inductor current is relatively low.com/RIGA_paper_27_JULY_04. In any event. causing conduction losses. Historically. in addition to overcurrents in machine all those superposed harmonic currents create measurable I2R and transformer windings. The first regulatory effort to control disIL VIN D1 VOUT Inductor current Peak inductor current Average inductor current (b) PFC controller Q1 C1 (a) Gating signal Critical conduction (“transition”) mode Continuous conduction mode 2. Actually. what’s actually so wrong with power isn’t sized to carry significant current. the supply draws current from the line when the input voltage exceeds the voltage on the filter capacitor. In ac-dc switching power supplies. Load with Where does that harmonic distortion come from? One comac-dc rectiﬁer Clipped voltage sine wave and cap as ﬁrst AC line mon misconception is that switching regulators cause harmonat the wall outlet power-conversion ic power-factor components. Power-factor correction (PFC) in ac-dc supplies consists of using a control circuit to switch a MOSFET so it draws current through an inductor in a way that fills in the gaps that would otherwise represent harmonics. When the PFC is operated in “critical conduction” or “transition” mode (a). In fact. one broad unlikely to appeal to state legislators. the current is only lim. and the volt-amperes reactive (VARs) were a net loss. The net effect is of a load current that is out of phase resistance of the diode that is forward-biased and the reactance with the line voltage and contains frequency components that exhibit skin of the capacitor that smoothes out the dc. rectiﬁer capacitor ﬁlter circuit In the steady state. while continuous mode results in power factors closer to unity. Whatever their phase relationships. resolving the situation on an engineering level is more practical than socking it definition of power factor is: to Joe Homeowner. they cumulatively represent an out-of phase current at the fundamental frequency. see losses as they’re drawn from the generator. 0923_EE_F1 cause some clipping distortion on the peaks of the voltage didn’t even record those currents. old mechanical power meters from the beginning. The wye ground conductor typically Whatever the cause. notably the third. tariffs for sinusoid.” by Basu. For a more detailed analysis. PFC can also be needed in any line-powered AC line Voltage AC line apparatus that uses ac-dc power conversion. aided and Line current drawn by abetted by the impedance of the power line itself. In fact. Cumulatively. and in any event. This creates a current waveform that includes all the odd 1. Harmonics get to be considered elements of power factor domestic consumers don’t permit charging for anything but because of their relationship to the power-line frequency. capacitors and cables. he has another reason to care. Transition mode is easier to achieve.EngineeringEssentials More broadly. where THD is total harmonic distortion. the high current peaks in power-company transformers that result in further losses. In terms of safety. can and do result in three-phase imbalance.pdf). As “real” power. 1). the power-line frequency’s current harmonics are produced when the load draws current from the power line harmonics of the power-line frequency (Fig.during the intervals when the line voltage is higher than the voltage on ited by the source impedance of the utility line as well as by the the filter capacitor. (http://boseresearch. to the home or workplace. That situation is likely to continue since “fixing” the tariffs is Fourier components. That’s the economic side of the story. Harmonics. mains power has been subject to interference the consumer paid for watts. if Joe’s home is an apartment. with current flowing in the ground conductor in a THE PROBLEM WITH Power Factor “wye” (Y) configuration. Another part has to do with safety. et al transmission and distribution lines. REGULATING PF Interestingly. they’re produced in the stage Time typical full-bridge rectifier and its filter capacitor. the utility delivered volt-amperes. When it is operated in “continuous conduction” mode (b). because the peak current is allowed to fall essentially to zero amps. the utility ate the expense of the losses. through miles of “PFC Strategies in light of EN 61000-3-2.
” (See the 0. and white paper for details. the current standards come out of Europe. the phase difference of each standards. (Classes A. the others can absorb the failed unit’s share of load. Its “Class D” requirements (the strictest) apply to personal computers. 80 Plus is a U. a supply that just ica. is based on 230-V single-phase and 230/400-V three-phase power at the wall-plug.9.8 utilities.3 0. the phase difference is 90°.6 In 2008.5 expanded to recognize higher-efficiency by “emulating an inductive-input filter 0. The U.S.7 0. the limits for Class D harmonic currents are laid down in terms of milliamps per watt consumed (Table 1). BELOW 20% LOAD One complaint about 80 Plus is that it does not set efficiency targets for very low load levels. the TI authors note that gram that subsidizes the extra cost of computer power supplies based on the basic definition of power factor as the ratio of the that achieve 80% or higher efficiency at low mid-range and average power in watts absorbed by a load from a voltage or peak outputs. Class D.9 for power factor.) What does the standard actually say? Under IEC 61000-3-2. Ironically. international standards IEC 555-2 “Harmonic injection into the AC Mains” and IEC 555-3 “Disturbances in supply systems caused by household appliances and similar electrical equipment .4 0. and current source to the product of RMS voltage appearing across 1. the load and the RMS current flowing in 0. the utilities pay $5 or $10 for simple full-wave bridge and drive it with Four phases 0. In the European Union. The amount of ripple reduction in multi-phase tuitously. initially using the Olymwith a large inductance value.726 is significantly less than 0. standard IEC/EN61000-3-2. it is theoretically possible to design a Two phases Three phases 0. Texas Instruments provides an interesting analysis of the issues in a white paper.3 pic medal colors of bronze. there are voluntary standards for North AmerSince 0.0 that exhibit a power factor of at least 0. “redundant” refers to the PFC schemes is a function of duty cycle.1 0. Of some further significance may be the conflict between specifying requirements for the individual components of harmonic distortion.” by Isaac Cohen and Bing Lu (http:// focus. but it isn’t when there are large numbers of computers in operations such as server farms. More recently (1978 and 1982). the expression for power factor reduces to: Awkwardly.7 every desktop computer or server sold. computer monitors.” sets current limits up to the 39th harmonic for equipment with maximum power-supply specs from 75 to 600 W. IEC61000-3-2. the processor’s power-saving modes tend to conflict with efforts to save power in the ac supply.9 Within territories served by participating it. the current limits have to be adjusted for 120/240-V mains voltages in North America. but they’re nearly universal. B. and China.) Like those standards. Making a few simplifications. Australia.Limits . Early in the paper.6 0.Part 3: Voltage fluctuations” were published.S.ti. was intended to keep uncontrolled arc-lamps from making incandescent lamps flicker. The new subcategories were meant shows that all harmonics above the 11th 0. ductor has addressed the issues of recRipple current reduction normalized to one phase of PFC Electronic Design Go To www. silver.” the authors say. and specifying a single value. as IEC 61000-3-2 does. While IEC61000-3-2 sets mandatory standards for supplies sold in the EU. all the commonly used activethat had moved ahead of the curve. There are related government regulations for power-line harmonics in Japan. “High Power Factor and High Efficiency – You Can Have Both. the British Lighting Clauses Act of 1899.) Nonetheless. This may seem like a trivial objection. and TV receivers./Canadian electric utility-funded rebate proJust to make things interesting. for desktop computers (later including servers) and laptops. In Table 2. the problem is a chimera. multiple supplies to deliver power to the phase is 360° divided by three.solid forms that can easily comply [with] both ating from a 230-V ac source and using three-phase design.Limits for harmonic current emissions (equipment input current ≤ 16 A per phase).0 0. Some systems may have up to six a four-phase design. a square wave and have it meet the 0. 0. The PFC circuits draw input-current wave0923_EE_F3 line represents a two-phase design.9. the 80 Plus program was power-factor Energy Star requirement 0. relative to the power rating on the nameplate.electronicdesign.4 power supplies.1 2) .8 0. GLOBAL DISHARMONY power supplies so if one fails.9 1. In a practice of server systems makers of oper.2 gold.5 0. In Like Texas Instruments. being a European-oriented standard. such as 0. 0.com/download/trng/docs/seminar/Topic_1_Cohen_ Lu. power tools.0 Duty cycle make it possible to offer larger consumer Ultimately.EngineeringEssentials turbances to the electrical grid. and C cover appliances.pdf). the authors calculate the power factor represented by the Class D harmonic levels specified by IED61000-3-2.9 0. In consequence. ON Semiconload.0 to help expand program branding and to exceed the IEC61000-3-2 limits. and lighting. as the higher levels of 80 Plus do. Department of Energy’s Energy Star Computer Specification includes “80 Plus” power-supply requirements meets the minimum requirement for the EU standard will fail Energy Star.2 0. “For3. which is 120°. and then adding platinum (Table a Fourier analysis of the square wave 0. “Electromagnetic compatibility (EMC) .Part 3-2 . as the title of the paper rebates for participating manufacturers suggests.com 17 . many of which may be in a standby or sleep mode at any given time. (Later they were updated to IEC1000 standards.
its ripple current has a Another issue with stating a PFC requirement directly.” mode. PFC controller (Fig. factor of 0. since heat losses from the two stages are spread over a wider VIN L1 D1 VOUT 18 Electronic Design . such as what might be used in APPROACHES TO UNITY POWER FACTOR telecom rectifiers or server front ends. This interleaved PWM operation reduces input and in a way that fills in the gaps that would output ripple currents. the company advised the Department of Energy that exter. To UCC28070 two-phase interleaved continuous-current mode understand it. two-stage external power supplies with an active-PFC lower power levels. and the conducted-EMI filtering is easier and less expensive. nal power supplies that meet the IEC61000-3-2 typically have The terms “critical” and “transition” reflect the fact that a power factor of 0.9 and yet will fail a given odd harmonic current and The circuit topology for CCM is like critical conduction therefore will not meet the IEC61000-3-2.levels as the higher currents magnify radiated and conducted ment would eliminate the single-stage topology that is one of electromagnetic interference (EMI) levels that critical conducthe most cost-effective ways of building highly efficient exter. the inductor is at a point rated output power. Texas Instruments’ UCC28070 0923_EE_F4 power-factor correction chip integrates two pulse-width FET to draw current through an inductor modulators operating 180° out of phase. and continuous conduction mode (CCM).0 Energy Star Requirements for External transition mode). “Comments operate in several modes: critical conduction mode (also called on Draft 1 Version 2. Applications explains. passive and active PFC and passive or active filtering. turn determines whether the inductor current (and the energy in pdf. M1 As noted above. Transition-mode operation “More specifically. at 100% of rated output power and 230-V can achieve power factors of 0. composite of the ac line current.” the paper cal. Solutions include higher power. otherwise represent harmonics.EngineeringEssentials Passive PFC involves an inductor on the power-supply input.85 or greater when measured at 100% of each time the current approaches 0 A. nal power supplies such as notebook adapters with a nameplate PFC CONTROLLER DESIGNS output power below 150 W. typically 600 W and below. ON Semiconductor cycle. To current T1 – sense input conduction losses. But unlike the simpler mode.The inductor always has current flowing through it and does not ciency. This also has thermal-management advantages. However. This is important at higher power typically greater than 0.e.” says. because it uses relatively few components. “The opposite is however not true. 4) . TI has an interesting solution for this. than in terms of individual harmonics. as well as conpossible that an external power supply can exhibit a power sumer electronics. but isn’t really practical for rea12 to 21 V + sons that include the necessary inductance. i.tion mode would have difficulty meeting.gov/ia/partners/ The differences lie in how fast the MOSFET switches. It opens the door to an interesting design question represented by TI and ON Semi. the cure power levels. 2). hence the term “continuous. it is limited to ac line.80. where its energy approaches zero. rather much lower peak-to-peak amplitude and does not go to 0 A. In a communication available online. it is possible to parallel two PFC stages to deliver is to increase the rectifier’s conduction angle. and possibility of resonance with the output filter capacitor. The basic PFC concept is fairly simple (Fig. let’s first look at actual PFC design approaches. has to do with design effi. the average current produces a higher-quality percent efficiency loss and in a substantially increased cost.energystar. which in prod_development/revisions/downloads/ON_Semiconductor. it is entirely include lighting ballasts and LED lighting. The proposed power-factor require. It is economifront end exhibit a power factor greater than 0. the necessary circuit modifications would result in a fewIn this case. This non-symmetrical curtransformer rent draw introduces harmonics of the ac line voltage on the line. The PFC controller can be designed to onciliation. Power Supplies (EPS)” at www. making it possible to achieve “For single-stage external power supplies the power factor is power factors near unity. Passive PFC looks simple. Since the discontinuous input-filter charging current creates The idea behind the design of the TI chip is that for higher the low power factor in switch-mode power supplies. the power-factor UCC28070 problem in ac-input switch-mode power To L2 current supplies arises because current is drawn D2 sense from the line only during parts of the acinput supply voltage waveform that rise above T2 From the dc voltage on the bulk storage (filter) current M2 capacitor(s).the inductor) approaches zero or remains relatively high. For a single-stage PFC topology to meet the proposed dump all of its energy at each pulse-width modulation (PWM) power-factor specification at 230-V ac line. The UCC28070 targets 300-W to multi-kilowatt power supplies. embodied in its Note the emphasis on single-stage.9. A control circuit switches a MOS4.9.” ON Semiconductor says.
ON Semiconductor’s NCL30001 employs a variable reference generator. 3). the ripple currents cancel. providing cost.33 kΩ PWM comparator + − 21. This output (VER80% 80% 80% Undefined 80 Plus Basic ROR) drives the PWM comparator through a 82% 85% 82% 81% 85% 81% Bronze reference buffer. The output of a reference generator is a rectified version of the input sine wave proportional Table 2: 80 Plus Efficiency Levels to the feedback (FB) and inversely proportional to the feedforward (VFF) values. The application often drives PFC controller design. area of the circuit board. That way. the number or physical size of the passive components can be smaller than in single-phase PFC. and EMI-filter complexity tradeoffs. the NCL30001 datasheet describes a simpler 3.0-V threshold.33 11 ON Semiconductor’s datasheet provides an instructive 3. It essentially needs 7 only one MOSFET.85/n 2.com 19 . due to the lower output ripple currents. which is intended for 12-V and higher LED lighting Harmonic Current Limits applications between 40 and 150 W.33 kΩ + 4 V Overload Latch S R Q AC in FB FB + Transient load detect + comparator − Ramp comp V-to-I V-to-I V-to-I + inverter Output driver DRV V SSKIP(TLD) Transconductance ampliﬁer + − AC error ampliﬁer Reference generator V CC Brownout V CC OK V FF V FF 0923_EE_F5 5. 87% 90% 87% 88% 92% 88% Gold Suitably compensated.electronicdesign. and one low-voltage output capacitor.30 3 approach that shrinks the front-end converter (ON Semi calls it 1. Relative While a typical LED lighting power supply might consist of a Absolute limit (A) Harmonic order (n) limit (mA/W) boost PFC stage that powers a 400-V bus followed by an isolated dc-dc converter. designs with more than two phases are common (Fig. the phase angles are distributed evenly. ON Semiconductor’s NCL30001 LED lighting controller. An ac 115-V internal non-redundant 230-V internal redundant Test type error amp forces the average current output Percent of 20% 50% 100% 20% 50% 100% of the current-sense amplifier to match the rated load reference-generator output. The disadvantage of simple parallel operation is higher input and output ripple currents.4 2. one low-voltage 0. 0. space.EngineeringEssentials V DD R + FB + − AC in skip V SSKIP(sync) comparator + − Soft-skip ramp Delay Start t SSKIP Clock DC max + V SSKIP FB skip comparator Terminate PWM skip comparator + − 21. this provides the duty90% 92% 89% 90% 94% 91% Platinum cycle control.25/n 13 to 39 description of the portion of the circuit shown in Figure 5. and a current shaping network. one magnetic element. Inputs to the reference generator include a scaled ac input signal (AC_IN) and feedforward input (VFF). and the PWM comparator sums VERROR and the instantaneous current 85% 88% 85% 85% 89% 85% Silver and compares the result to a 4. TI says that a better alternative is to interleave the two stages so their currents are 180° out of phase.9 1. a low-frequency voltage-regulation error amplifier. 5).14 5 the PFC preregulator) and the dc-dc converter into a single pow1.35 0.5 0. Electronic Design Go To www. combines CCM PFC and a (Power = 75 To 600 W) flyback step-down converter (Fig. In multiphase PFC. For Table 1: EN61000-3-2 Class D example.0 0. In fact. ramp compensation.40 9 output rectifier.77 er-processing stage with fewer components. In those cases.
and more. the primary means of heat transfer are through conduction to the PCB and by convection to the surrounding air. As the percentages show. Radiation. tire monitoring. the 20 Electronic Design . and manage thermal dissipation. Despite many new applications for semiconductors in the automotive industry. designers can provide an optimized design with fewer silicon test builds. radio. the device’s reliability is compromised over time. 40% from the bottom of the package. However. Semiconductor packaging serves to protect the die. The heat is then dissipated through the PCB into the surroundings. Heat transfer occurs via conduction. providing no direct thermal connection to the PCB. and it provides a good thermal conductor surface. 1. or radiation. Here. when present. which forces semiconductor providers to include more functions with higher power consumption. again). quickly moving the heat away from the die and out toward the larger system prevents highly concentrated areas of heat on the silicon. represents a minor portion of the heat transfer. in turn. from small. the current drive is for smaller assemblies with lower part counts. A common semiconductor package type in the auto industry is the exposed pad. This pad supports the die during fabrication. helps to deliver the best possible automotive designs. climate control. In the automotive safety industry. single-function transistors to complex power packages with more than 100 leads and specially designed heatsinking capabilities. depending on the application. thermal modeling has become an essential tool for the automotive industry. In leaded packages. Thermal Challenges Operation. package (Fig. leading to a quicker development cycle time. which is then soldered to the circuit board. 0708_EE_F1 Semiconductor Thermal Packaging The automotive electronics industry uses various semiconductor package types. we’ll focus on the semiconductor package’s ability to conduct heat away from the die. Typical operating temperatures for silicon die range from 105°C to 150°C. For automotive semiconductor packaging. The higher temperatures generated ultimately will affect reliability and. the die is mounted to a metal plate called the die pad. as well as thermal improvements at the page and system level.com Optimizing die layout and power early in the design cycle. provide electrical connection between the device and external passive components in the system. and approximately 2% from the top. The other 20% of the heat dissipates from the device leads and sides of the package. and comfort automotive systems rely heavily on semiconductors. metal diffusion is more prevalent and eventually the device can fail from shorting. For this discussion. or PowerPAD-style. PowerPAD-style package <1% ~20% ~80% Standard leaded package <2% ~40% ~58% 1. For very short durations. anti-theft systems. Less than 1% of the heat dissipates from the top of the package. Approximately 58% of the heat dissipates from the leads and sides of the package. three traditional areas still maintain individual environmental requirements: inside the vehicle cab. a silicon die can tolerate temperatures well above the published acceptable values. But by optimizing the die layout and power pulse timing early in the design cycle. 1). convection. The primary heat path runs down through the exposed pad. providing a direct thermal connection from the die to the PCB. A similar leaded package is the non-exposed pad package (Fig. W hy is it important to dissipate heat? For most semiconductor applications.EngineeringEssentials Thermal Modeling Takes The Heat Off Of Automotive Silicon Design Sandra Horton | TExas Instruments ti_sandrahorton@list. Due to this delicate balance between power needs and thermal limits. automotive safety. The bottom side of the die pad is exposed and soldered directly to the printed-circuit board (PCB). airbags. The die’s reliability depends greatly upon the amount of time that’s spent at the high temperatures. safety. They’re now common in body electronics. steering. passive entry. At higher temperatures. plastic fully surrounds the die pad. Exposed-pad-style packages conduct approximately 80% of the heat though the bottom of the package and into the PCB.ti. thermal dissipation is distinctly different between a standard leaded package and a PowerPAD-style package.
and antilock Electronic Design Go To www. eliminating material builds.7413 0.4149 3 larger die pads.3077 0. using simplified rather than detailed PCB copper routing.com 0708_EE_F3 21 . Variations such as 5. Regarding thermal challenges in terms of material proper20 ties. can be lowered 25°C by fusing several leads to the die pad. heat can quickly dissipate from the die to 5.6931 0.1553 5. For 0708_EE_F2 eight-lead small-outine IC (SOIC) packages. In addition. Thermal modeling software uses comma-separated variable (.4892 3. Plastic materials have very low thermal conductivity.366 Thermal modeling is also 143 6 1. In firewall applications.8303 2.5967 5.4214 2 5.0968 5. Temperatures for automotive environments versus other environments are typically worlds apart. modeling activity typically focuses on the thermal performance and design of a single device.0765 0. so they function as thermal insulators. three factors continue to challenge the automotive environment: high ambient temperatures. high power.0984 5.1657 3.2595 0. some cars now come with as many as 12 airbags. where electronics are located between the engine compartment and the vehicle’s cab. consumerelectronics temperature commonly resides at 25°C.2228 0.8512 6 1. Increased functionality demands plus concentrated multiple sources drive the die’s high power. Generally. from as low Temperature (ºC) panel firewall.7477 22 0. can all streamline the thermal model for fast solver times.4165 12 tion to the PCB.2632 5. or under the hood.0495 5.8321 0. increasing the thermal load on 2.7477 performance. and limited material thermaldissipation properties.71 2.csv) inputs to generate detailed die layout and ity of packaging materials show any potential hotspot locations on the die surface. System-level simplifications. or assuming chassis is at a fixed temperature for heatsinking. it’s no secret that there’s a concerted effort to reduce 103 cost in automotive assemblies.8499 0.5326 potential material changes in 140 1 0.9504 0.0874 2. On the other hand.2859 5. Plastic enclosures have the benefit of being cheaper to produce.3851 60 3. Thermal demands increase with the addition of more safety 141 features.9272 0. Semiconductor packaging design can be varied to allow for the optimal thermal dissipation depending on the application’s needs. such as power steering.0225 6. is a reduction in thermal performance. With exposed-pad packages like PowerPAD. or improved 4.4757 0.4756 0.electronicdesign.384 0. devices can be exposed to ambient temperatures up to 105°C. they will still deliver an accurate representation of the thermal impedance network. however.1511 4.3559 20 die pad design offer ways to 2. power levels of up to 100 W can be expected for short duration (~1 ms). electronics inside the passenger compartment of the car or panel applications will run at temperatures up to 85°C (see the table). Die temps for some automotive-application semiconductors can reach up to 175°C to 185°C for short periods of time.5 sequenced operation and create a much greater thermal design challenge compared to a single traditional airbag. this is the thermal shutdown limit for automotive devices. 20 No doubt. Temperature (ºC) Temperature (ºC) Why Modeling? Within the automotive semiconductor industry.5326 a device. die junction temperature the semiconductor device.288 7 1. with upper limits around 70°C. Careful simplifications can be assumed to obtain modeling data. Underhood applications require operation in an environment with ambient temperatures up to 125°C. Thermal considerations are especially important in safetyrelated systems.2471 0. multiple airbags require a 80. then. can vary widely.3666 2.EngineeringEssentials brakes.4407 120 the PCB.0759 4.6695 4. 61. in the range of 0.3601 improve a device’s thermal 146 1.2026 0.7201 0.3 The tradeoff for lower cost and reduced weight. that the changeover to plastic enclosures will limit a system’s heat dissipation. such as eliminating extraneous low-power devices from the model. They also weigh less.4923 0. better connec5.8499 0. Typically. Plastic materials are replacing metal modules and PCB enclosures.0006 0.226 1 0. Thermal conductiv3.7317 1. During deployment. In braking and airbag applications.6289 10 used to review the impact of 1 0. airbags. In conjunction.5018 0. Package-level thermal modeling makes it possible to review potential packaging design changes in advance without costly development and testing activity.9784 2. 0. Though airbags have been common in vehicles for longer than a decade.3 to 1 W/mK.7914 0.
of the non-critical low-power die structures.taining a level of accuracy. Texas Instruments’ policy is to run tation of the silicon die layout.performance too. and out and thermal-modeling software. This uneven power geometry simplification. small. background or quiescent power can be To aid in semiconductor package design. careful lab-based analysis can determine on a single.csv) inputs (Fig. system-level thermal modeling small areas on the die. conductivity of a particular material. In simple cases. there are four main used across the die’s surface to account for a large percentage types of thermal models: system level. including material properties. including copper layers and therresidual heating and possible thermal Firewall (between mal vias. Yet in semiconductor This allows for an easy transfer of information between die layapplications. For material properties. IC designer to identify the powered regions for inclusion in the Power losses in the board or other areas in the system may also thermal model. suming and costly. These highis important because it shows how a parpowered regions can lead to localized Maximum Ambient ticular device will perform in a specific heating regions. because The thermal-modeling engineer should work closely with the applied power on a device during operation can vary with time. The ideal thermal modeling flow begins months before In smaller and lower-pin-count devices. the thermal modeling engineer creates a thermal model significantly improve the overall junction temperature without based on this review.4 W/mK (thermal insulator) to more than 300 W/mK include any unique geometry. most die layouts have power in uneven patterns These correlation studies highlighted several areas of potential error. Once thermal-model results are complete. the die layout can be accurate system representation. or (good thermal conductor).Automotive thermal problems in which clusters environment temperature (°C) mary heatsink for most semiconducof medium power silicon products Inside car tor packages. yet still mainaddressing the system’s thermal needs and satisfying opera. power definition. helps balance product cost versus performance. these powered regions on the die can vary from two to three locations to several hundred. Using thermal modeling techniques metal connections like screws or rivets. simplifying the thermal model while still accounting for the device’s overall power. Compact models are less complex networks of thermal resisIn the semiconductor industry. 3). 105 engine and cab) Models can also aid in the placement mal model to accurately determine theror calibration of embedded thermal mal behavioral analysis. die level. the semiconductor industry targets thermal modeling For critical systems. Modeling Assumptions Die-level thermal analysis begins with an accurate represenVerification of all finite element analysis (FEA) modeling is highly recommended. 125 Under hood 22 Electronic Design . thermal modeling has become tance that provide a reasonable approximation of the thermal an early part of the concept testing and silicon die design pro. Other power components on thermal performance and operating temperatures. thin layers of material are commonly used. Here. Carefully note the power represented in the model. in thermal conductivity compared to the bulk value. However. For thermally critical devices. cess. review die layout and power losses for the device. TypiVerification Of Modeling cally. In some thermal software programs. Similarly. be grouped into larger regions. such as embedded heatsinks. often requires compact models. the PCB. tional requirements. pay close attention to to the assumptions made during modeling to ensure the most the power structure’s location on the die. very low-powered regions can impact the die surface’s true power. other methods can fabricating any die. though. Vehicle Applications conductor thermal modeling takes the Thermal modeling helps highlight Ambient PCB into account because it’s the pri. published values often show the bulk entered using comma-separated variable (. thermal modeling is instrumental in Simplifying the inputs from these packages. In the automotive semiconduc Device functionality frequently requires high power over tor arena. careful attention must be paid formance. the designer and modeling engineer review the data and tune the model to accurately reflect possible application scenarios. While no model will be a perfect distribution can be critical to the device’s overall thermal perduplication of a true system. depending on functionality. Types of Modeling in a thermal model. The IC designer and thermal engineer be used to improve thermal performance (Fig. assume that the power is evenly distributed across the silicon. Often. Forced airflow around the system and PCB can also play a role in the convective heat transfer from the system. Depending on the device’s the increased surface area of the material can cause a decrease complexity and the power level. fusing several of the package leads to the device’s die pad can Then. and die-level transient analysis. and across the die. However.EngineeringEssentials as 0. system’s physical measurements. The composition of the located in close proximity may cause 85 or panels PCB. 2). may play a large role in the system’s overall lab-based measurement of these systems may be time-con. automotive semisilicon.performance of these non-critical devices. nificantly hotter than the surrounding At a basic level. Furthermore. including any powered regions correlation studies comparing thermal-modeling results with a on the die. impacting the device’s operation. should be added to the therstress to the die under assessment. package level. which may be sigTemperatures For system. high-power device. For instance.
With this method. College Station.ti.5 the thermal system to account for only the Time (seconds) worst-case power. mK. or die thermal system to recover before more heat is applied. leads fused to the die pad. device power varies 85 with time and configurability. metal connection to chassis. more 2. Another is 1. e. or external heatsinking.com/automotive-ca. or mounting locations tions (Fig. PCB. direct attachment to a PCB such the “response with time” of varying power in multiple die loca. Analog Packaging Group at Texas Instruments. a device’s power-up or shutdown mode. 95 3ºC Ambient The aforementioned model types all temperature assume a constant dc power input.130 powered region on the die.course. includBoard 5ºC ing at the sensor location. Thermal vias located below the exposed pad of a device help Sandra Horton. Temperature (ºC) Electronic Design Go To www. package. When located away from the center of the powered 120 region. Download an application note for PowerPad at www. 115 Thermal models can be used to determine 110 the thermal gradient across the die.fully designing the die. These transient variations allow the Small enhancements to the system. Texas. References conductive heat paths. To learn more about thermal modeling and other automotive to provide more metal area for heat dissipation. the thermal load may become prohibitive. 4) . though.for many possible ways to minimize overall temperature. and thermal vias. such as by semiconductor devices.2 0. package. By carepotentially leads to dramatic improvements in final tempera. By designing 0 0. several areas on the die.25 0. Transient modeling is also helpful in viewing the full dura. visit www. locating powered regions device function. The simplest method is to assume a dc power source on the die. Yet due to layout 125 constraints.com/powlayers or denser copper layers on a PCB. Semiconductor of the device as a function of time. A second method inputs a device packages are designed to quickly move the heat away varying power source and then uses thermal software to deter. the device power remains at a low level for ered regions instead of square regions. a device’s tures. goals of thermal modeling for the automotive semiconductor This results in either a long lag time between power pulses so industry.com 23 . thermally connected erpad_slma002d-ca. Device and system limitations can eliminate some of thermal performance can be dramatically improved. Thermal response can vary with time across the surface of a semiconductor device. you can catch interactions for external heatsinks. In the case of an airbag sys.3 0. though. Silicon is a good thertem during deployment. this is often not possible.ti. or high power events are shared over improves a device’s reliability.1 0. good thermal practices tion of certain die operations that occur separate from normal include larger heat-dissipation areas. In actu4ºC 90 al operation. 0708_EE_F4 methods. using long and narrow powairbag deployment. such as braking actuation or away from the edges of the die. staggering power pulses to Design optimization and lower overall temperatures are the decrease instantaneous power will lower overall temperatures.2ºC 7ºC 100 difference between the hottest region and 8ºC 2ºC the sensor location. The third and most useful transient modeling style is to view higher conductivity materials. Lowering the operating die junction temperatures that the heat can dissipate. board. A semiconductor package can be improved thermally with mine the final steady-state temperature. copper planes. adding external heatsinks. In many automotive systems. Then the sensor 105 Die junction 6ºC is calibrated to account for the temperature 1. and providing adequate the bulk of the device’s lifetime. Transient thermal response can be 4.g.EngineeringEssentials Thermal response with time sensors on the die. the power pulse can reach very high mal conductor with a conductivity of approximately 117 W/ power for short durations. Ideally. the temperature sensor is unable to read the device’s full maximum temperature.35 0.4 0. Of tions. a temperature sensor is placed at the center of the highest.45 0. The semiconductor die itself allows between devices that may not be apparent under normal condi. Methods for boosting thermal performance include airflow.space between high-powered regions. In this regions across the die have been powered in a staggered fashion reviewed using one of several different case.05 0.as PowerPAD. For silicon circuit design and layout.15 0. then track the thermal response dissipation to the rest of the circuit board.electronicdesign. as well as speed holds a BSME from Texas A&M University. Improvements For transient power on a die.. Allowing the maximum amount of silicon around a powered region improves the device’s thermal dissipation. and system. the best way to lower temperature is to lower power. to quickly carry heat away from the device.from the die and to the larger system. these suggestions.
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