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Verilog Questions

Verilog Questions

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Published by Ashok A
Verilog Blocking; non-Blocking assignments
Verilog Blocking; non-Blocking assignments

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Published by: Ashok A on May 13, 2013
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01/04/2016

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Verilog blocking nonblocking assignments Ratnendra Pandey pandey at hotmail.com 1.

Verilog blocking and nonblocking statements must be used with care to av oid simulation mismatches in RTL and synthesized netlist. 2. Use blocking assignments in always block that are written to generate co mbinational logic. 3. Use nonblocking assignments in always block created to generate sequenti al logic. 4. Functionality and scheduling a. initial block is executed once b. always block is executed whenever the item in sensitivity list changes. always drives only reg or integer data type. Does not drive type wire. c. assign block is executed continuously. It has no sensitivity list. Used with wires, tristates, buffers etc. 5. Race condition in Verilog occurs if the end result of two or more assign ments scheduled to execute in same simulator time step would differ if the order or execution of the assignment is changed. In other words, if the end result o f two or more assignment scheduled to be executed in same simulation time step i s dependent on the order of execution of the statements, there will be race cond ition in verilog. 6. BLOCKING ASSIGNEMENTS: ( = ) an assignment must be executed completely befor e execution of trailing assignments. Order of execution affects the end result. Executed sequentially by simulators. 7. NONBLOCKING ASSIGNMENT ( <= ) order of execution does not affect end result. All nonblocking assignments scheduled in a time step are executed at once. Exec ution is concurrent. VERILOG CODING GUIDELINES (Taken from Nonblocking Assignments In Verilog Synthesis, Coding Styles That Kill by Clifford Cummings) 1. When modeling sequential logic, use nonblocking assignments 2. When modeling latches, use nonblocking assignments 3. When modeling combinational logic with an always block, use blocking ass ignments. 4. When modeling both sequential and combinational logic within same always block, use nonblocking assignments 5. Do not mix blocking and nonblocking assignments in the same always block . 6. Do not make assignments to the same variable from more than one always b lock.

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