You are on page 1of 4

VLSI LABORATORY

EXPERIMENT-6

AIM :Design,synthesize and stimulate the 2:4 Decoder circuit using Xilinx Software. ACTIVITY 1: Write VHDL code using Data Flow Modeling. entity decoder is Port ( i1,i2,enable : in std_logic; y0,y1,y2,y3 : out std_logic); end decoder; architecture Dataflow of decoder is begin y0<=(not i1)and(not i2)and(not enable); y1<=(not i1)and(i2)and(not enable); y2<=(i1)and(not i2)and(not enable); y3<=(i1 and i2)and(not enable); end Dataflow; RTL SCHEMATIC

T ime (ns i1 i2 enab y0 y1 y2 y3

0 0 0 0 1 0 0 0

100 1 0 1 0 0

200 1 0 0 0 1 0

300 1 0 0 0 1

400 0 0 1 0 0 0 0

500

600

700

800

900

1000

1100

1200

1300

1

Synthesis Result :
sarvraj singh(101096)

y3<='0'.i1.y1<='0'.y1<='1'.y1<='0'.VLSI LABORATORY Modeling Used Dataflow Component Used 2s15cs144-6 Number of Slices 1 out of 192 0% Propagation Delay 8. end decoder.y3<='0'.y2<='0'. end process.y1<='0'.y3 : out std_logic).enable) begin if(i0='0' and i1='0' and enable='0')then y0<='1'.y2<='0'. RTL SCHEMATIC T ime (ns i0 i1 enab y0 y1 y2 y3 0 0 0 0 1 0 0 0 100 1 0 1 0 0 200 1 0 0 0 1 0 300 1 0 0 0 1 400 0 0 1 0 0 0 1 500 600 700 800 900 1000 1100 1200 1300 1 sarvraj singh(101096) . end if.486ns ACTIVITY 2: Write VHDL code using Behavioral Modeling. architecture Behavioral of decoder is begin process(i0.y3<='1'. elsif(i0='0' and i1='1' and enable='0')then y0<='0'. elsif(i0='1' and i1='0' and enable='0')then y0<='0'. entity decoder is Port ( i0.y3<='0'.y1. y0.y2<='1'.y2<='0'.y2. elsif(i0='1' and i1='1' and enable='0')then y0<='0'.enable : in std_logic.i1. end Behavioral.

y3 : out std_logic). x4:andgate port map (s1. x7:andgate port map (s5. x8:andgate port map (s3.i1.486ns ACTIVITY 3: Write VHDL code using Structural Modeling.s1. entity decoder is Port ( i0.y3). begin x1:notgate port map (enable. x9:andgate port map (s7.s1).s5).s4. x6:andgate port map (s2. x11:andgate port map (s8.s8).y1.s3.s4). x10:andgate port map (i0.y0). x3:notgate port map (i1.i1. end Structural.y2).s3. end component.s2.s6. end component.y2. signal s1.s2.y1). x2:notgate port map (i0.i0.VLSI LABORATORY Synthesis Result : Modeling Used Behavioral Component Used 2s15cs144-6 Number of Slices 1 out of 192 0% Propagation Delay 8.b : in std_logic.s8 : std_logic. c : out std_logic).s7. RTL SCHEMATIC sarvraj singh(101096) . component notgate is Port ( a : in std_logic. y0.s1. x5:andgate port map (s4.s5. c : out std_logic). architecture Structural of decoder is component andgate is Port ( a.enable : in std_logic. end decoder.s2).s1.s7).s3).i1.

VLSI LABORATORY T ime (ns i0 i1 enab y0 y1 y2 y3 0 0 0 0 1 0 0 0 100 1 0 1 0 0 200 1 0 0 0 1 0 300 1 0 0 0 1 400 0 0 1 0 0 0 0 500 600 700 800 900 1000 1100 1200 1300 1 Synthesis Result : Modeling Used Structural Component Used 2s15cs144-6 Number of Slices 3 out of 192 1% Propagation Delay 8.486ns sarvraj singh(101096) .