What is HDL?
 hardware

description language describes the hardware of digital systems in textual form.  One can design any hardware at any level  Simulation of designs before fabrication  With the advent of VLSI, it is not possible to verify a complex design with millions of gates on a breadboard, HDLs came into existence to verify the functionality of these circuits.

Major digital design companies in Pakistan use Verilog HDL as their primary choice. verification.Most Commonly used HDLs  Verilog  Verilog HDL is commonly used in the US industry.  most commonly used in the design. and implementation of digital logic chips  VHDL (VHSIC (Very High Speed Integrated Circuits) hardware description language)  VHDL is more popular in Europe. Field-Programmable Gate Array is a type of logic chip that can be programmed.  commonly used as a design-entry language for field- programmable gate arrays. .

Most common are: Xilinx Veriwell Model Sim For Beginners Veriwell is good choice and is very user friendly. Xilinx and ModelSim are widely used. .Verilog Simulator There are many logic simulators used for Verilog HDL.

Data flow and Behavioral Level modeling . We will cover Gate level.Levels of Abstraction There are four different levels of abstraction in verilog: Behavioral /Algorithmic Data flow Gate level Switch level.

Getting started… A verilog program for a particular application consists of two blocks Design Block (Module) Testing Block (Stimulus) .

Design Block Design Methodologies: Two types of design methodologies  Top Down Design  Bottom Up Design inputs Design Block outputs .

We further divide the sub-block until we come to the leaf cells. we define the top level block and identify the sub-blocks necessary to build the top level block. .Top Down Design In Top Down design methodology. which are the cells which cannot be divided.

These cells are then used for high level block until we build the top level block in the design .Bottom Up Design In a Bottom Up design methodology. we build bigger blocks using these building blocks. we first identify the building blocks .

EXAMPLE FOUR BIT ADDER (Ripple carry adder) .

Module Representation Verilog provides the concept of module A module is a  Basic Building block in Verilog  Basic Building block in Verilog  It can be a single element or collection of lower design blocks A verilog code starts with module Syntax: module <module-name>(inputs. //Define inputs and outputs Every verilog program starts with the ………… keyword module and ends with the keyword ………… endmodule ………… endmodule . outputs).

e. two or more bits. e. output [3:0] C.g.  input a . then the definition will be: input [3:0] A. B.Input Output Definition  Once the module is defined at the start the inputs and outputs are to be defined explicitly. //4 bit inputs A3-A0 and B3-B0 . b //means there are 2 inputs of one bit each  If input or output is more than 1 bit i.

Levels of Abstraction .

inputs). inputs). . The basic gates and their syntax is as follows: and gate_name(output. These gates predefined in verilog library. xor gate_name(output.Gate Level Modeling In gate level modeling a circuit can be defined by use of logic gates. nor gate_name(output. inputs). inputs). not gate_name (output. xnor gate_name(output. or gate_name(output. inputs). inputs). nand gate_name(output. inputs).

Keyword assign is used followed by = Most common operator types are Operator Types Operator Symbol Arithmetic * / + ~ & | ^ ^~ or ~^ >> << {} Operation performed Multiply Divide Add Subract Bitwise negation Bitwise and Bitwise or Bitwise xor Bitwise xnor Shift right Shift left Concatenation Number of Operands Two Two Two two One Two Two Two two Two Two Any number Bitwise Logical Shift Concatenation Conditional ?: Conditional three .Data Flow Modeling Continuous assignment statement is used.

c}. y = a assign y = s1 ? ( s0 ? d : c ) : ( s0 ? b : a ). assign y = a & b. 6. assign w = a ^ b. 5. // y=x’ // y= ab //y= a b //shift right x by 1 //concatenate b with c e. //concatenate sum and cout 7.g. assign x = a + b. sum} = a + b + cin. b = 3’b101. assign y = ~ x . // 4×1 MUX .Examples 1. c =3’b 111 y = 101111 assign {cout . assign y = s ? b : a // 2×1 multiplexer when s = 1 . 2. 4. 3. assign y = x >> 1. assign y = {b. y = b when s = 0 .

Module Instantiation  Module instantiation is a process of connecting one module to another.  For example in a test bench or stimulus the top level design has to be instantiated .

 The design block has to be instantiated/called  It displays the output of the design based on the inputs.Testing Block (Stimulus)  In order to test your circuit a test bench code is to be written which is commonly called Stimulus. .

Example 2.Input AND Gate The Design and Stimulus blocks will be as follows: .

b) . //module definition input a. a. b. b). a.Design Block 1)Gate Level Modeling module practice (y. // one bit output and gate_1(y. // inputs(by default it takes 1 bit input output y. endmodule .

2) Data Flow Modeling module practice (y. output y. b). assign y = a & b. endmodule //module definition // by default it takes 1 bit input // one bit output . input a. a. b.

#5 a=1. b=0. #5 a=0. initial begin a=0. $monitor ($time. #5 a=1. #5 a=1. b). // terminate the simulation end initial begin $display("|%b| and |%b| = ". // stop the simulation #5 $finish. reg a. b=1. // display the simulation in the form of timing diagram endmodule . #5 $stop. b=1.Stimulus Block module stimulus. "|%b |" . b). //Instantiate the practice module practice p0(y. b. b=1. b=0. a. wire y. y). end //initial //$vw_dumpvars. a.

4 bit ripple carry adder Example #2: .

Full Adder .

b).b). or (c_out. c_in).a. //I/O Port declaration output sum. c_out. b.c2. c_in. and (c1. //Internal nets wire s1. c2. c1.s1.c_in). b. a.c1).Bottom Level module //Define a full adder module fulladder (sum. endmodule . input a. and (c2.a.c_in).s1. xor (sum. //full adder logic configuration xor ( s1. c_out.

fulladder fa1(sum[1]. //Instantiate four 1-bit full adder fulladder fa0(sum[0].c1.b[3]. //internal nets wire c1.b[1].b.a[2].c_out.TOP LEVEL MODULE //Define a 4 bit 4 adder module toplevel_fa(sum.b[2].c_in). b.c1).c2.c_out.b[0]. input [3:0] a.c3).a. fulladder fa3(sum[3].c3.c2. output c_out.a[1].a[3]. fulladder fa2(sum[2]. input c_in.c_in).c3.c2).a[0]. endmodule . //I/O port declaration output [3:0] sum.

wire c_out.c_in). . reg [3:0]a. //set up variables reg c_in.b.Test Bench (stimulus) //define stimulus toplevel module module stimulus.c_out. wire [3:0] sum. //Instantiate the toplevelmodule(ripple carry adder) call it tl toplevel_fa tl(sum.b.a.

b. sum). sum = %b". #2$display (“ a = %b. c_in = %b. sum). b = %b. c_in = %b. c_in = %b. c_in = 1'b0. #2$display (“ a = %b.//stimulate inputs initial begin a = 4'b0000. a. c_in = 1'b1. end endmodule . sum). c_in. sum = %b". b. sum = %b". c_in. b = 4'ha. a = 4'd1. b = 4'd2. a = 4'hf. a. b = %b. a. b = 4'b0010. #1 $display (“ a = %b. c_in = 1'b0. b. c_in. b = %b.

if. begin. if it is not shown in a colored font it means there must be some typing error. for. while etc… lower case. All the keywords are represented in colored font (either green. semicolon(. blue or red).) except for the statements (keywords) like initial. always. the keywords are written in .  All the verilog statements are terminated with a  Verilog is case sensitive i.Verilog Keywords  Verilog uses about 100 predefined keywords.e.

Continued……  Most common keywords are module.g // This is the first session of verilog /* this is the first session of verilog*/ . $stop. negedge. nor posedge . $print. xor. reset. endmodule input. output wire. clock. xnor. reg $display. if initial. for. case $vw_dumpvars. while. $finish  Single line comment is given by // ( two consecutive slash) and multi-line comment is given by /*……… */ for e. $monitor always. or. not. begin and. nard.

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