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mp8051.ppt

mp8051.ppt

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UNIT - II

FEATURES
           8-bit CPU optimized for control applications Extensive Boolean processing (Single-bit logic) capabilities 64K Program Memory address space 64K Data Memory address space 4K bytes of on-chip Program Memory 128 bytes of on-chip Data RAM 32 bidirectional and individually addressable 1/0 lines Two 16-bit timer/counters Full duplex UART 6-source/5-vector interrupt structure with two priority levels On-chip clock oscillator

PIN DETAILS P1 P0 RESET + _ P3 P2 XTAL .

BLOCK DIAGRAM Interrupt Control 4K ROM 128 RAM Timer 0 Timer 1 CPU OSC Bus Control 4 I/O Ports Serial Port TXD RXD P0 P1 P2 P3 .

ARCHITECURE All .

ARCHITECURE 1 .

ARCHITECURE 2 .

ARCHITECURE 3 .

MEMORY STRUCTURE External 60K 64K External SFR 64K EXT EA = 0 INT EA = 1 4K 128 Data Memory Program Memory .

INTERNAL RAM STRUCTURE Inirect Direct Addressing Addressing Only Only SFR Direct & Indirect Addressing 128 Byte Internal RAM .

128 BYTE RAM General Purpose Area BIT Addressable Area 128 BYTE INTERNAL RAM Reg Bank 3 Reg Bank 2 Register Banks Reg Bank 1 Reg Bank 0 .

REGISTER BANK STRUCTURE Bank 3 Bank 2 R0 R1 R2 R3 R4 R5 R6 R7 R0 R1 R2 R3 R4 R5 R6 R7 Bank 1 Bank 0 R0 R1 R2 R3 R4 R5 R6 R7 R0 R1 R2 R3 R4 R5 R6 R7 Program Status Word .PSW CY AC F0 RS1 RS0 OV - P .

SFR F8 F0 E8 E0 D8 D0 C8 PSW Acc B FF F7 EF E7 DF D7 CF C0 B8 B0 A8 A0 98 90 88 80 IP P3 IE P2 SCON P1 TCON P0 TMOD SP TL0 DPL TL1 DPH TH0 TH1 PCON SBUF C7 BF B7 AF A7 9F 97 8F 87 .

III .UNIT .

TIMERS SERIAL PORT INTERRUPTS .

TIMERS SERIAL PORT INTERRUPTS .

TIMERS Timer 0 Mode 0 Mode 1 Mode 2 Mode 3 Timer 1 Mode 0 Mode 1 Mode 2 .

TIMER / COUNTER OSC ÷12 C /T  0 TL TH TF (1 Bit) C /T 1 (8 Bit) (8 Bit) T PIN TR Gate INT PIN INTERRUPT .

TIMER 0 OSC ÷12 C /T  0 TL0 TH0 TF0 C /T 1 T 0PIN TR0 Gate INT 0 PIN INTERRUPT x .

TIMER 0 – Mode 0 13 Bit Timer / Counter OSC ÷12 T 0PIN TR0 Gate INT 0 PIN X C /T  0 C /T 1 TL0 TH0 (5 Bit) (8 Bit) TF0 INTERRUPT Maximum Count = 1FFFh (1111111111111) .

TIMER 0 – Mode 1 16 Bit Timer / Counter OSC ÷12 T 0PIN TR0 Gate INT 0 PIN X C /T  0 C /T 1 TL0 TH0 (8 Bit) (8 Bit) TF0 INTERRUPT Maximum Count = FFFFh (1111111111111111) .

TIMER 0 – Mode 2 8 Bit Timer / Counter with AUTORELOAD OSC ÷12 T 0PIN TR0 Gate INT 0 PIN X C /T  0 C /T 1 TL0 (8 Bit) Reload TF0 INTERRUPT TH0 (8 Bit) Maximum Count = FFh (11111111) .

TIMER 0 – Mode 3 Two .8 Bit Timer / Counter OSC ÷12 T 0PIN TR0 Gate INT 0 PIN X C /T  0 C /T 1 TL0 (8 Bit) TF0 INTERRUPT OSC ÷12 TH0 (8 Bit) TF1 INTERRUPT TR1 .

TIMER 1 OSC ÷12 C /T  0 TL1 TH1 TF1 C /T 1 T1PIN TR1 Gate INT 1 PIN INTERRUPT .

TIMER 1 OSC ÷12 C /T  0 TL1 TH1 TF1 C /T 1 T1PIN TR1 Gate INT 1 PIN INTERRUPT Y .

TIMER 1 – Mode 0 13 Bit Timer / Counter OSC ÷12 T1PIN TR1 Gate INT 1 PIN Y C /T  0 C /T 1 TL1 TH1 (5 Bit) (8 Bit) TF1 INTERRUPT Maximum Count = 1FFFh (1111111111111) .

TIMER 1 – Mode 1 16 Bit Timer / Counter OSC ÷12 T1PIN TR1 Gate INT 1 PIN Y C /T  0 C /T 1 TL1 TH1 (8 Bit) (8 Bit) TF1 INTERRUPT Maximum Count = FFFFh (1111111111111111) .

TIMER 1 – Mode 2
8 Bit Timer / Counter with AUTORELOAD
OSC ÷12
T1PIN

TR1
Gate
INT 1 PIN

Y

C /T  0
C /T 1

TL1 (8 Bit)
Reload

TF1

INTERRUPT

TH1 (8 Bit)

Maximum Count = FFh (11111111)

SFRs Related to TIMER
TMOD
Gate C/Ť M1 M0 Gate C/Ť M1 M0

Timer 1

Timer 0

TCON
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Timers

Interrupt

TIMERS SERIAL PORT INTERRUPTS

Write to BUFFER S Q D CL SBUFF Zero Detector RXD O/P Start Shift TX Control CLK TX Clock TI Send Serial Port Interrupt RX Clock RI Receive Shift TXD Shift Clock RI REN RX Control Start 1 1 1 1 1 1 1 0 RXD I/P Input Shift Register Load to BUFFER SBUFF Read From BUFFER .

SERIAL PORT– Mode 0 The Serial Port in Mode-0 has the following features: • Serial data enters and exits through RXD • TXD outputs the shifl clock • 8 bits are transmitted / received • The baud rate is fixed at (1/12) of the oscillator frequency .

SERIAL PORT– Mode 0 .

SERIAL PORT– Mode 0 .

SERIAL PORT– Mode 1 The Serial Port in Mode-1 has the following features: • Serial data enters RXD • Serial data exits through TXD • On receive. the stop bit goes into RB8 in SCON • 10 bits are transmitted / received  Start bit (0)  Data bits (8)  Stop Bit (1) • Baud rate is determined by the Timer 1 over flow rate. .

SERIAL PORT– Mode 1 .

SERIAL PORT– Mode 1 .

the 9th data bit goes into RB8 in SCON • 11 bits are transmitted / received  Start bit (0)  Data bits (9)  Stop Bit (1) • Baud rate is programmable – (1/32) or (1/64) of the oscillator frequency .SERIAL PORT– Mode 2 The Serial Port in Mode-2 has the following features: • Serial data enters RXD • Serial data exits through TXD • 9th data bit (TB8) can be assign value 0 or 1 • On receive.

SERIAL PORT– Mode 2 .

SERIAL PORT– Mode 2 .

. the 9th data bit goes into RB8 in SCON • 11 bits are transmitted / received  Start bit (0)  Data bits (9)  Stop Bit (1) • Baud rate is determined by the Timer 1 over flow rate.SERIAL PORT– Mode 3 The Serial Port in Mode-3 has the following features: • Serial data enters RXD • Serial data exits through TXD • 9th data bit (TB8) can be assign value 0 or 1 • On receive.

SERIAL PORT– Mode 3 .

SERIAL PORT– Mode 3 .

SFRs Related to SERIAL PORT SCON SM0 SM1 SM2 REN TB8 RB8 TI RI PCON SMOD - - - GF1 GF0 PD IDL .

TIMERS SERIAL PORT INTERRUPTS .

EA • External interrupt type can be programmed  Edge triggered  Level Triggered .INTERRUPTS The Interrupt structure has the following features: • 6 sources / 5 vectored interrupts • Each interrupts can be individually programmable • Each interrupts can have two priority levels • Priority levels can be programmed • All interrupts can be masked by a single bit .

TIMER / COUNTER INT 0 IE0 TF 0 INT 1 IE1 INTERRUPT SOURCES TF1 TI RI .

TIMER / COUNTER IE Reg IP Reg High Priority Interrupt INT 0 0 IT 0 1 IE0 TF 0 0 INT 1 IT1 IE1 1 Interrupt Polling Sequence TF1 TI RI Individual Enable Global Disable Low Priority Interrupt .

SFRs Related to INTERRUPTS IE IP - EA - - ES ET1 EX1 ET0 EX0 - - PS PT1 PX1 PT0 PX0 Priority Within Level RI / TI LOW TF1 TR1 TF0 TF1 IE1 TF0 IE0 HIGH TCON TR0 IE1 IT1 IE0 IT0 .

.

MEMORY INTERFACING External RAM Interfacing :- P1 P0 Data EXT RAM MCS 51 P3 ALE P2 ALE Address WR RD RD WR .

MEMORY INTERFACING
External RAM Interfacing :D0

AD0

D CLK

Q

A0 D1

AD1

D
CLK

Q

A1 D2

AD2

D CLK

Q

A2 D3

AD3

D CLK

Q

A3

MEMORY INTERFACING
External ROM Interfacing :-

P1

P0

Instr

EA

EXT ROM
ALE

MCS 51
P3 ALE P2

EEPROM
Address

PSEN

CE

Instruction Set 5 Groups  Arithmetic Operation Group  Logical Operation Group  Data Transfer Group  Boolean Variable Manipulation Group  Program Branching Group .

Instruction Set 5 Groups  Arithmetic Operation Group  Logical Operation Group  Data Transfer Group  Boolean Variable Manipulation Group  Program Branching Group .

Arithmetic Operation Group ADD ADD ADD ADD A.@Ri A.Direct A.Rn A.#Data .

Rn A.Arithmetic Operation Group ADDC ADDC ADDC ADDC A.@Ri A.#Data .Direct A.

Direct A.Rn A.#Data .Arithmetic Operation Group SUBB SUBB SUBB SUBB A.@Ri A.

Arithmetic Operation Group INC INC INC INC A Direct Rn @Ri .

Arithmetic Operation Group DEC DEC DEC DEC A Direct Rn @Ri .

Arithmetic Operation Group INC MUL DIV DA DPTR AB AB A .

Instruction Set 5 Groups  Arithmetic Operation Group  Logical Operation Group  Data Transfer Group  Boolean Variable Manipulation Group  Program Branching Group .

Rn A.#Data .#Data Direct.@Ri A.A Direct.Logical Operation Group ANL ANL ANL ANL ANL ANL A.Direct A.

Logical Operation Group ORL ORL ORL ORL ORL ORL A.Direct A.@Ri A.#Data .A Direct.#Data Direct.Rn A.

#Data .A Direct.Logical Operation Group XRL XRL XRL XRL XRL XRL A.#Data Direct.Direct A.Rn A.@Ri A.

Logical Operation Group CLR A CPL A RL A RLC A RR A RRC A SWAP A .

Instruction Set 5 Groups  Arithmetic Operation Group  Logical Operation Group  Data Transfer Group  Boolean Variable Manipulation Group  Program Branching Group .

#Data .Direct Rn.Rn A.@Ri A.Direct A.Data Transfer Group MOV MOV MOV MOV MOV MOV MOV A.@Ri Rn.#Data Rn.

Direct Direct.A @Ri.#Data Direct.#Data .Rn Direct.Data Transfer Group MOV MOV MOV MOV MOV MOV MOV Direct.A @Ri.@Ri Direct.

Data Transfer Group MOV @Ri.@Ri MOVX @Ri.Direct MOV DPTR.A MOVX @DPTR.@A+PC MOVX A.#DATA16 MOVC A.@A+DPTR MOVC A.A .

@Ri .@Ri XCHD A.Data Transfer Group PUSH Direct POP Direct XCH A.Direct XCH A.Rn XCH A.

Instruction Set 5 Groups  Arithmetic Operation Group  Logical Operation Group  Data Transfer Group  Boolean Variable Manipulation Group  Program Branching Group .

Boolean Variable Manipulation Group CLR C CLR bit SETB C SETB bit CPL C CPL bit .

Boolean Variable Manipulation Group ANL ANL ORL ORL MOV MOV C.bit C.bit C./bit C.C ./bit C.bit bit.

rel .rel bit.rel bit.Boolean Variable Manipulation Group JC JNC JB JNB JBC rel rel bit.

Instruction Set 5 Groups  Arithmetic Operation Group  Logical Operation Group  Data Transfer Group  Boolean Variable Manipulation Group  Program Branching Group .

Program Branching Group ACALL LCALL RET RETI AJMP LJMP SJMP addr11 addr16 addr11 addr16 rel .

#Data.#Data.rel @Ri.rel .rel A.#Data.rel Rn.Program Branching Group JMP JZ JNZ CJNE CJNE CJNE CJNE @A+DPTR rel rel A.Direct.

rel NOP .Program Branching Group DJNZ Rn.rel DJNZ Direct.

IV .UNIT .

UNIT .IV .

8255 Programmable Peripheral Interface  24 Programmable I/O pins  Three Configurable Ports .B & C  BSR Mode  TTL Compatible .A.

8255 Programmable Peripheral Interface .

8255 Programmable Peripheral Interface .

.8255 Programmable Peripheral Interface A1 0 0 1 1 A0 0 1 0 1 Select PA PB PC Control reg.

8255 Programmable Peripheral Interface Control Word General D7 D6 D5 D4 D3 D2 D1 D0 Group A Mode Selection 00 = Mode 0 01 = Mode 1 1x = Mode 2 PortA 1 = Input 0 = Output PortC (Upper) 1 = Input 0 = Output BSR Mode Select 0 = BSR Mode Enabled 1 = BSR Mode Enabled Group B PortC (Lower) 1 = Input 0 = Output PortB 1 = Input 0 = Output Mode Selection 0 = Mode 0 1 = Mode 1 .

8255 Programmable Peripheral Interface Control Word – BSR Mode D7 D6 D5 D4 D3 D2 D1 D0 Bit Set/Reset X X X Not Used 1 = Set 0 = Reset Bit Select 000 = Bit 0 001 = Bit 1 010 = Bit 2 011 = Bit 3 100 = Bit 4 101 = Bit 5 110 = Bit 6 111 = Bit 7 0 BSR Mode Selected .

8255 Programmable Peripheral Interface Mode 0 :- .

8255 Programmable Peripheral Interface Mode 1 :- .

8255 Programmable Peripheral Interface Mode 2 :- .

6MHz  BCD or Binary Counting  Programmable Counting Modes  Single Supply Operations .2.8253 Programmable Interval Timer  3 Independent 16bit Counters  DC .

8253 Programmable Interval Timer Pin Diagram :- .

8253 Programmable Interval Timer Block Diagram :- .

8253 Programmable Interval Timer System Interface :- .

8253 Programmable Interval Timer Control Word SC1 SC0 RL1 RL0 M2 M1 M0 BCD Read / Load 00 = Counter Latching 01 = Read/Load MSB only 10 = Read/Load LSB only 11 = Read/Load LSB first then MSB Binary / BCD 1 = BCD 0 = Binary Mode Select 000 = Mode 0 001 = Mode 1 X10 = Mode 2 X11 = Mode 3 100 = Mode 4 101 = Mode 5 Select Counter 00 = Select Counter 0 01 = Select Counter 1 10 = Select Counter 2 11 = Illegal .

8253 Programmable Interval Timer Mode 0 :- .

8253 Programmable Interval Timer Mode 1 :- .

8253 Programmable Interval Timer Mode 2 :- .

8253 Programmable Interval Timer Mode 3 :- .

8253 Programmable Interval Timer Mode 4 :- .

8253 Programmable Interval Timer Mode 5 :- .

8279 Programmable Keyboard / Display Interface  Simultaneous Keyboard & Display Drive  Scanned Keyboard Mode  Scanned Sensor Mode  8-Character Keyboard FIFO  Duel 8 / 16 Numerical Display  R / L Entry 16 bit Display RAM  Mode Programmable From CPU  Programmable Scan Timing  Interrupt Output on Key Entry .

8279 Programmable Keyboard / Display Interface Pin Diagram :- .

8279 Programmable Keyboard / Display Interface Signal Diagram :- .

8279 Programmable Keyboard / Display Interface Block Diagram :- .

8279 Programmable Keyboard / Display Interface System Interface :- .

8251 Programmable Communication Interface Pin Diagram :- .

8251 Programmable Communication Interface Block Diagram :- .

8251 Programmable Communication Interface System Interface :- .

8251 Programmable Communication Interface Mode Instruction Format .

8251 Programmable Communication Interface Command Instruction Format .

V .UNIT .

1) Stepper Motor Control 2) Matrix Keyboard 3) Dynamic 7 Segment Display 4) Analog to Digital converter 5) DC Motor Control 6) LCD Display 7) Serial Data Transfer .

STEPPER MOTOR CONTROL        Stepper Motor Winding Diagram Specifications Rotation / Excitation methods Clockwise / Anti Clockwise Sequence Single & Multi Winding Excitation Driving unit Digital & Analog .

STEPPER MOTOR CONTROL W1 1 0 0 1 1 0 0 1 W2 1 1 0 0 1 1 0 0 W3 0 1 1 0 0 1 1 0 W4 0 0 1 1 0 0 1 1 .

STEPPER MOTOR CONTROL .

MATRIX KEYBOARD       General Keyboard Structure Adv & Disadv of General Keyboard Layout of Matrix Keyboard Scanning and Sense Lines Scan Sequence Key De-bounce Methods .

MATRIX KEYBOARD DRIVER Scan Lines Sense Lines 7 8 9 5 6 4 1 MATRIX KEYBOARD  0 # 2 3 .

MATRIX KEYBOARD Sense Lines RL2 RL1 RL0 SL0 Scan Lines 1 4 7  2 5 8 0 3 6 9 # SL1 SL2 SL3 .

MATRIX KEYBOARD
SL3 SL2 SL1 SL0 RL2 RL1 RL0
0 0 1 0 0 1 0 0 1 1 0 0 1 0 0 1 0

1 2 3 4 5
RL2 RL1 RL0 SL0 SL1

0 0 0 01

0 0 1 0

0 1 0 0

1 0 0 0

0 1 0 0 1 0 0

1 4 7 

2 5 8 0

3 6 9 #

1
0 0

0
0 1

0
1 0

6 7 8 9 
0

SL2 SL3

1

0

0

#

MATRIX KEYBOARD

MATRIX KEYBOARD

DYNAMIC 7 SEGMENT DISPLAY      Seven Segment Display Eight LEDs Two types – Common Anode & Common Cathode Dynamic Seven Segment Display Scan Sequence .

DYNAMIC 7 SEGMENT DISPLAY Seven Segment Display a f b gV e d dp c a b c d e f g dp Common .

DYNAMIC 7 SEGMENT DISPLAY .

DYNAMIC 7 SEGMENT DISPLAY .

DYNAMIC 7 SEGMENT DISPLAY .

i/p.ANALOG TO DIGITAL CONVERTER      ADC Working Types Applications Specifications – No of Bits. o/p etc .

ANALOG TO DIGITAL CONVERTER .

DIGITAL TO ANALOG CONVERTER .

DC MOTOR CONTROL     DC Motor Speed Control Methods Advantage of PWM Method Driving Circuit .

DC MOTOR CONTROL .

L/R Entry etc .LCD DISPLAY       Principle of LCD 16x2 LCD LCD Module – Driver & Screen RAM Character Molding Display Type – Cursor.

LCD DISPLAY .

LCD DISPLAY .

LCD DISPLAY .

1 = Read from LCD module Enable signal Data bus line 0 (LSB) 5 6 7 R/W E DB0 0/1 1.Pin number 1 2 3 4 Symbol Vss Vcc Vee RS Level 0/1 I/O I Function Power supply (GND) Power supply (+5V) Contrast adjust 0 = Instruction input. 1 = Data input 0 = Write to LCD module. 1->0 0/1 I I I/O 8 9 10 11 12 13 14 DB1 DB2 DB3 DB4 DB5 DB6 DB7 0/1 0/1 0/1 0/1 0/1 0/1 0/1 I/O I/O I/O I/O I/O I/O I/O Data bus line 1 Data bus line 2 Data bus line 3 Data bus line 4 Data bus line 5 Data bus line 6 Data bus line 7 (MSB) .

cursor On/Off (C) and blink of cursor position character (B).64mS 0 0 0 0 0 0 0 1 I/D S 40uS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 DL 1 S/C D R/L C * * B * * 40uS 40uS 40uS N F CGRAM address 40uS 0 0 1 DDRAM address 40uS 0 1 BF CGRAM / DDRAM address Reads Busy-flag (BF) indicating internal operation is being performed and reads CGRAM or DDRAM address counter contents (depending on previous instruction). DDRAM contents remains unchanged. Sets cursor move direction (I/D). Sets On/Off of all display (D). Sets the DDRAM address. CGRAM data is sent and received after this setting. DDRAM contents remains unchanged. 40uS . specifies to shift the display (S). Sets cursor-move or display-shift (S/C). Sets the CGRAM address.64mS 1. shift direction (R/L). 0uS 1 0 write data Writes data to CGRAM or DDRAM. 40uS 1 1 read data Reads data from CGRAM or DDRAM. These operations are performed during data read/write. Returns cursor to home position (address 0). Sets interface data length (DL). number of display line (N) and character font(F). DDRAM data is sent and received after this setting. Also returns display being shifted to the original position.Code Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description Executi on time Clear display Cursor home Entry mode set Display On/Off control Cursor/disp lay shift Function set Set CGRAM address Set DDRAM address Read busyflag and address counter Write to CGRAM or DDRAM Read from CGRAM or DDRAM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 * Clears display and returns cursor to the home position (address 0). 1.

LCD DISPLAY .

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